JPH11204777A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase gain while restraining varieties of a threshold and enable making characteristics of a subthreshold region excellent, in an FET having a double heterojunction. SOLUTION: A buffer layer 12 consisting of nondoped I-GaAs of 200 nm in thickness and relieves adverse effect (lattice defect, background carrier concentration, etc.), of a substrate 11 is formed on a main surface of the substrate 11 composed of GaAs. A first spacer layer 13 consisting of P-type p-Al0.2 Ga0.8 As of 8 nm in thickness and having carrier concentration of 1×10<18> cm<-3> and forms an energy barrier to a quantum well layer, and a first carrier supply layer 14 consisting of N-type n-Al0.2 Ga0.8 As of 10 nm in thickness and having carrier concentration of 4×10<18> cm<-3> , forms an energy barrier to the quantum well layer and supplies carriers are formed on the buffer layer 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a Schottky double heterojunction field effect transistor having no recess gate.

[0002]

2. Description of the Related Art A field effect transistor (hereinafter abbreviated as FET) having a double heterojunction containing GaAs in a semiconductor layer is composed of two layers facing each other with a quantum well layer in which carriers travel. Since it has a carrier supply layer, a higher electron density can be obtained as compared with a single heterojunction FET having only one carrier supply layer. Therefore, it is widely used as a high output device for a high frequency band such as a power amplifier of a mobile phone. I have.

Generally, these heterojunction FETs are formed on the main surface of an epitaxial growth substrate obtained by using a molecular beam epitaxy (MBE) method or the like. Where FE
In order to reduce the ohmic contact resistance of the source electrode and the drain electrode of T, a contact formation region, ie,
The uppermost layer of the epitaxial growth substrate is made of high concentration n-type or p-type.
Type ohmic contact layer, and the lower part of the gate electrode in the ohmic contact layer must be removed so that the gate electrode does not have parallel conduction in which current flows in parallel with the channel layer in the ohmic contact layer. Recess etching must be performed. However, the recess etching of the ohmic contact layer tends to cause variation in the film thickness of the recessed portion.
th varies and electrical characteristics are not uniform.

Therefore, in recent years, a double heterojunction FET having no recess gate formed in a recess portion has been developed.

Hereinafter, a conventional double hetero junction FET having no recess gate will be described with reference to the drawings.

FIG. 7A shows a conventional double heterojunction FE.
1 shows a cross-sectional configuration of an epitaxial growth substrate for forming T. The epitaxial growth substrate shown in FIG. 7A has a substrate 1 made of non-doped i-GaAs having a thickness of 200 nm on a main surface of a substrate 101 made of GaAs.
A buffer layer 102 for alleviating the lattice mismatch between the GaAs crystal of No. 01 and each crystal layer grown on the substrate 101, and a non-doped i-Al _0.2 Ga _0.8 As 2 nm-thick carrier supply layer, which will be described later. The first is to lattice match and generate an energy barrier for the quantum well layer described later.
Spacer layer 103 and n-Al _0.2 Ga _0.8 As having a thickness of 10 nm and an n-type carrier concentration of 2 × 10 ¹⁸ cm ^−3.
A first carrier supply layer 104 that generates an energy barrier for the quantum well layer and supplies carriers.
And a non-doped i-Al _0.2 Ga _0.8 having a thickness of 2 nm
A second spacer layer 105 made of As, which separates a doped layer and a non-doped layer to improve gain and generate an energy barrier for the channel layer;
The gain is divided into a quantum well layer 106 made of non-doped i-In _0.2 Ga _0.8 As m and having carriers traveling therethrough, and a doped layer and a non-doped layer made of non-doped i-Al _0.2 Ga _0.8 As having a thickness of 2 nm. And a third spacer layer 107 which generates an energy barrier for the quantum well layer 106 and an n-Al _0.2 Ga _0.8 layer having a thickness of 20 nm and an n-type carrier concentration of 2 × 10 ¹⁸ cm ^−3.
A second carrier supply layer 108 made of As, which generates an energy barrier for the quantum well layer 106 and supplies carriers, and a non-doped i-GaAs having a thickness of 5 nm.
The gate contact layer 109 made of s and having a Schottky contact with the gate electrode is sequentially epitaxially grown.

FIG. 7B shows a sectional structure of a double hetero junction FET using the epitaxial growth substrate shown in FIG. 7A. As shown in FIG.
The gate electrode 11 is formed on the upper gate contact layer 109.
0 is selectively formed, and the gate contact layer 10
A source electrode 111 and a drain electrode 112, which are ohmic electrodes, are selectively formed in a region of the gate electrode 110 on the side of the gate electrode 110 in the gate length direction. Further, in a region below the source electrode 111 and the drain electrode 112 on the substrate 101, an ohmic contact region 113 formed by ion-implanting silicon (Si) so as to reach the buffer layer 102 is formed. On the substrate 101, an insulating film 114 made of a silicon oxide film is formed over the entire surface except for the upper surfaces of the source electrode 111 and the drain electrode 112.

As described above, the ohmic contact region 1
Since the gate electrode 13 is formed using the ion implantation method, the recess etching is not used for forming the gate electrode 110, so that the variation in the threshold voltage Vth can be extremely reduced.

Also, since the buffer layer 102 is made of the same material as the first spacer layer 103 and the carrier supply layer 104 and uses i-GaAs instead of the normally used non-doped i-AlGaAs, When the contact region 113 is formed, i-GaAs becomes i-A
Since the activation rate of Si ions is higher than that of lGaAs, ohmic contact resistance is reduced, and as a result, an FET with improved gain can be realized.

The ion implantation of Si ions into AlGaAs is described in, for example, S.I. Adachi, "
Si-ion implantation InGaAs
sand Al _x Ga _1-x As ”, J. Appl. ph
ys. 63 [1], 64, (1988) shows the details.

[0011]

However, in the conventional double heterojunction FET, the thickness of the first spacer layer 103 made of i-AlGaAs generally depends on the thickness of each crystal layer and the carrier concentration. When the voltage value of the gate voltage Vg approaches the threshold voltage Vth in the case where is less than or equal to 10 nm, as shown in the current-voltage characteristics of the FET in FIG. 8, the sub-threshold region A (Vg ≒ Vth)
In this case, there is a problem that a leakage current occurs between the drain and the source, and the sub-threshold characteristic is not good. That is, as shown in FIG.
It can be seen that the transconductance gm is small in the sub-threshold region A, and the transconductance gm is rapidly increased in a region where the gate voltage Vg is higher than the threshold voltage Vth (Vg> Vth). Since the gate voltage Vg when the magnitude of the transconductance gm changes depends on the thickness and the impurity concentration of each crystal layer of the epitaxial growth substrate, even if the gate voltage Vg is a region away from the sub-threshold region A (Vg> Vth). The case where the transconductance gm becomes small occurs. In this case,
If the gate voltage is not used in a region (Vg >> Vth) much higher than the threshold voltage Vth, a sufficiently large transconductance gm cannot be obtained, so that the thickness of the first spacer layer 103 is set to 10 nm or more. It is necessary to

On the other hand, when the thickness of the first spacer layer 103 made of i-AlGaAs is 10 nm or more, as shown in FIG. 9, the sheet resistance of the first spacer layer 103 included in the ohmic contact region 113 is 300 Ω /. □, there is a problem that the gain in the high frequency region of the FET is greatly reduced and the power efficiency is also deteriorated.

In view of the above problems, an object of the present invention is to improve gain while improving characteristics of a sub-threshold region while suppressing variations in threshold values.

[0014]

In order to achieve the above object, the present invention provides a buffer layer and a first layer in contact with the buffer layer.
Is provided with a p-type conductive layer on the junction surface with the barrier layer.

A first semiconductor device according to the present invention comprises: a buffer layer formed on a substrate; a first barrier layer formed on the buffer layer and having a larger energy band gap than the buffer layer; A quantum well layer formed on the first barrier layer, a second barrier layer formed on the quantum well layer, an ohmic electrode selectively formed on the second barrier layer, An ohmic contact region formed below the ohmic electrode on the substrate and reaching the buffer layer; the first barrier layer comprises a p-type spacer layer and an n-type carrier supply layer formed sequentially on the buffer layer. have.

According to the first semiconductor device, since the ohmic contact region reaching the buffer layer is provided in the region below the ohmic electrode on the substrate, the recess structure is not required when forming the gate electrode.

Further, since the first barrier layer has a p-type spacer layer and an n-type carrier supply layer formed sequentially from the buffer layer side, the first barrier layer has a p-type spacer layer and an n-type carrier supply layer. Since a pn junction including the n-type carrier supply layer is formed, a barrier for the built-in potential due to the pn junction is formed in the first barrier layer. As a result, the first
Of the conduction band at the interface between the barrier layer and the buffer layer can be made higher than the Fermi level.

In the first semiconductor device, the buffer layer is made of GaAs, and the barrier layer is made of AlGaAs or InGa.
Preferably, the quantum well layer is made of P and the quantum well layer is made of InGaAs or GaAs.

In the first semiconductor device, the thickness of the spacer layer is preferably 10 nm or less.

A second semiconductor device according to the present invention includes a buffer layer formed on a substrate, a first barrier layer formed on the buffer layer and having a larger energy band gap than the buffer layer, A quantum well layer formed on the first barrier layer, a second barrier layer formed on the quantum well layer, an ohmic electrode selectively formed on the second barrier layer, An ohmic contact region formed in the substrate below the ohmic electrode and reaching the buffer layer, wherein the buffer layer has p-type conductivity at least on the side in contact with the first barrier layer.

According to the second semiconductor device, since the ohmic contact region reaching the buffer layer is provided in the region below the ohmic electrode on the substrate, the recess structure is not required when forming the gate electrode.

Further, since at least the side of the buffer layer that contacts the first barrier layer has p-type conductivity, the Fermi level of the buffer layer is located closer to the valence band side of the band gap than in the case of non-doping. Therefore, the lower end of the conduction band at the interface between the first barrier layer and the buffer layer can be higher than the Fermi level.

In the second semiconductor device, the buffer layer is made of GaAs, and the barrier layer is made of AlGaAs or InGa.
Preferably, the quantum well layer is made of P and the quantum well layer is made of InGaAs or GaAs.

In the second semiconductor device, the spacer layer preferably has a thickness of 10 nm or less.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION The inventors of the present application have studied various reasons why the conventional subhetero-junction FET having no recess gate has poor subthreshold characteristics, and found the following problems.

That is, the energy level of the conventional double hetero junction FET shown in FIG.
As shown in ((b) is an enlarged view of (a)), the first spacer layer 103 is made of i-Al _0.2 Ga _0.8 As, and the buffer layer 102 is made of i-GaAs. It becomes a heterojunction. Therefore, the joining surface 201
Lower E _C of the conduction band in the cases located below the Fermi level E _F occurs. As a result, some of the carriers in the first carrier supply layer 104, ie, some of the electrons, seep out to the buffer layer 102 side, and the seeping out electrons become a drain-source leakage current in the sub-threshold region, so that the sub-threshold characteristic is obtained. Gets worse.

Therefore, the double hetero junction F in the present application is
In ET, a p-type conductive layer (spacer layer) is provided on the junction surface between the buffer layer and the first barrier layer in contact with the buffer layer, and the energy level of the junction surface 201 is changed to the Fermi level E.
_F , the first carrier supply layer 1
This suppresses carriers that seep from the buffer layer 102 into the buffer layer 102.

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1A shows a sectional structure of an epitaxial growth substrate for forming a double hetero junction FET as a semiconductor device according to the first embodiment of the present invention, and FIG. 2) shows a cross-sectional configuration of a double heterojunction FET using the epitaxial growth substrate shown in FIG.

The epitaxial growth substrate shown in FIG. 1A is formed on a main surface of a substrate 11 made of GaAs by, for example, the MBE method.
A buffer layer 12 made of GaAs, which alleviates the adverse effects (such as lattice defects and background carrier concentration) of the GaAs crystal of the substrate 11, a thickness of 8 nm, and a p-type carrier concentration of 1 × 10 ¹⁸ cm ⁻³ ; , first as a p-type spacer layer mole fraction ratio of AlAs to generate energy barrier for the quantum well layer described later with achieving p-Al _0.2 Ga _0.8 carrier supply layer described later consists as lattice matched 0.2 Spacer layer 13 and n-Al _0.2 Ga having a thickness of 10 nm and an n-type carrier concentration of 4 × 10 ¹⁸ cm ^−3.
_A first carrier supply layer 14 of _0.8 As, which generates an energy barrier for the quantum well layer and supplies carriers, and a non-doped i-Al _0.2 G layer having a thickness of 2 nm.
a _0.8 As, a second spacer layer 15 that separates a doped layer from a non-doped layer to improve electron mobility and generate an energy barrier for the channel layer, and a thickness of 15 nm and a molar fraction of InAs of 15 nm. A quantum well layer 16 made of _0.2 non-doped i-In _0.2 Ga _0.8 As and in which carriers travel, and a non-doped i layer having a thickness of 2 nm;
A third spacer layer 17, which is made of -Al _0.2 Ga _0.8 As and separates a doped layer and a non-doped layer to improve electron mobility and generate an energy barrier for the quantum well layer 16; a second carrier supply layer 18 supplies a carrier with a carrier concentration of the mold to produce an energy barrier to 2 × 10 ¹⁸ cm ^-3 of n-Al _0.2 Ga _0.8 quantum well layer 16 made of as, 5 nm thick Anti-oxidation layer 1 made of non-doped i-GaAs and having a Schottky contact with the gate electrode to prevent oxidation of the second carrier supply layer 18 and improve gate breakdown voltage.
9 are sequentially grown epitaxially.

Here, as shown in FIG. 1A, the quantum well layer 16 is formed of a first barrier layer comprising a first spacer layer 13, a first carrier supply layer 14, and a second spacer layer 15. 21 and a second barrier layer 22 composed of a third spacer layer 17 and a second carrier supply layer 18 to form a double hetero junction, and the first barrier layer 21 composed of AlGaAs and The energy band gap of the second barrier layer 22 is larger than the energy band gap of the buffer layer 12 made of GaAs.

Hereinafter, a method for manufacturing a double heterojunction FET using the epitaxially grown substrate configured as described above will be described.

As shown in FIG. 1B, first, the substrate 11
After depositing a conductor film made of tungsten silicide (WSi), which is a high melting point metal, over the entire surface of the oxidation prevention layer 19, the conductor film is selectively etched, and Then, a gate electrode 31 is formed.

Next, a silicon oxide film (S) is formed over the entire surface of the oxidation prevention layer 19 and the gate electrode 31 on the substrate 11.
After depositing an insulating film 32 made of iO _x ), ion implantation is performed on the source / drain formation region on the substrate 11 so that Si ions, which are n-type impurity ions, reach the buffer layer 12. Thereafter, an annealing protective film made of WSi is deposited on the entire surface of the substrate 11, and the substrate 11 exposed to a hydrogen atmosphere is annealed at 750 ° C. for 30 seconds using a hot plate annealing method. By activating the implanted Si ions, an ohmic contact region 33 is formed on the substrate 11 in the gate length direction.

Next, an opening for exposing the upper surface of the ohmic contact region 33 is formed by etching the source / drain formation region of the insulating film 32, and an ohmic metal film is deposited on the opening to form an argon gas. The substrate 11 exposed to the atmosphere is subjected to a heat treatment at a temperature of 450 ° C. for 15 minutes to form a source electrode 34 and a drain electrode 35 on the upper surface of the ohmic contact region 33 of the substrate 11.
Are formed respectively.

In this way, it is possible to form a double heterojunction FET having no recess gate, which causes a large variation in the threshold voltage Vth.

In the present embodiment, the antioxidant layer 19 is provided on the uppermost layer in contact with the gate electrode 31 on the epitaxial growth substrate, but the antioxidant layer 19 may not be provided.

As described above, according to the present embodiment, the first
In the barrier layer 21, a first spacer layer 13 made of _{p-Al 0. 2 Ga 0.8 As} , n-Al 0.2 Ga 0.8 A
The first carrier supply layer 14 made of s forms a pn junction. As a result, as shown in the energy level diagrams of FIGS. 2A and 2B, a built-in potential (diffusion potential) is generated in this pn junction, and thus the lower end E of the conduction band on the first spacer layer 13 side is generated. _C increases by this built-in potential. As a result, the gate electrode 31
When the gate voltage Vg applied to the first spacer layer 13 is about the threshold voltage Vth, the thickness of the first spacer layer 13 is set to 10 nm.
In the following, if the p-type impurity concentration of the first spacer layer 13 is optimized, the energy level of the bonding surface 51 between the buffer layer 12 and the first spacer layer 13 at the lower end E _C of the conduction band can be reduced. it can be higher than the Fermi level E _F. Here, FIG. 2B is an enlarged view of FIG. 2A in the y-axis direction.

Accordingly, the amount of carriers that seeps out of the first carrier supply layer 14 to the buffer layer 12 side can be suppressed to a negligible level. Therefore, as shown in the current-voltage characteristics of the FET according to this embodiment in FIG. It can be seen that the sub-threshold characteristic is improved and the leakage current between the drain and the source is reduced in the sub-threshold region. Thus, the transconductance gm of the subthreshold region is improved.

FIG. 4 shows a drain current-gate voltage (Ids-Vg) curve of the double heterojunction FET of this embodiment and a conventional double heterojunction FET. In FIG. 4, the gate voltage of the FET of the present invention shown by curve 1 is 0V.
Although the drain current stops flowing in the vicinity, on the other hand, it can be seen that the conventional FET shown by curve 2 has a leakage current of several hundred mA even in the region where the gate voltage is 0 V or less.

As shown in FIGS. 1A and 1B, the sub-threshold characteristic can be improved while the thickness of the first spacer layer 13 made of p-Al _0.2 Ga _0.8 As is kept at 10 nm or less. Therefore, the sheet resistance of the first spacer layer 13 can be set to a sufficiently low value of 300 Ω / □ for practical use, so that the gain does not decrease even in a high frequency region.

As described above, the double heterojunction FET according to the present embodiment can have a high gain even in a high frequency region, and a high power efficiency can be realized by the high gain.

In this embodiment, InGaAs is used for the quantum well layer. However, GaAs may be used.
The first and second barrier layers 21 and 22 are made of AlGaAs.
Was used, but InGaP may be used instead.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 5A shows a cross-sectional structure of an epitaxial growth substrate for forming a double heterojunction FET as a semiconductor device according to a second embodiment of the present invention, and FIG. 2) shows a cross-sectional configuration of a double heterojunction FET using the epitaxial growth substrate shown in FIG.

The epitaxial growth substrate shown in FIG. 5 (a), for example, by using the MBE method, on the main surface of the substrate 11 made of GaAs, the carrier concentration of the p-type in the 200nm thickness of 1 × 10 ¹⁸ cm ^- Substrate 11 composed of ³ p-GaAs
A buffer layer 42 for alleviating the adverse effects (such as lattice defects and background carrier concentration) of the GaAs crystal, and a non-doped i-Al _0.2 Ga _0.8 As layer having a thickness of 2 nm to achieve lattice matching with a carrier supply layer described later. A first spacer layer 43 for generating an energy barrier for a quantum well layer to be described later; and a quantum well layer comprising n-Al _0.2 Ga _0.8 As having a thickness of 10 nm and an n-type carrier concentration of 2 × 10 ¹⁸ cm ^−3. The first carrier supply layer 14 that generates an energy barrier and supplies carriers and the non-doped i-Al _0.2 Ga _0.8 As layer having a thickness of 2 nm is divided into a doped layer and a non-doped layer to separate the electron mobility. And a second spacer layer 15 for improving energy dissipation and generating an energy barrier for the channel layer, and having a thickness of 15 nm and a molar fraction of InAs. .2 non-doped i-an In
A quantum well layer 16 made of _0.2 Ga _0.8 As, in which carriers travel, and a non-doped i-Al _0.2 G layer having a thickness of 2 nm;
A third spacer layer 17 made of a _0.8 As, which separates a doped layer from a non-doped layer to improve electron mobility and generates an energy barrier for the quantum well layer 16.
And an n-type carrier concentration of 4 × 10 ¹⁸ with a thickness of 20 nm
a second carrier supply layer 18, which is made of n-Al _0.2 Ga _0.8 As cm ⁻³ and generates an energy barrier for the quantum well layer 16 and supplies carriers, and has a thickness of 5 nm.
A non-doped i-GaAs layer, which is in Schottky contact with the gate electrode, prevents oxidation of the second carrier supply layer 18 and improves the gate withstand voltage, and an oxidation prevention layer 19 is sequentially epitaxially grown.

The double heterojunction FET shown in FIG.
Is manufactured using the same method as that of the first embodiment, and a gate electrode 31 made of WSi is selectively formed on an oxidation preventing layer 19 on a substrate 11. A source electrode 34 and a drain electrode 35, which are ohmic electrodes, are selectively formed in a region on the side of the gate electrode 31 in the gate length direction. Further, the source electrode 34 and the drain electrode 35 on the substrate 11
In the lower region of FIG.
Ohmic contact region 33 implanted with ions
In addition, an insulating film 32 made of a silicon oxide film is formed on the entire surface of the substrate 11 except for the upper surfaces of the source electrode 34 and the drain electrode 35.

As described above, the ohmic contact region 3
Since the gate electrode 3 is formed by using the ion implantation method, recess etching is not used for forming the gate electrode 31, so that variation in the threshold voltage Vth can be extremely reduced.

In this embodiment, the oxidation preventing layer 19 is provided as the uppermost layer in contact with the gate electrode 31 on the epitaxial growth substrate. However, the oxidation preventing layer 19 may not be provided.

As described above, according to the present embodiment, p-
GaAs buffer layer 42 and first barrier layer 21
And the first spacer layer 43 made of i-Al _0.2 Ga _0.8 As form a hetero junction. As shown in the energy level diagrams of FIGS. 6A and 6B, the buffer layer 4
Because 2 is doped p-type, in comparison with the case of using a non-doped i-GaAs buffer layer 42, as the Fermi level E _F of the buffer layer 42 is located at the upper end E _V side of the valence band Become. As a result, when the gate voltage value Vg applied to the gate electrode 31 is about the threshold voltage Vth, the p-type impurity concentration of the buffer layer 42 is reduced even when the thickness of the first spacer layer 43 is set to 10 nm or less. be optimized, it can be higher than the Fermi level E _F lower end Ec of the conduction band at the bonding surface 51 of the buffer layer 42 and the first spacer layer 43. Here, FIG.
It is the figure which expanded (a) to the y-axis direction.

Therefore, the amount of carriers that seeps out of the first carrier supply layer 14 to the buffer layer 42 side can be suppressed to a negligible level. As in the first embodiment, the current-voltage of the FET shown in FIG. As shown in the characteristics, the sub-threshold characteristic is improved, and the leakage current between the drain and the source is reduced in the sub-threshold region. Thus, the transconductance gm of the subthreshold region is improved.

As shown in FIGS. 5A and 5B, the sub-threshold characteristic can be improved while the thickness of the first spacer layer 43 made of i-Al _0.2 Ga _0.8 As is kept at 10 nm or less. Therefore, the sheet resistance of the first spacer layer 43 can be set to a sufficiently low value of 300Ω / □ for practical use, so that the gain does not decrease even in a high frequency region.

In the present embodiment, the entire buffer layer 42 having a high activation rate of Si ions in the ohmic contact region 33 is p-GaAs, but the buffer layer 42 is bonded to the first spacer layer 43. A p-GaAs layer on the side of the junction to be formed, and an i-type layer below the p-GaAs layer.
A stacked structure having a GaAs layer may be used.

As described above, the double heterojunction FET according to the present embodiment can have a high gain even in a high frequency region, and a high power efficiency can be realized by the high gain.

In this embodiment, InGaAs is used for the quantum well layer. However, GaAs may be used.
The first and second barrier layers 21 and 22 are made of AlGaAs.
Was used, but InGaP may be used instead.

[0056]

According to the first and second semiconductor devices of the present invention, the lower end of the conduction band at the interface between the first barrier layer and the buffer layer can be made larger than the Fermi level. Carriers that leak from the barrier layer to the buffer layer side can be suppressed, so that the subthreshold characteristics can be improved.

In the first and second semiconductor devices, the buffer layer is made of GaAs, the barrier layer is made of AlGaAs or InGaP, and the quantum well layer is made of InGaAs or G.
The use of aAs ensures a double heterojunction FET with improved subthreshold characteristics.

In the first and second semiconductor devices, if the thickness of the spacer layer is 10 nm or less, the sheet resistance can be made sufficiently small, so that the gain does not deteriorate even in a high frequency region. .

[Brief description of the drawings]

FIG. 1A is a sectional view showing a structure of an epitaxial growth substrate for forming a semiconductor device according to a first embodiment of the present invention. FIG. 2B is a configuration sectional view illustrating the semiconductor device according to the first embodiment of the present invention.

FIG. 2A is a diagram illustrating an energy level of the semiconductor device according to the first embodiment of the present invention. (B) is (a)
FIG. 3 is an enlarged view in the y-axis direction of FIG.

FIG. 3 is a graph showing a characteristic curve of drain current-drain voltage in the semiconductor devices according to the first and second embodiments of the present invention.

FIG. 4 is a graph comparing the drain current-gate voltage characteristic curves of the semiconductor device according to the first and second embodiments of the present invention and a conventional semiconductor device.

FIG. 5A is a configuration sectional view showing an epitaxial growth substrate for forming a semiconductor device according to a second embodiment of the present invention. (B) is a sectional view showing a configuration of a semiconductor device according to a second embodiment of the present invention.

FIG. 6A is a diagram illustrating an energy level of a semiconductor device according to a second embodiment of the present invention. (B) is (a)
FIG. 3 is an enlarged view in the y-axis direction.

FIG. 7A is a configuration sectional view showing an epitaxial growth substrate for forming a conventional semiconductor device. (B)
FIG. 1 is a sectional view showing a configuration of a conventional semiconductor device.

FIG. 8 is a graph showing a drain current-drain voltage characteristic curve in a conventional semiconductor device.

FIG. 9 is a graph showing the dependence of ohmic contact resistance on the thickness of a spacer layer made of AlGaAs in a conventional semiconductor device.

FIG. 10A is a diagram showing an energy level of a conventional semiconductor device. (B) is an enlarged view in the y-axis direction of (a).

[Explanation of symbols]

 Reference Signs List 11 substrate 12 buffer layer 13 first spacer layer (p-type spacer layer) 14 first carrier supply layer 15 second spacer layer 16 quantum well layer 17 third spacer layer 18 second carrier supply layer 19 oxidation prevention Layer 21 First barrier layer 22 Second barrier layer 31 Gate electrode 32 Insulating film 33 Ohmic contact region 34 Source electrode 35 Drain electrode 42 Buffer layer 43 First spacer layer 51 Junction surface

Claims (6)

[Claims] A buffer layer formed on the substrate; a first barrier layer formed on the buffer layer and having a larger energy band gap than the buffer layer; A second barrier layer formed on the quantum well layer; an ohmic electrode selectively formed on the second barrier layer; and the ohmic electrode on the substrate. An ohmic contact region formed in a region below the electrode and reaching the buffer layer, wherein the first barrier layer includes a p-type spacer layer and an n-type carrier supply layer sequentially formed on the buffer layer. A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein said buffer layer is made of GaAs, said barrier layer is made of AlGaAs or InGaP, and said quantum well layer is made of InGaAs or GaAs. 3. The semiconductor device according to claim 2, wherein said spacer layer has a thickness of 10 nm or less. 4. A buffer layer formed on a substrate; a first barrier layer formed on the buffer layer and having an energy band gap larger than the buffer layer; A second barrier layer formed on the quantum well layer; an ohmic electrode selectively formed on the second barrier layer; and the ohmic electrode on the substrate. An ohmic contact region formed in a region below the electrode and reaching the buffer layer, wherein the buffer layer has p-type conductivity at least on a side in contact with the first barrier layer. Semiconductor device. 5. The semiconductor device according to claim 4, wherein said buffer layer is made of GaAs, said barrier layer is made of AlGaAs or InGaP, and said quantum well layer is made of InGaAs or GaAs. 6. The semiconductor device according to claim 5, wherein said spacer layer has a thickness of 10 nm or less.