JP2012043938A - Method of manufacturing field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a field effect transistor having a heterostructure constituting a channel layer from InAs to be stably operated at a high speed.SOLUTION: A surface of a cap layer 105 is processed with a processing solution made of hydrochloric acid. The processing solution is formed by, for example, diluting a water solution by 37% of mass of hydrogen chloride with five times (volume) its volume of water. Next, a substrate 101 is pulled up from the processing solution, and hydrochloric acid adhered to the surface of the cap layer 105 is immediately removed. In this removal of hydrochloric acid, without using water, for example, nitrogen gas is blown to the surface of the cap layer 105 to remove hydrochloric acid adhered thereto.

Description

  The present invention relates to a method for manufacturing a field effect transistor having a channel layer made of InAs.

  There is a need for field effect transistors (FETs) that can operate at higher speeds for faster computations and higher frequency oscillations. High-speed field effect transistors require high electron mobility and high electron saturation speed. For example, a field effect transistor having a basic structure of a GaAs / AlGaAs heterostructure in which an electron channel layer is made of GaAs and an InGaAs / InAlAs / InP heterostructure in which an electron channel layer is made of InGaAs, and an operation of 500 GHz or more is realized. ing.

  Under such circumstances, InAs is a material having higher electron saturation density and higher mobility than the above-described GaAs and InGaAs, and a heterostructure field effect transistor having a channel layer made of InAs is capable of operating at higher speed. Expected to be possible. As shown in FIG. 8, the field effect transistor includes a first barrier layer 802 made of AlGaSb formed on a substrate 801, a channel layer 803 made of InAs formed on the first barrier layer 802, And a second barrier layer 804 made of AlGaSb formed on the channel layer 803. The field effect transistor is formed on a cap layer 805 made of GaSb formed on the second barrier layer 804, a gate insulating layer 806 formed on the cap layer 805, and a gate insulating layer 806. And a source electrode 808 and a drain electrode 809 which are arranged with the gate electrode 807 interposed therebetween and are ohmically connected to the channel layer 803.

  In general, in a heterostructure field effect transistor using InAs for a channel layer, a quantum layer in which a channel layer 803 made of InAs is sandwiched between a first barrier layer 802 and a second barrier layer 804 made of AlSb or AlGaSb having a lattice constant close to InAs. A well structure is used. In the production of these structures, each layer made of a compound semiconductor is deposited by molecular beam epitaxy (MBE) or metal organic vapor phase epitaxy (MOVPE).

If the channel layer 803 made of InAs is thick to some extent (about 10 nm or more), the energy level of electrons in InAs becomes lower than the deep acceptor energy level in AlSb (or AlGaSb) constituting each barrier layer. Electrons of about × 10 ¹² cm ⁻² accumulate in the channel layer 803 (see Non-Patent Documents 1, 2, and 3).

  By the way, AlSb (or AlGaSb) constituting the barrier layer is easily oxidized because it contains Al and has deliquescence in the atmosphere. For this reason, in the production of a quantum well structure in which the channel layer is made of InAs, generally, a cap layer 805 made of GaSb having a lattice constant close to that of the second barrier layer 804 is formed and used as a lower layer. Oxidation and deliquescence of the Al-containing layer is prevented.

  In order to form a field effect transistor using the above-described quantum well structure, an insulating layer is required between the channel layer 803 and the gate electrode 807. For example, in a field effect transistor using silicon, an insulating layer made of silicon oxide is used as a gate insulating layer. In a field effect transistor having a GaAs / AlGaAs heterostructure, an AlGaAs layer used as a barrier layer is a gate insulating layer.

  On the other hand, in the case of a field effect transistor using InAs for the channel layer, the insulating properties of the second barrier layer 804 made of AlSb or AlGaSb and the cap layer 805 made of GaSb are low. For this reason, when the gate electrode 807 is formed directly on the cap layer 805 without using the gate insulating layer 806, a leakage current flows between the gate and the channel, and an electric field cannot be applied, so that it functions as a field effect transistor. do not do. Therefore, for example, a gate insulating layer 806 such as aluminum oxide is formed on the cap layer 805, and a gate electrode 807 is disposed thereon. Note that the gate insulating layer 806 can be formed by, for example, plasma induced chemical vapor deposition (PECVD) (see Non-Patent Document 4), atomic layer deposition (ALD) (see Non-Patent Document 5), or the like.

D.J.Chadi, "Electron accumulation at undoped AlSb-InAs quantum wells; Theory", Physical Review B, vol.47, no.20, pp.13478-13484, 1993. J. Shen et al., "Remote n-type modulation doping of InAs quantum wells by" deep acceptors "in AlSb", Journal of Applied Physics, vol.73, no.12, pp.8313-8318, 1993. M.Ideshita et al., "Electron accumulation in AIGaSb / lnAs / AIGaSb quantum well system", Applied Physics Letters, vol.60, no.20, pp.2549-2511, 1992. C. Nguyen et al., "Magneto-transport in InAs / AlSb quantum wells with large electron concentration modulation", Surface Science, vol.267, pp.549-552, 1992. Ian J. Gelfand et al., "Surface-gated quantum Hall effect in an InAs heterostructure", Applied Physics Letters, vol.88, 252105, 2006.

  However, when InAs is used for the channel layer, normal transistor control by the gate voltage is caused by an oxide layer formed on the surface of the cap layer 805 or a defect formed at the interface between the cap layer 805 and the gate insulating layer 806. There is a problem that it becomes impossible. The oxide layer and defects described above become traps of electrons, cancel the electric field due to the application of the gate voltage, suppress the change of the electron concentration with respect to the gate voltage change, and lower the efficiency of the electron concentration change with respect to the gate voltage change. .

  When an oxide layer or a defect is formed at the interface of the cap layer 805, as shown in FIG. 9A, an electron trap is formed at the interface between the cap layer 805 and the gate insulating layer 806 as indicated by a dotted white circle. A level is formed. When the gate voltage is 0, electrons are accommodated in some of the electron trap levels and some of the trap levels are empty. The entire interface is in an almost electrically neutral state as indicated by black dots in FIG.

  Next, when a positive gate voltage is applied, electrons are filled in the electron trap level as shown in FIG. In the process of applying the gate voltage in which electrons are filled in the electron trap level, the electric field due to the application of the positive gate voltage is canceled. For this reason, when a positive gate voltage is applied, as shown by a solid line in FIG. 10B, when the positive gate voltage is small, the channel layer 803 does not accumulate much electrons, and the applied voltage increases. When all the electron trap levels are filled with electrons, the electrons in the channel layer 803 increase along the straight line “Q = CV + α”. Note that Q is the amount of charge in the channel layer 803, and Q / e = n when the electron concentration n and the elementary charge amount e are used. α is a constant.

  Further, when a negative gate voltage is applied, as shown in FIG. 11A, electrons are emitted from the electron trap level, and a positive charge remains. In the process of applying a gate voltage in which electrons exit from the electron trap level, the electric field due to the negative gate voltage application is canceled. For this reason, when a negative gate voltage is applied, as shown by a solid line in FIG. 11B, in a state where the negative gate voltage is small, electrons in the channel layer 803 remain without being emitted, and the negative applied voltage is reduced. When the electron trap level becomes larger and all the electron trap levels become empty, the electrons in the channel layer 803 decrease along the straight line “Q = CV + β”. Note that β is a constant.

  As described above, when an oxide layer, a defect, or the like is formed on the surface of the cap layer 805, there is a problem that the operation of the transistor is hindered and a stable operation cannot be performed at high speed.

  The present invention has been made to solve the above-described problems, and it is an object of the present invention to be a heterostructure field effect transistor having a channel layer made of InAs and capable of stable operation at high speed. To do.

  The field effect transistor manufacturing method according to the present invention includes a step of forming a first barrier layer made of a compound semiconductor selected from AlGaSb and AlSb on a substrate, and a channel layer made of InAs on the first barrier layer. A step of forming a second barrier layer made of a compound semiconductor selected from AlGaSb and AlSb on the channel layer, and a step of forming a cap layer made of GaSb on the second barrier layer And a step of treating the surface of the cap layer with a treatment liquid comprising hydrochloric acid after forming the cap layer, a step of removing the treatment liquid without using water after treating the surface of the cap layer with the treatment liquid, and a treatment liquid A step of forming a gate insulating layer on the cap layer before the surface of the cap layer is oxidized after removing the gate electrode, and a gate electrode on the gate insulating layer. Comprising at least a step of forming, and the forming the source electrode and the drain electrode in ohmic connections are arranged to sandwich the gate electrode to the channel layer.

  In the method for manufacturing the field effect transistor, the treatment liquid may be removed by blowing an inert gas after treating the surface of the cap layer with the treatment liquid.

  As described above, according to the present invention, after the cap layer is formed, the surface of the cap layer is treated with the treatment liquid composed of hydrochloric acid, and then the treatment liquid is removed without using water. A field effect transistor having a heterostructure whose layer is made of InAs has an excellent effect of being able to operate stably at high speed.

FIG. 1A is a cross-sectional view showing a cross section in each step for explaining a method of manufacturing a field effect transistor according to an embodiment of the present invention. FIG. 1B is a cross-sectional view showing a cross section in each step for explaining the method of manufacturing the field effect transistor in the embodiment of the present invention. FIG. 1C is a cross-sectional view showing a cross section in each step for explaining a method of manufacturing the field effect transistor in the embodiment of the present invention. FIG. 1D is a cross-sectional view showing a cross section in each step for explaining the method of manufacturing the field effect transistor in the embodiment of the present invention. FIG. 1E is a cross-sectional view showing a cross section in each step for explaining the method of manufacturing the field effect transistor in the embodiment of the present invention. FIG. 2 is a characteristic diagram showing changes in the electron density n of the channel layer with respect to changes in the gate voltage V of the first comparison element. FIG. 3 is a characteristic diagram showing a change in the electron density n of the channel layer with respect to a change in the gate voltage V of the field effect transistor manufactured by the manufacturing method according to the embodiment. FIG. 4 is a characteristic diagram showing changes in the electron concentration n of the channel layer with respect to changes in the gate voltage V of the second comparison element. FIG. 5 is a photograph obtained by observing the surface of the cap layer in the first comparison element with an atomic force microscope. FIG. 6 is a photograph of the surface of the cap layer in the field effect transistor manufactured by the manufacturing method according to the embodiment, observed with an atomic force microscope. FIG. 7 is a photograph obtained by observing the surface of the cap layer in the second comparison element with an atomic force microscope. FIG. 8 is a cross-sectional view showing the configuration of a field effect transistor using InAs for the channel layer. FIG. 9 is an explanatory diagram for explaining the configuration and characteristics of a field effect transistor using InAs for the channel layer. FIG. 10 is an explanatory diagram for explaining the configuration and characteristics of a field effect transistor using InAs for the channel layer. FIG. 11 is an explanatory diagram for explaining the configuration and characteristics of a field effect transistor using InAs for the channel layer.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1A to 1E are cross-sectional views showing cross sections in each step for explaining a method of manufacturing a field effect transistor according to an embodiment of the present invention.

  First, as shown in FIG. 1A, a substrate 101 made of InAs or GaAs is prepared, and an AlSb layer having a thickness of 2.5 nm and a GaSb layer having a thickness of 2.5 nm are alternately formed thereon by molecular beam epitaxy. Superlattice layer 121 is formed by laminating 10 periods. Subsequently, a semiconductor layer 122 made of AlGaSb and having a layer thickness of 500 nm is formed, and an AlSb layer having a layer thickness of 2.5 nm and a GaSb layer having a layer thickness of 2.5 nm are alternately stacked thereon for 10 periods to form a superlattice layer 123. Form. These layers serve as buffer layers for each layer to be formed later.

Subsequently, as shown in FIG. 1B, on the superlattice layer 123, a first barrier layer 102 made of Al _0.7 Ga _0.3 Sb with a thickness of 50 nm and a channel layer 103 made of InAs with a thickness of 15 nm are formed by molecular beam epitaxy. Then, a second barrier layer 104 made of Al _0.7 Ga _0.3 Sb with a thickness of 30 nm and a cap layer 105 made of GaSb with a thickness of 5 nm are sequentially stacked. Each of the compound semiconductor layers described above is continuously formed by switching to the corresponding source beam in the same film forming apparatus.

  Next, the substrate 101 formed up to the cap layer 105 is unloaded from the film formation apparatus, and as illustrated in FIG. 1C, the source electrode 108 and the drain electrode 109 that are in ohmic contact with the channel layer 103 are formed. The source electrode 108 and the drain electrode 109 may be made of an AuGeNi alloy. These electrodes may be made of In. The source electrode 108 and the drain electrode 109 are electrically connected to the channel layer 103 by forming an alloy layer from the cap layer 105. For example, a resist is applied, patterning is performed by a known lithography technique, the resist on the electrode portion is peeled off, and a metal as an electrode material is deposited on the entire surface by sputtering or vapor deposition to form an electrode material layer and then lifted off. Thus, the source electrode 108 and the drain electrode 109 may be formed.

  After forming the source electrode 108 and the drain electrode 109 as described above, the surface of the cap layer 105 exposed at this stage is cleaned (degreased) with acetone and isopropanol. First, the surface of the cap layer 105 is immersed in acetone, and subsequently immersed in isopropanol before acetone adhering to the surface is dried. Thereafter, the substrate 101 is pulled up from the isopropanol solution and, for example, nitrogen gas is blown onto the surface of the cap layer 105 to dry it. In addition, if the surface of the cap layer 105 is clean, the degreasing process described above may not be performed.

  Next, the surface of the cap layer 105 is treated with a treatment liquid made of hydrochloric acid. The treatment liquid is, for example, one obtained by diluting a 37% by mass aqueous solution of hydrogen chloride with water 5 times (volume). By immersing the substrate 101 in this treatment solution for about 10 seconds, the oxide layer formed of gallium oxide, antimony oxide, or the like formed on the surface of the cap layer 105 is dissolved and removed. GaSb hardly dissolves in hydrochloric acid, but minute protrusions formed on the surface of the cap layer 105 are dissolved and shaved. As a result, the surface flatness of the cap layer 105 is increased by the treatment with the hydrochloric acid treatment solution.

  Next, the substrate 101 is pulled up from the processing solution, and hydrochloric acid adhering to the surface of the cap layer 105 is immediately removed. In this removal of hydrochloric acid, for example, the attached hydrochloric acid is removed by blowing nitrogen gas onto the surface of the cap layer 105 without using water. For example, nitrogen gas having a pressure of about 1 MPa may be blown. Further, the nitrogen gas may be sprayed until the liquid droplets disappear on the surface of the cap layer 105 by visual inspection.

Here, GaSb is hardly soluble in hydrochloric acid, but oxides such as Ga ₂ O ₃ and Sb ₂ O ₃ are dissolved in hydrochloric acid. Therefore, it can be used to remove the oxide layer on the surface of the cap layer 105. In contrast, sulfuric acid such as InAs and GaAs, including the substrate 101, is completely dissolved, and thus cannot be used for the treatment of the cap layer 105 surface. Furthermore, phosphoric acid cannot be used because it dissolves GaSb and AlGaSb. In addition, even alkali such as NaOH and NH ₃ can not be used because it dissolves GaSb and AlGaSb.

As described above, after the treatment with the treatment liquid made of hydrochloric acid and drying, before the oxide layer is formed again on the surface, as shown in FIG. 1D, the layer made of aluminum oxide (Al ₂ O ₃ ) A gate insulating layer 106 having a thickness of 20 nm is formed. Since GaSb is oxidized in the atmosphere in about 20 minutes to form an oxide layer, the gate insulating layer 106 is formed before the oxide layer is formed in this way. For example, an atomic layer growth method in which an aluminum raw material composed of trimethylaluminum or triethylaluminum and water vapor as an oxidant are supplied alternately and intermittently to form an aluminum oxide layer one atomic layer at a time. May be formed. The atomic layer growth method using trimethylaluminum or triethylaluminum also has the effect of removing the surface oxide film of GaSb and reducing the electron trap level. In this atomic layer growth, the pressure in the deposition chamber of the atomic layer growth apparatus may be about 10 hPa, and the growth temperature may be 190 ° C.

  Next, as illustrated in FIG. 1E, the gate electrode 107 is formed over the gate insulating layer 106 between the source electrode 108 and the drain electrode 109. For example, a resist pattern in which the formation position of the gate electrode 107 is opened is formed on the gate insulating layer 106. Next, a titanium film having a thickness of 5 nm is deposited, and an Au film having a thickness of 95 nm is formed on the titanium film. Thereafter, if the resist pattern is removed, the gate electrode 107 made of Ti / Au can be formed (lift-off method). In FIG. 1E, the gate insulating layer 106 is formed over the source electrode 108 and the drain electrode 109; however, when wiring is connected to the source electrode 108 and the drain electrode 109, the gate insulating layer 106 at the connection portion is changed. Remove it.

  According to the present embodiment described above, after the surface of the cap layer 105 is treated with the treatment liquid made of hydrochloric acid, the treatment liquid is removed without using water (without washing with water), and the gate insulating layer 106 is immediately removed. Therefore, the formation of an oxide layer, a defect, or the like serving as an electron trap at the interface between the cap layer 105 and the gate insulating layer 106 is suppressed. As a result, the operation of the transistor is not hindered by the presence of an oxide layer or a defect on the surface of the cap layer 105, and stable operation can be performed at high speed.

  Hereinafter, experimental results of the actually fabricated elements will be described. First, the measurement is performed on the first comparison element and the second comparison element manufactured by another manufacturing method in addition to the field effect transistor manufactured by the manufacturing method of the present embodiment described above. In this experiment, the change in the electron concentration in the channel layer with respect to the gate voltage sweep rate (1 V / 30 minutes) is measured.

  In the first comparison element, the surface of the cap layer 105 is degreased with acetone and isopropanol. In the first comparison element, the surface of the cap layer 105 is not treated with hydrochloric acid. In the first comparison element, the surface of the cap layer 105 is not washed with water.

  In the second comparison element, the surface of the cap layer 105 is degreased with acetone and isopropanol, and then treated with hydrochloric acid and washed with water. The water washing treatment is a treatment performed for removing hydrochloric acid after the hydrochloric acid treatment. In all of the field effect transistors according to the first comparison element, the second comparison element, and the manufacturing method according to the embodiment, in this experiment, the channel layer has a layer thickness of 12 nm and is between the channel layer and the first barrier layer. In addition, a GaSb layer having a layer thickness of 18 nm is provided.

  In the first comparison element, as shown in FIG. 2, in the region 201, the electron concentration does not change much with respect to the change in the gate voltage. The arrow indicates the sweep direction.

  In the field effect transistor in this embodiment, as shown in FIG. 3, the electron concentration changes with the change of the gate voltage, and there is no region where the electron concentration does not change. The arrow indicates the sweep direction.

  In the second comparison element, as shown in FIG. 4, in the region 401, the electron concentration does not change much with respect to the change of the gate voltage. Compared with the first comparison element, a region where the electron concentration does not change so much is a wider voltage range. The arrow indicates the sweep direction.

  As described above, according to the present embodiment, the electron concentration changes substantially in proportion to the change in the gate voltage without canceling out the electric field due to the application of the gate voltage.

  Next, in the first comparison element, the second comparison element, and the field effect transistor according to the present embodiment, the result of observation of the cap layer surface state immediately after the surface treatment for the cap layer with an atomic force microscope will be described. This observation was performed at room temperature (20 to 25 ° C.).

  In the process according to the first comparison element and the present embodiment, as shown in the photograph of FIG. 5 and the photograph of FIG. 6, no great difference is observed. On the other hand, in the second comparison element, as shown in the photograph of FIG. 7, a large number of minute black spots that look like a rough image are observed. This is considered to be a defect such as an oxide layer formed by the water washing treatment. When combined with the result of the electrical measurement described above, it can be understood that the water washing treatment leads to defect formation on the surface of the cap layer. Therefore, it can be seen that removal of defects by hydrochloric acid and removal of hydrochloric acid by blowing nitrogen are effective in preventing formation of defects on the surface of the cap layer. 5, FIG. 6 and FIG. 7 show an area of 2 μm × 2 μm.

  It should be noted that the present invention is not limited to the embodiment described above, and that many modifications can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention. It is obvious. For example, in the above description, the treatment liquid is removed by blowing nitrogen gas, but not limited to nitrogen gas, inert gas such as helium and argon may be used. Further, after the hydrochloric acid treatment, hydrochloric acid is removed by blowing nitrogen gas. However, the present invention is not limited to this, and the substrate may be rotated using a so-called spinner to remove hydrochloric acid by centrifugal force. In the above description, the barrier layer is made of AlGaSb. However, the barrier layer may be made of AlSb.

  In the present invention, the surface of the cap layer made of GaSb is treated with a treatment solution with hydrochloric acid, and then the treatment solution is removed without washing with water. Thereafter, a gate insulating layer is immediately formed on the cap layer. There are features. Therefore, the formation of the source electrode and the drain electrode may be performed, for example, after forming the gate insulating layer, and is not limited to the order of the manufacturing steps described using the above-described embodiment.

  DESCRIPTION OF SYMBOLS 101 ... Substrate, 102 ... First barrier layer, 103 ... Channel layer, 104 ... Second barrier layer, 105 ... Cap layer, 106 ... Gate insulating layer, 107 ... Gate electrode, 108 ... Source electrode, 109 ... Drain electrode, 121 , 123 ... superlattice layer, 122 ... semiconductor layer.

Claims (2)

Forming a first barrier layer made of a compound semiconductor selected from AlGaSb and AlSb on a substrate;
Forming a channel layer made of InAs on the first barrier layer;
Forming a second barrier layer made of a compound semiconductor selected from AlGaSb and AlSb on the channel layer;
Forming a cap layer made of GaSb on the second barrier layer;
Treating the surface of the cap layer with a treatment liquid comprising hydrochloric acid after forming the cap layer;
Removing the treatment liquid without using water after treating the surface of the cap layer with the treatment liquid;
Forming a gate insulating layer on the cap layer before the surface of the cap layer is oxidized after removing the treatment liquid;
Forming a gate electrode on the gate insulating layer;
And a step of forming a source electrode and a drain electrode which are disposed with the gate electrode interposed therebetween and are in ohmic contact with the channel layer. In the manufacturing method of the field effect transistor of Claim 1,
A method for producing a field effect transistor, comprising: treating the surface of the cap layer with the treatment liquid; and removing the treatment liquid by spraying an inert gas.