JPH05211340A - Enhancement-mode field-effect transistor - Google Patents

Enhancement-mode field-effect transistor

Info

Publication number
JPH05211340A
JPH05211340A JP32350191A JP32350191A JPH05211340A JP H05211340 A JPH05211340 A JP H05211340A JP 32350191 A JP32350191 A JP 32350191A JP 32350191 A JP32350191 A JP 32350191A JP H05211340 A JPH05211340 A JP H05211340A
Authority
JP
Japan
Prior art keywords
algasb
layer
inas
level
quantum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP32350191A
Other languages
Japanese (ja)
Other versions
JP2701632B2 (en
Inventor
Tomoshi Ideshita
知史 井手下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP32350191A priority Critical patent/JP2701632B2/en
Publication of JPH05211340A publication Critical patent/JPH05211340A/en
Application granted granted Critical
Publication of JP2701632B2 publication Critical patent/JP2701632B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To realize an ultrahigh-speed and low-power consumption enhancement- mode field-effect transistor in an AlGaSb/InAs/AlGaSb quantum well system. CONSTITUTION:In an electron storage mechanism in an AlGaSb/InAs/AlGaSb quantum well system, an electron supply source in an AlGaSb barrier layer 1 is donors in a direct manner, but the positional relation between a deep acceptor level in the layer 1 and a quantum level in an InAs quantum well layer 2 plays an important role. A structure in which the quantum level in the layer 2 is higher than the deep acceptor level 4 in the AlGaSb barrier layer 1 was fabricated and the normally OFF-state was confirmed. In this structure, the layer 1 on the side of the surface of the layer 1 is sufficiently thick and the supply of electrons from the surface level in the layer 1 is inhibited.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は3−5族化合物半導体を
用いた超高速・低消費電力・低雑音トランジスタに関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultra-high speed, low power consumption, low noise transistor using a 3-5 group compound semiconductor.

【0002】[0002]

【従来の技術】超高速コンピュータ・超高速通信システ
ムの構築に向けて、半導体デバイスの分野では材料の選
択・デバイス構造の改善等により、さらなる高速化・低
消費電力化・低雑音化が進められようとしている。
2. Description of the Related Art In the field of semiconductor devices, further speedup, lower power consumption, and lower noise are being promoted in the field of semiconductor devices by constructing materials and improving the device structure in order to build ultrahigh-speed computers and ultrahigh-speed communication systems. I am trying to do.

【0003】3−5族化合物半導体ヘテロ接合を用いた
デバイスにおける材料系からのアプローチは、チャネル
層として、GaAsからInGaAsへ、さらにInA
sへと、電子の移動度・飽和速度の大きい材料を用いる
方向に向かっている。ヘテロ接合系では格子整合がとれ
ていることが重要であり、GaAs系では(AlGaA
s/GaAs/GaAs基板)構造、InGaAs系で
は(AlInAs/InGaAs/InP基板)構造な
どが用いられている。一方、InAsの場合は格子整合
を満たす障壁層は存在しないが、AlGaSb系との格
子不整合は0.7〜1.3%と比較的小さく、数百オン
グストローム(以下Aと記す)以内であれば歪による欠
陥のない成長が可能であり、(AlGaSb/InAs
/AlGaSb/GaSb基板)等の量子井戸構造が一
般に用いられている。電界効果トランジスタ(FET)
の中でも、より高速性が期待されるのがエンハンスメン
ト型であるが、AlGaSb/InAs/AlGaSb
系ではまだ実現されていない。
The approach from the material system in the device using the group III-V compound semiconductor heterojunction is as follows.
Toward s, the direction of using a material having a high electron mobility / saturation speed is being pursued. It is important for the heterojunction system to have lattice matching, and for the GaAs system, (AlGaA
s / GaAs / GaAs substrate) structure, and InGaAs-based (AlInAs / InGaAs / InP substrate) structure. On the other hand, in the case of InAs, there is no barrier layer that satisfies the lattice matching, but the lattice mismatch with the AlGaSb system is comparatively small at 0.7 to 1.3%, and is within a few hundred angstroms (hereinafter referred to as A). For example, strain-free growth due to strain is possible, and (AlGaSb / InAs
/ AlGaSb / GaSb substrate) and the like are generally used. Field effect transistor (FET)
Among them, enhancement type is expected to have higher speed, but AlGaSb / InAs / AlGaSb
It has not been realized yet in the system.

【0004】[0004]

【発明が解決すべき課題】FETをの高速性・低消費電
力性を向上させる上で、しきい値電圧は小さい方が、ま
た、障壁層厚は薄い方が望ましい。AlGaAs/Ga
As系の場合には、AlGaAs障壁層厚が薄くなるほ
どしきい値電圧が減少する傾向にあった。しかし、Al
GaSb/InAs/AlGaSb系の場合は、逆に増
加する。これは、InAsの伝導帯よりもAlGaSb
の表面ピンニングレベルが300meV程度高いため
に、表面準位からInAsチャネルへ電子が供給される
からである。したがって、AlGaAs/GaAs系の
場合とは異なり、障壁層を薄くすることとしきい値電圧
の低減とは相反することになる。
In order to improve the high speed and low power consumption of the FET, it is desirable that the threshold voltage is small and the barrier layer is thin. AlGaAs / Ga
In the case of As series, the threshold voltage tended to decrease as the AlGaAs barrier layer thickness decreased. However, Al
In the case of GaSb / InAs / AlGaSb system, it increases conversely. This is AlGaSb rather than the conduction band of InAs.
Since the surface pinning level of is about 300 meV, electrons are supplied from the surface level to the InAs channel. Therefore, unlike the case of the AlGaAs / GaAs system, thinning the barrier layer and reducing the threshold voltage conflict with each other.

【0005】一方、表面のAlGaSb層を十分に厚く
して表面の効果を抑制した場合でさえ、InAs中への
電子蓄積は見られる。この原因は明らかにされていなか
った。蓄積電子濃度低減のための最も安易な方法として
は、AlGaSb障壁層中へのp型ドーピングが考えら
れるが、実際にはAlGaSb/InAs界面に正孔が
蓄積してしまい、デバイスとして機能しなくなり、手の
打ちようがなかった。また、InAsゲート構造を持つ
FETは考案されてはいるが、この系でまだ確立されて
いないドライプロセスが必要となる等、解決すべき問題
が残されている。
On the other hand, even when the surface AlGaSb layer is made sufficiently thick to suppress the surface effect, electron accumulation in InAs is observed. The cause of this has not been clarified. As the easiest method for reducing the concentration of accumulated electrons, p-type doping in the AlGaSb barrier layer is conceivable, but in reality, holes accumulate at the AlGaSb / InAs interface and the device does not function as a device. I couldn't beat it. Further, although an FET having an InAs gate structure has been devised, there still remains a problem to be solved, such as the need for a dry process that has not yet been established in this system.

【0006】[0006]

【課題を解決するための手段】(1)我々は、AlGa
Sb中にintrinsicな欠陥によるものと考えら
れるドナー及び深いアクセプタが存在すること、このう
ち、深いアクセプタがドナーの電子をトラップして、I
nAs層への電子の供給源になることを見いだした。
[Means for Solving the Problems] (1) We use AlGa
The presence of a donor and a deep acceptor, which are considered to be due to an intrinsic defect in Sb, of which the deep acceptor traps the electron of the donor,
It has been found that it serves as a source of electrons to the nAs layer.

【0007】アクセプタ準位からの電子蓄積効果を除去
するために、AlGaSb/InAs/AlGaSb量
子井戸型のエンハンスメント型FETのInAs井戸層
厚を薄くすることによってその第一量子準位をAlGa
Sb中の深いアクセプタ準位よりも高くしたことを特徴
とする。
In order to remove the electron storage effect from the acceptor level, the thickness of the InAs well layer of the AlGaSb / InAs / AlGaSb quantum well enhancement type FET is reduced to reduce the first quantum level to AlGaSb / InAs / AlGaSb.
It is characterized in that it is higher than the deep acceptor level in Sb.

【0008】(2)FET特性を向上させる上で、障壁
層厚を薄くする過程は避けては通れない。障壁層厚が薄
くなると、表面準位からの電子蓄積が顕著になる。これ
を避けるために、AlGaSb/InAs/AlGaS
b量子井戸型のエンハンスメント型FETの、表面側A
lGaSb層の最表面の数十Aを高濃度のp型層とする
構造であることを特徴とする。
(2) In improving the FET characteristics, the process of making the barrier layer thin is inevitable. As the barrier layer becomes thinner, the electron accumulation from the surface level becomes remarkable. To avoid this, AlGaSb / InAs / AlGaS
b Quantum well type enhancement type FET, surface side A
It is characterized in that the outermost surface of the lGaSb layer has a high concentration of a few tens of amperes of a p-type layer.

【0009】[0009]

【作用】(1)に関する作用について説明する。[Operation] The operation relating to (1) will be described.

【0010】このInAs/AlGaSb系の場合、I
nAs井戸層中量子準位とAlGaSb層中電子トラッ
プ準位とのエネルギー差は僅かで、せいぜい150me
V程度である。これは、電子トラップ準位がアクセプタ
準位であるために、一般のドナー準位の場合と比較して
低いエネルギー位置にあるからである。150meVと
いう値は、InAsでは100A程度の比較的厚い井戸
の量子準位に対応する。GaAs系では、量子準位が1
50meVも上昇すると、電気特性に致命的な影響を与
える。しかし、InAsの場合には、谷間エネルギー差
が780meVと大きいこと、InAs/AlGaSb
間の伝導帯不連続値が大きいことのために、電気特性に
悪影響を及ぼすことなく、量子準位を上昇させることが
できる。
In the case of this InAs / AlGaSb system, I
The energy difference between the quantum level in the nAs well layer and the electron trap level in the AlGaSb layer is small, and is at most 150 me.
It is about V. This is because the electron trap level is the acceptor level and is at a lower energy position than the general donor level. The value of 150 meV corresponds to the quantum level of a relatively thick well of about 100 A for InAs. In the GaAs system, the quantum level is 1
A rise of as much as 50 meV will have a fatal effect on the electrical characteristics. However, in the case of InAs, the valley energy difference is as large as 780 meV, and InAs / AlGaSb
Due to the large conduction band discontinuity between them, the quantum level can be raised without adversely affecting the electrical characteristics.

【0011】したがって、表面準位の効果のないような
系(すなわち、表面AlGaSb層が厚い系)では、量
子準位を僅かに上昇させるだけで、良好な電気特性を保
ったまま、電子蓄積を防止できる。
Therefore, in a system in which the effect of the surface level is not exerted (that is, a system in which the surface AlGaSb layer is thick), electron accumulation can be performed while maintaining good electric characteristics by only slightly increasing the quantum level. It can be prevented.

【0012】(2)に関する作用について説明する。The operation relating to (2) will be described.

【0013】表面高濃度ドーピングにより、ショットキ
ー接触による静電ポテンシャルの大部分は表面近傍で解
消される。ドープ層は、完全に空之化しているのでキャ
リアの伝導はなく、パラレル伝導は抑制できる。また、
この構造では、ゲート電圧を負側に振ったときには、電
場のほとんどが表面ドープ層で消費されるものの、正側
(電子が蓄積される方向)に振った場合には、ダイレク
トにチャネルの電子濃度を制御することができるので、
エンハンスメント型のFETとして使用するのには何等
問題がない。
Due to the high surface concentration doping, most of the electrostatic potential due to the Schottky contact is eliminated near the surface. Since the doped layer is completely empty, there is no carrier conduction and parallel conduction can be suppressed. Also,
In this structure, when the gate voltage is swung to the negative side, most of the electric field is consumed by the surface-doped layer, but when swung to the positive side (the direction in which electrons are accumulated), the electron concentration in the channel is directly increased. Because you can control
There is no problem in using it as an enhancement type FET.

【0014】[0014]

【実施例】図1を用いて第1の実施例を説明する。EXAMPLE A first example will be described with reference to FIG.

【0015】Al0 . 5 Ga0 . 5 Sb/InAs/A
0 . 5 Ga0 . 5 Sb量子井戸構造の場合、Al
0 . 5 Ga0 . 5 Sbの中の深いアクセプタ準位は価電
子帯頂上の140meV程度上にある。これは、InA
sの伝導帯の底よりも約100meV程度エネルギー的
に高いことを意味する。従って、障壁層から井戸層への
電子供給を抑制するためには、InAs井戸の量子準位
を、100meV以上にすればよいのだが、この系にお
けるバンドパラメータがかなりの不確定性を含んでいる
ことを考慮して、実際には量子準位が150meVとな
るようにInAs井戸層2の厚さを100オングストロ
ーム(A)に設計した。この構造図とそのバンド図を図
1に示す。表面の効果が無視できるよう、表面AlGa
Sb障壁層1の厚さは、1000Aと厚くした。この
時、系は77kにおいて高抵抗を示し、電子濃度は測定
できなかった。つまり、ノーマリーオフ状態のInAs
チャネルが実現された。これは、前述のように、井戸中
の量子準位の方が電子をトラップしている深いアクセプ
タ準位4により高い位置にあるからである。
[0015] Al 0. 5 Ga 0. 5 Sb / InAs / A
For l 0. 5 Ga 0. 5 Sb quantum well structure, Al
0. 5 Ga 0. 5 deep acceptor level in the Sb is on about 140meV top of the valence band. This is InA
It means that the energy is higher than the bottom of the conduction band of s by about 100 meV. Therefore, in order to suppress the electron supply from the barrier layer to the well layer, the quantum level of the InAs well may be set to 100 meV or more, but the band parameter in this system includes a considerable uncertainty. In consideration of this, the thickness of the InAs well layer 2 is designed to be 100 angstrom (A) so that the quantum level is actually 150 meV. This structural diagram and its band diagram are shown in FIG. Surface AlGa so that the effect of the surface can be ignored
The thickness of the Sb barrier layer 1 was 1000A. At this time, the system showed high resistance at 77 k, and the electron concentration could not be measured. In other words, normally-off InAs
The channel was realized. This is because, as described above, the quantum level in the well is higher than the deep acceptor level 4 trapping electrons.

【0016】次に第2の実施例を説明する。図2に、障
壁層表面に高濃度のp型ドーピングをした場合の試料構
造図とそのハンド図を示す。表面Al0 . 5 Ga0 . 5
Sb障壁層11の厚さ250Aとし、そのうち最表面の
50AにBe等のp型ドーパントを1×19cm- 3
ープする。InAs井戸層12の厚さは、100Aにし
た。この場合、約400meVショットキーバリアの大
部分が表面ドープ層13で解消され、InAs中の電子
濃度は高濃度ドープ層がない場合より一桁以上低減さ
れ、ノーマリーオフ状態が実現される。ドープ層厚が5
0Aと薄いことから250Aよりさらに薄い障壁層を持
つ構造にも対応できる。従って、本発明により、良好な
特性を持つエンハンスメント型FETが実現できる。
Next, a second embodiment will be described. FIG. 2 shows a sample structure diagram and a hand diagram thereof when the barrier layer surface is heavily p-doped. Surface Al 0. 5 Ga 0. 5
The thickness of the Sb barrier layer 11 is set to 250 A, and the outermost surface 50 A is doped with 1 × 19 cm −3 of p-type dopant such as Be. The thickness of the InAs well layer 12 was 100A. In this case, most of the approximately 400 meV Schottky barrier is eliminated by the surface-doped layer 13, the electron concentration in InAs is reduced by one digit or more as compared with the case without the high-doped layer, and a normally-off state is realized. Dope layer thickness is 5
Since it is as thin as 0 A, it can be applied to a structure having a barrier layer thinner than 250 A. Therefore, according to the present invention, an enhancement type FET having good characteristics can be realized.

【0017】[0017]

【発明の効果】本発明を用いるならば、従来より難しい
とされていたAlGaSb/InAs/AlGaSb量
子井戸構造を用いて、高速のエンハンスメント型FET
を実現できる。
According to the present invention, a high-speed enhancement type FET using the AlGaSb / InAs / AlGaSb quantum well structure which has been considered to be more difficult than the conventional one.
Can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を説明するための図で、
(A)は構造を示す図、(B)はバンド図である。
FIG. 1 is a diagram for explaining a first embodiment of the present invention,
(A) is a diagram showing a structure and (B) is a band diagram.

【図2】本発明の第2の実施例を説明するための図で、
(A)は構造を示す図、(B)はバンド図である。
FIG. 2 is a diagram for explaining a second embodiment of the present invention,
(A) is a diagram showing a structure and (B) is a band diagram.

【符号の説明】[Explanation of symbols]

1 アンドープAlGaSb(障壁層) 2 InAs(量子井戸層) 3 表面ピンニング準位 4 アクセプタ準位 11 アンドープAlGaSb(障壁層) 12 InAs(量子井戸層) 13 高濃度p型ドーピング層 14 表面ピンニング準位 15 アクセプタ準位 1 Undoped AlGaSb (barrier layer) 2 InAs (quantum well layer) 3 Surface pinning level 4 Acceptor level 11 Undoped AlGaSb (barrier layer) 12 InAs (quantum well layer) 13 High-concentration p-type doping layer 14 Surface pinning level 15 Acceptor level

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 AlGaSb/InAs/AlGaSb
量子井戸構造を有するエンハンスメント型の電界効果ト
ランジスタであって、InAs井戸層の量子準位がAl
GaSb層中のアクセプタ準位よりも高いことを特徴と
するエンハンスメント型電界効果トランジスタ。
1. AlGaSb / InAs / AlGaSb
An enhancement-type field effect transistor having a quantum well structure, wherein the quantum level of an InAs well layer is Al.
An enhancement type field effect transistor characterized by being higher than an acceptor level in a GaSb layer.
【請求項2】 AlGaSb/InAs/AlGaSb
量子井戸構造を有するエンハンスメント型の電界効果ト
ランジスタであって、AlGaSb層表面の数十オング
ストロームの領域にp型高濃度ドーピングされているこ
とを特徴とするエンハンスメント型電界効果トランジス
タ。
2. AlGaSb / InAs / AlGaSb
An enhancement-type field-effect transistor having a quantum well structure, characterized in that a region of several tens of angstroms on the surface of an AlGaSb layer is heavily doped with p-type.
JP32350191A 1991-12-09 1991-12-09 Enhancement type field effect transistor Expired - Fee Related JP2701632B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32350191A JP2701632B2 (en) 1991-12-09 1991-12-09 Enhancement type field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32350191A JP2701632B2 (en) 1991-12-09 1991-12-09 Enhancement type field effect transistor

Publications (2)

Publication Number Publication Date
JPH05211340A true JPH05211340A (en) 1993-08-20
JP2701632B2 JP2701632B2 (en) 1998-01-21

Family

ID=18155399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32350191A Expired - Fee Related JP2701632B2 (en) 1991-12-09 1991-12-09 Enhancement type field effect transistor

Country Status (1)

Country Link
JP (1) JP2701632B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07235188A (en) * 1993-12-28 1995-09-05 Nec Corp Optical memory using impurity level in semiconductor fine particles
JP2012043938A (en) * 2010-08-18 2012-03-01 Nippon Telegr & Teleph Corp <Ntt> Method of manufacturing field effect transistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07235188A (en) * 1993-12-28 1995-09-05 Nec Corp Optical memory using impurity level in semiconductor fine particles
JP2012043938A (en) * 2010-08-18 2012-03-01 Nippon Telegr & Teleph Corp <Ntt> Method of manufacturing field effect transistor

Also Published As

Publication number Publication date
JP2701632B2 (en) 1998-01-21

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