WO2008007335A2 - High electron mobility transistor. - Google Patents

High electron mobility transistor. Download PDF

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Publication number
WO2008007335A2
WO2008007335A2 PCT/IB2007/052744 IB2007052744W WO2008007335A2 WO 2008007335 A2 WO2008007335 A2 WO 2008007335A2 IB 2007052744 W IB2007052744 W IB 2007052744W WO 2008007335 A2 WO2008007335 A2 WO 2008007335A2
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layer
alinas
electron mobility
alassb
high electron
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PCT/IB2007/052744
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French (fr)
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WO2008007335A3 (en
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Hassan Maher
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Ommic
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/122—Single quantum well structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Definitions

  • the invention relates to a high electron mobility transistor (HEMT) and method of making it.
  • HEMT high electron mobility transistor
  • HEMTs The performance of HEMTs depends on a number of factors, but one of the most important is the choice of materials used for the semiconductor layers forming one or more heterojunctions to define the channel of the HEMT. Perhaps the best known combination of materials is GaAs / AlGaAs, but other combinations are also described in the literature including for example InGaP/ GaAs, InAlAs/InGaAs, AlGaN/ GaN and others.
  • JP62-208455 describes a semiconductor device with the heterojunction forming the channel at the heart of the device being an AlAsSb layer in contact with an InGaAs layer.
  • a superlattice buffer of InGaAs /AlAsSb is grown on a substrate, ending with an InGaAs channel layer, followed by an n AlAsSb electron supply layer.
  • a gate is formed over part of the electron supply layer.
  • the inventors of the present case are unaware of any commercial devices using this materials system, or even any other subsequent publications.
  • the problem is that it has taken decades of technical development to improve AlGaAs / GaAs deposition to the point where very high electron mobilities can be obtained.
  • the effect of introducing an AlAsSb layer on InGaAs is a drastic degradation of the electron mobility in the channel and resulting very poor electronic properties.
  • conventional choices of materials are used which can deliver high electron mobilities.
  • One such choice is the InAlAs/ InGaAs / InAlAs HEMT which can deliver very good dynamic performance compared with other types of HEMT.
  • the gate length of transistors decreases and an InAlAs/ InGaAs / InAlAs HEMT with a short gate length can exhibit certain undesireable properties.
  • the HEMT can have a low breakdown voltage and a high gate leakage current.
  • the HEMT can suffer from the so-called short channel effect which gives rise to a number of negative properties such as high output conductance, high pinch-off voltage, real space transfer effect, and dynamic performance limitation.
  • the gate voltage swing can be small, especially for enhancement mode HEMTs. This degradation in properties is directly related to the physical properties of the layer structure and cannot therefore easily be solved simply by improved deposition technologies. The problems become worse at high power.
  • a high electron mobility transistor comprising: an InGaAs channel layer; an AlInAs upper intermediate layer on the InGaAs channel layer (10); a barrier layer on the AlInAs upper intermediate layer, the barrier layer being of AlAsSb or Ga w Al 1 -w AsSb with w less than or equal to 0.2; and a gate layer above the AlInAs intermediate layer for controlling conduction in a channel in the InGaAs channel layer.
  • the interface quality achievable with InGaAs/ AlAsSb is not nearly as good as for
  • the structure according to the invention accordingly includes a thin upper intermediate layer of AlInAs above the channel layer to improve the conduction in the channel, i.e. the electron mobility, since much better interfaces are possible with this material.
  • the layer of AlAsSb or GaAlAsSb greatly improves the confinement of electrons in the channel, since the conduction band offset between InGaAs and AlAsSb is three times higher than between InGaAs and AlInAs.
  • the increased carrier confinement in the channel minimises the short channel effect.
  • the structure also reduces the gate current and increases the breakdown voltage by reducing the current through the barrier layer.
  • Enhanced radio frequency properties are also achieved since the HEMT has a lower output conductance (Gd)and high transconductance (Gm).
  • the distance between the channel and the gate electrode is preferably less than approximately 13nm.
  • the AlInAs intermediate layer has a thickness less than 5nm, further preferably of 3nm to 5nm. This thin intermediate layer improves the interface quality without overly reducing the effect of the greater electron confinement afforded by the large band gap and particularly large conduction band offset provided by the AlAsSb layers.
  • the HEMT preferably includes an AlInAs protection layer on the AlAsSb barrier layer, the gate layer being provided on the AlInAs upper gate contact layer. Further, the HEMT preferably has an AlAsSb buffer layer; and an AlInAs lower intermediate layer on the AlAsSb buffer layer, wherein the InGaAs channel layer is formed on the AlInAs lower intermediate layer.
  • the HEMT may be formed on a substrate with an AlInAs buffer layer on the substrate, the AlAsSb buffer layer being on the AlInAs buffer layer.
  • the AlInAs lower intermediate layer may also have a thickness of 3nm to 5nm.
  • the or each AlAsSb or GaAlAsSb layer preferably has the formula AlAs x Sbi_ x where x is preferably in the range 0.45 to 0.65, preferably 0.56.
  • x is preferably in the range 0.45 to 0.65, preferably 0.56.
  • the use of the same material for each AlAsSb layer eases manufacture, but different values of x can be used for different layers if required.
  • the or each AlInAs layer preferably has the formula Al y Ini_ y As where y is in the range 0.4 to 0.6, preferably 0.48. Again, the use of the same material for different layers eases manufacture but different values of y can be used for different layers if required.
  • the InGaAs channel layer preferably has a formula In z Gai_ z As where z is in the range 0.4 to 0.80, preferably 0.53.
  • the invention also relates to a method of manufacture of a high electron mobility transistor, comprising: growing an AlInAs buffer layer; growing a buffer layer on the AlInAs lower buffer layer the buffer layer being of AlAsSb or Ga w Ali_ w AsSb with w less than or equal to 0.2; growing an AlInAs lower intermediate layer on the AlAsSb buffer layer; growing an InGaAs channel layer on the AlInAs lower intermediate layer; growing an AlInAs upper intermediate layer on the InGaAs channel layer; growing a barrier layer on the AlInAs intermediate layer the barrier layer being of AlAsSb or Ga w Ali_ w AsSb with w less than or equal to 0.2; growing an AlInAs protection layer on the AlAsSb barrier layer; growing an InGaAs cap layer on the AlInAs gate intermediate layer; forming source and drain contacts to contact the InGaAs channel layer; and depositing a gate layer on the AlInAs intermediate layer in the recess region
  • the source and drain contacts may be formed either before or after the gate. .
  • Figure 1 shows a side view of a HEMT structure according to the invention
  • Figure 2 shows a band diagram of the HEMT structure of claim 1.
  • the figures are schematic and not to scale.
  • the HEMT is formed on a semiconductor substrate 2. Any suitable material may be used, such as InP. In some cases, for example when using a Si or GaAs substrate, a metamorphic buffer may be used.
  • a number of layers are epitaxially grown on substrate 2.
  • the layers may be grown by any suitable method, including for example MOCVD, MBE, and other known semiconductor growth processes.
  • the first layer grown is a relatively thick buffer layer 4 of AlInAs.
  • the exact composition may be varied as desired.
  • the InGaAs channel layer 10 is grown.
  • the InGaAs channel layer has a formula In z Gai_ z As where z is in the specific embodiment 0.53. Again, the exact composition can be varied.
  • an AlInAs upper intermediate layer 12 of the same composition as the lower intermediate layer 8. Again, this is not essential.
  • the layer 12 contains a doping plane supply layer, which creates a high-density 2D electron gas in the channel.
  • An AlAsSb barrier layer 14 is formed on the AlInAs upper intermediate layer, in the embodiment of the same composition as lower layer 6
  • barrier layer 14 is an upper protection layer 16, of AlInAs, again in the embodiment of the same material as the other AlInAs layers.
  • This upper protection layer 16 deals with the difficulty that AlAsSb is highly oxidisable and oxidises very rapidly. In many semiconductors, for example AlInAs, only a surface layer of a thickness less than 3nm oxidises. In contrast, the whole thickness of an AlAsSb layer can oxidise, ruining the device properties. The upper protection layer 16 protects the AlAsSb from this oxidation.
  • a cap layer 17 is formed on the upper barrier layer 16.
  • a recess 19 is then formed, removing the cap layer 17 from a region to form the gate but leaving the cap layer 17 present in the region where the source and drain contacts 20,22 are to be formed.
  • the cap layer is a low band-gap layer, for example InGaAs, which protects the upper barrier layer 16 from oxidation in the access region where the source and drain contacts are formed.
  • a metal gate 18 is formed on the upper barrier layer 16 in the recess 19.
  • Source 20 and drain 22 contacts are formed, on the cap layer 17, extending to the channel layer 10. These contact the two dimensional electron gas 24 (2DEG) formed in the channel layer 10 at the heterojunction interface between the channel layer 10 and upper intermediate layer 12.
  • 2DEG two dimensional electron gas 24
  • the electrons in the 2DEG are supplied by the doping plane localised in the AlInAs upper intermediate layer 12.
  • diffusions 20,22 are used but any suitable contacts may be used.
  • a voltage applied to the gate controls conduction between the source and drain contacts 20,22 through the 2DEG 24 channel.
  • 2DEG is not intended to limit the invention to the case where only a single quantum state is occupied and is intended instead to relate to an substantially two dimensional channel confined by the heterostructure.
  • the transistor formed may be an enhancement type transistor or a depletion type transistor.
  • the transistor needs to be turned on by applying a positive voltage to the gate 18 to create the 2DEG channel.
  • a 2DEG channel 24 is present in the absence of a voltage, and a voltage is applied to the gate 18 to turn the device off.
  • the doping levels and the barrier layer thickness may be varied as required to achieve the desired properties.
  • the upper layer 12 may be doped as required to ensure sufficient electrons density in the channel.
  • the doping may be doping of the entire upper intermediate layer or only part of it.
  • a delta doping layer may be provided at some point in this region, either above, below, or within the upper layer 12
  • Doping may also be provided in other layers, particularly but not exclusively in lower layer 6, for example.
  • the band diagram of Figure 2 illustrates the band diagram of the device of Figure 1.
  • the conduction band 30, valence band 32 and Fermi energy level 34 are all shown.
  • the layers are indicated with the same reference numbers as in Figure 1.
  • the band gap of Alo.4sIno.52As is 1.45eV and of AlAso.56Sbo.44 is 2.45 eV.
  • the wider band gap of AlAso.56Sbo.44 is reflected particularly in the conduction band offset of AlAso.56Sbo.44 with Ino.53Gao.47As of 1.74eV. This may be compared with the conduction band offset of Alo.4sIno.52As with Ino.53Gao.47As of 0.52eV.
  • This enhanced conduction band offset greatly improves the confinement of the 2DEG 24 and hence gives improved dynamic and static properties.
  • the improved confinement caused by the conduction band offset of the channel 10 with the barrier 14 minimises the short channel effect.
  • the large conduction band offset between the gate 18 and the channel layer 10 of upper AlAsSb layer 14 has a further beneficial effect of reducing the gate current, increasing the breakdown voltage, and the positive gate voltage swing.
  • the good heterointerfaces between the InGaAs channel layer 10 and the AlInAs upper and lower intermediate layers 8,12 ensures a suitably high interface quality and hence electron mobility and so good performance.
  • a low output conductance and high transconductance may be achieved.
  • the buffer layer 6 may be replaced by other suitable buffers, including for example a superlattice buffer.
  • the superlattice buffer may also be of AlAsSb and AlInAs, for example, or other materials may also be used.
  • the material of the buffer layer 6 and barrier layer 14 is
  • Ga w Ali_ w AsSb instead of AlAsSb.
  • w will be less than 0.2.
  • part of the Al in the AlAsSb of the first embodiment is replaced by Ga.
  • the buffer layer 6 and barrier layer 14 will be more stable, since Ga w Ali_ w AsSb is less oxidisable.
  • the level is still very high for w ⁇ 0.2 compared to the conduction band offset between InGaAs and InAlAs.
  • the exact value of w may be selected based on a tradeoff between the improved material properties of higher values of w and beneficial band gap of low values of w.
  • the other semiconductor layers may also include small amounts of other elements.
  • the layers described as InGaAs or AlInAs layers may include small but non-trivial amounts of other elements, for example phosphide, although preferably less than 20% of the group III or group V elements are replaced by other elements in this way.

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Abstract

A HEMT is formed of a material system including an InGaAs channel layer 10, an AlInAs upper intermediate layer 12 on the InGaAs channel layer and an AlAsSb barrier layer on the AlInAs upper intermediate layer. A gate 18 is used to control conduction in the channel between source and drain. The high conduction band offset of the AlAsSb ensures good carrier confinement and enhanced properties, while the AlInAs intermediate layers form a good interface with the channel layer. The short channel effect can be reduced and both good static and dynamic properties obtained.

Description

HIGH ELECTRON MOBILITY TRANSISTOR
Field of the invention The invention relates to a high electron mobility transistor (HEMT) and method of making it.
Background of the invention
The performance of HEMTs depends on a number of factors, but one of the most important is the choice of materials used for the semiconductor layers forming one or more heterojunctions to define the channel of the HEMT. Perhaps the best known combination of materials is GaAs / AlGaAs, but other combinations are also described in the literature including for example InGaP/ GaAs, InAlAs/InGaAs, AlGaN/ GaN and others.
More esoteric combinations exist. For example, JP62-208455 describes a semiconductor device with the heterojunction forming the channel at the heart of the device being an AlAsSb layer in contact with an InGaAs layer. A superlattice buffer of InGaAs /AlAsSb is grown on a substrate, ending with an InGaAs channel layer, followed by an n AlAsSb electron supply layer. A gate is formed over part of the electron supply layer.
The inventors of the present case are unaware of any commercial devices using this materials system, or even any other subsequent publications. The problem is that it has taken decades of technical development to improve AlGaAs / GaAs deposition to the point where very high electron mobilities can be obtained. The effect of introducing an AlAsSb layer on InGaAs is a drastic degradation of the electron mobility in the channel and resulting very poor electronic properties. In practice therefore conventional choices of materials are used which can deliver high electron mobilities. One such choice is the InAlAs/ InGaAs / InAlAs HEMT which can deliver very good dynamic performance compared with other types of HEMT.
However, as device sizes shrink the gate length of transistors decreases and an InAlAs/ InGaAs / InAlAs HEMT with a short gate length can exhibit certain undesireable properties. Firstly, the HEMT can have a low breakdown voltage and a high gate leakage current. Secondly, the HEMT can suffer from the so-called short channel effect which gives rise to a number of negative properties such as high output conductance, high pinch-off voltage, real space transfer effect, and dynamic performance limitation. Thirdly, the gate voltage swing can be small, especially for enhancement mode HEMTs. This degradation in properties is directly related to the physical properties of the layer structure and cannot therefore easily be solved simply by improved deposition technologies. The problems become worse at high power.
There thus remains a need for HEMTs which address these issues.
Summary of the invention
According to the invention there is provided a high electron mobility transistor, comprising: an InGaAs channel layer; an AlInAs upper intermediate layer on the InGaAs channel layer (10); a barrier layer on the AlInAs upper intermediate layer, the barrier layer being of AlAsSb or Gaw Al1 -w AsSb with w less than or equal to 0.2; and a gate layer above the AlInAs intermediate layer for controlling conduction in a channel in the InGaAs channel layer.. The interface quality achievable with InGaAs/ AlAsSb is not nearly as good as for
InGaAs/ AlInAs. The structure according to the invention accordingly includes a thin upper intermediate layer of AlInAs above the channel layer to improve the conduction in the channel, i.e. the electron mobility, since much better interfaces are possible with this material. The layer of AlAsSb or GaAlAsSb greatly improves the confinement of electrons in the channel, since the conduction band offset between InGaAs and AlAsSb is three times higher than between InGaAs and AlInAs.
The increased carrier confinement in the channel minimises the short channel effect. The structure also reduces the gate current and increases the breakdown voltage by reducing the current through the barrier layer. Enhanced radio frequency properties are also achieved since the HEMT has a lower output conductance (Gd)and high transconductance (Gm).
For high performance devices the distance between the channel and the gate electrode is preferably less than approximately 13nm. Preferably, the AlInAs intermediate layer has a thickness less than 5nm, further preferably of 3nm to 5nm. This thin intermediate layer improves the interface quality without overly reducing the effect of the greater electron confinement afforded by the large band gap and particularly large conduction band offset provided by the AlAsSb layers.
The HEMT preferably includes an AlInAs protection layer on the AlAsSb barrier layer, the gate layer being provided on the AlInAs upper gate contact layer. Further, the HEMT preferably has an AlAsSb buffer layer; and an AlInAs lower intermediate layer on the AlAsSb buffer layer, wherein the InGaAs channel layer is formed on the AlInAs lower intermediate layer.
The HEMT may be formed on a substrate with an AlInAs buffer layer on the substrate, the AlAsSb buffer layer being on the AlInAs buffer layer.
The AlInAs lower intermediate layer may also have a thickness of 3nm to 5nm.
The or each AlAsSb or GaAlAsSb layer preferably has the formula AlAsxSbi_x where x is preferably in the range 0.45 to 0.65, preferably 0.56. The use of the same material for each AlAsSb layer eases manufacture, but different values of x can be used for different layers if required.
The or each AlInAs layer preferably has the formula Aly Ini_y As where y is in the range 0.4 to 0.6, preferably 0.48. Again, the use of the same material for different layers eases manufacture but different values of y can be used for different layers if required.
The InGaAs channel layer preferably has a formula Inz Gai_z As where z is in the range 0.4 to 0.80, preferably 0.53.
The invention also relates to a method of manufacture of a high electron mobility transistor, comprising: growing an AlInAs buffer layer; growing a buffer layer on the AlInAs lower buffer layer the buffer layer being of AlAsSb or GawAli_wAsSb with w less than or equal to 0.2; growing an AlInAs lower intermediate layer on the AlAsSb buffer layer; growing an InGaAs channel layer on the AlInAs lower intermediate layer; growing an AlInAs upper intermediate layer on the InGaAs channel layer; growing a barrier layer on the AlInAs intermediate layer the barrier layer being of AlAsSb or GawAli_wAsSb with w less than or equal to 0.2; growing an AlInAs protection layer on the AlAsSb barrier layer; growing an InGaAs cap layer on the AlInAs gate intermediate layer; forming source and drain contacts to contact the InGaAs channel layer; and depositing a gate layer on the AlInAs intermediate layer in the recess region for controlling conduction in a channel in the InGaAs channel layer between the source and drain contacts.
The source and drain contacts may be formed either before or after the gate. .
Brief description of the drawings For a better understanding of the invention, an embodiment will be described, purely by way of example, with reference to Figures 1 and 2, wherein
Figure 1 shows a side view of a HEMT structure according to the invention; and Figure 2 shows a band diagram of the HEMT structure of claim 1. The figures are schematic and not to scale.
Detailed description of the invention
The HEMT is formed on a semiconductor substrate 2. Any suitable material may be used, such as InP. In some cases, for example when using a Si or GaAs substrate, a metamorphic buffer may be used.
A number of layers are epitaxially grown on substrate 2. The layers may be grown by any suitable method, including for example MOCVD, MBE, and other known semiconductor growth processes.
The first layer grown is a relatively thick buffer layer 4 of AlInAs. In the specific embodiment described the AlInAs is of the formula Aly Ini_y As with y = 0.48. However, the exact composition may be varied if required.
On this layer is grown a buffer layer 6 of high bandgap AlAsSb. The AlAsSb has formula Al Asx Sbi_x with x=0.56. Again, the exact composition may be varied as desired.
A thin lower intermediate layer 8 of AlInAs is then grown. In this embodiment, the AlInAs is of the formula Aly Ini_y As with y = 0.48, the same as the lower layer. The exact composition may be varied as desired.
Next, the InGaAs channel layer 10 is grown. The InGaAs channel layer has a formula Inz Gai_z As where z is in the specific embodiment 0.53. Again, the exact composition can be varied. Above the InGaAs channel layer 10 is formed an AlInAs upper intermediate layer 12 of the same composition as the lower intermediate layer 8. Again, this is not essential. The layer 12 contains a doping plane supply layer, which creates a high-density 2D electron gas in the channel.
An AlAsSb barrier layer 14 is formed on the AlInAs upper intermediate layer, in the embodiment of the same composition as lower layer 6
Above the barrier layer 14 is an upper protection layer 16, of AlInAs, again in the embodiment of the same material as the other AlInAs layers.
This upper protection layer 16 deals with the difficulty that AlAsSb is highly oxidisable and oxidises very rapidly. In many semiconductors, for example AlInAs, only a surface layer of a thickness less than 3nm oxidises. In contrast, the whole thickness of an AlAsSb layer can oxidise, ruining the device properties. The upper protection layer 16 protects the AlAsSb from this oxidation.
A cap layer 17 is formed on the upper barrier layer 16. A recess 19 is then formed, removing the cap layer 17 from a region to form the gate but leaving the cap layer 17 present in the region where the source and drain contacts 20,22 are to be formed. The cap layer is a low band-gap layer, for example InGaAs, which protects the upper barrier layer 16 from oxidation in the access region where the source and drain contacts are formed. A metal gate 18 is formed on the upper barrier layer 16 in the recess 19.
Source 20 and drain 22 contacts are formed, on the cap layer 17, extending to the channel layer 10. These contact the two dimensional electron gas 24 (2DEG) formed in the channel layer 10 at the heterojunction interface between the channel layer 10 and upper intermediate layer 12. The electrons in the 2DEG are supplied by the doping plane localised in the AlInAs upper intermediate layer 12. In the specific embodiment, diffusions 20,22 are used but any suitable contacts may be used.
In use, a voltage applied to the gate controls conduction between the source and drain contacts 20,22 through the 2DEG 24 channel. Note that the use of the term "2DEG" is not intended to limit the invention to the case where only a single quantum state is occupied and is intended instead to relate to an substantially two dimensional channel confined by the heterostructure.
The transistor formed may be an enhancement type transistor or a depletion type transistor. In an enhancement type transistor, the transistor needs to be turned on by applying a positive voltage to the gate 18 to create the 2DEG channel. In a depletion type transistor, a 2DEG channel 24 is present in the absence of a voltage, and a voltage is applied to the gate 18 to turn the device off. The doping levels and the barrier layer thickness may be varied as required to achieve the desired properties.
The upper layer 12 may be doped as required to ensure sufficient electrons density in the channel. The doping may be doping of the entire upper intermediate layer or only part of it. Alternatively or additionally, a delta doping layer may be provided at some point in this region, either above, below, or within the upper layer 12
Doping may also be provided in other layers, particularly but not exclusively in lower layer 6, for example. The band diagram of Figure 2 illustrates the band diagram of the device of Figure 1. The conduction band 30, valence band 32 and Fermi energy level 34 are all shown. The layers are indicated with the same reference numbers as in Figure 1.
The band gap of Alo.4sIno.52As is 1.45eV and of AlAso.56Sbo.44 is 2.45 eV. The wider band gap of AlAso.56Sbo.44 is reflected particularly in the conduction band offset of AlAso.56Sbo.44 with Ino.53Gao.47As of 1.74eV. This may be compared with the conduction band offset of Alo.4sIno.52As with Ino.53Gao.47As of 0.52eV.
This enhanced conduction band offset greatly improves the confinement of the 2DEG 24 and hence gives improved dynamic and static properties. In particular, the improved confinement caused by the conduction band offset of the channel 10 with the barrier 14 minimises the short channel effect.
The large conduction band offset between the gate 18 and the channel layer 10 of upper AlAsSb layer 14 has a further beneficial effect of reducing the gate current, increasing the breakdown voltage, and the positive gate voltage swing. The good heterointerfaces between the InGaAs channel layer 10 and the AlInAs upper and lower intermediate layers 8,12 ensures a suitably high interface quality and hence electron mobility and so good performance.
A low output conductance and high transconductance may be achieved.
Although the specific embodiment describes a number of layers, variations are possible. In particularly, the buffer layer 6 may be replaced by other suitable buffers, including for example a superlattice buffer. The superlattice buffer may also be of AlAsSb and AlInAs, for example, or other materials may also be used.
In an alternative embodiment, the material of the buffer layer 6 and barrier layer 14 is
GawAli_wAsSb instead of AlAsSb. Typically, w will be less than 0.2. Thus, part of the Al in the AlAsSb of the first embodiment is replaced by Ga. The buffer layer 6 and barrier layer 14 will be more stable, since GawAli_wAsSb is less oxidisable. Although the introduction of Ga reduces the band gap and the conduction band offset between the buffer and barrier layers
6,14 and channel layer 10, the level is still very high for w <0.2 compared to the conduction band offset between InGaAs and InAlAs. The exact value of w may be selected based on a tradeoff between the improved material properties of higher values of w and beneficial band gap of low values of w.
Indeed, the other semiconductor layers may also include small amounts of other elements. Thus, for example the layers described as InGaAs or AlInAs layers may include small but non-trivial amounts of other elements, for example phosphide, although preferably less than 20% of the group III or group V elements are replaced by other elements in this way.

Claims

1. A high electron mobility transistor, comprising: an InGaAs channel layer (10); an AlInAs upper intermediate layer (12) on the InGaAs channel layer (10); a barrier layer (14) on the AlInAs upper intermediate layer (12), the barrier layer (14) being of AlAsSb or GawAli_wAsSb with w less than or equal to 0.2; and a gate layer above the AlInAs intermediate layer (18) for controlling conduction in a channel in the InGaAs channel layer (10).
2. A high electron mobility transistor according to any preceding claim wherein the AlInAs upper intermediate layer (12) has a thickness of 3nm to 5nm.
3. A high electron mobility transistor according to claim 1 or 2, further comprising an AlInAs protection layer (16) on the barrier layer (14), the gate electrode (18) being provided on the AlInAs protection layer (16).
4. A high electron mobility transistor, according to claim 1, 2 or 3, further comprising: an buffer layer (6), the buffer layer (6) being of AlAsSb or GawAli_wAsSb with w less than or equal to 0.2; and an AlInAs lower intermediate layer (8) on the buffer layer (6); wherein the InGaAs channel layer (10) is formed on the AlInAs lower intermediate layer (8).
5. A high electron mobility transistor according to claim 4, further comprising: a substrate (2); and a AlInAs lower buffer layer (4) on the substrate (2); wherein the buffer layer (6) is on the AlInAs lower buffer layer (4).
6. A high electron mobility transistor according to claim 4 or 5 wherein the AlInAs lower intermediate layer (8) has a thickness of 3nm to 5nm.
7. A high electron mobility transistor according to any preceding claim wherein the barrier layer (14) and the buffer layer (6) if present has a formula Al Asx Sbi_x where x is in the range 0.45 to 0.65, preferably 0.56.
8. A high electron mobility transistor according to any of claims 1 to 6 wherein the barrier layer (14) and the buffer layer (6) if present has a formula formula Gaw Al1 -w Asx Sbi_x where x is in the range 0.45 to 0.65, preferably 0.56.
9. A high electron mobility transistor according to any preceding claim wherein the or each AlInAs layer has a formula Aly Ini_y As where y is in the range 0.4 to 0.6, preferably
0.448.
10. A high electron mobility transistor according to any preceding claim wherein the InGaAs channel layer has a formula Inz Gai_z As where z is in the range 0.4 to 0.8, preferably 0.53.
11. A method of manufacture of a high electron mobility transistor, comprising: growing an AlInAs lower buffer layer (4); growing a buffer layer (6) on the AlInAs lower buffer layer (4) the buffer layer (6) being of AlAsSb or GawAli_wAsSb with w less than or equal to 0.2; growing an AlInAs lower intermediate layer (8) on the AlAsSb buffer layer (6); growing an InGaAs channel layer (10) on the AlInAs lower intermediate layer (8); growing an AlInAs upper intermediate layer (12) on the InGaAs channel layer (10); growing a barrier layer (14) on the AlInAs intermediate layer (12) the barrier layer (14) being of AlAsSb or GawAli_wAsSb with w less than or equal to 0.2; growing an AlInAs protection layer (16) on the barrier layer (14). growing an InGaAs cap layer (17) on the AlInAs protection layer (16); forming a recess region (19) in which the InGaAs cap layer (17) is removed; forming source and drain contacts (20,22) to contact the InGaAs channel layer (10); and depositing a gate layer (18) in the recess region (19) for controlling conduction in a channel in the InGaAs channel layer (10) between the source and drain contacts.
PCT/IB2007/052744 2006-07-12 2007-07-10 High electron mobility transistor. WO2008007335A2 (en)

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