JPH06188274A - Hetero junction field effect transistor - Google Patents

Abstract

PURPOSE:To control a decrease in gate forward allowable voltage and gate breakdown strength and control an increase in noise, by using a semiconductor material of reverse conductive type to an operating layer as a cap layer or a spacer layer in EFET or DFET. CONSTITUTION:An operating layer 1 is growth to a thickness of 15nm on a buffer layer 4 and sequentially an un-AlGaAs barrier layer 2 is growth to 10nm and a p-GaAs layer 3 is grown to 10nm by a MBE method. Then, only the element forming region is left and the other regions are isolated by a wet etching. After this, a gate electrode 6 (WSix) is formed and an SiO2 film is coated and then only the regions forming high concentration conductive layers 5 are removed by a dry etching, After recovering damage of the dry etching by a short-time annealing, sing the SiO2 film as a mask, an n-GaAs is selectively growth by a MOVPE method and the high concentration conductive layers 5 are formed, and ohmic electrodes 7 are installed y a lift-off method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction field effect transistor, and more particularly to a device structure for suppressing a decrease in gate forward voltage and a decrease in gate breakdown voltage due to temperature rise.

[0002]

2. Description of the Related Art AlGaAs / GaAs structures and InAlAs / I
In a heterojunction FET of nGaAs structure, an AlGaAs layer or In
To prevent oxidation of the AlAs layer, undoped Ga
It is necessary to provide a cap layer composed of an As layer or an InGaAs layer. Further, in the case of depletion type FET (DFET), a spacer layer for adjusting the threshold voltage (Vth) can be used instead of the cap layer. As these conventional examples, enhancement type FET (EFET) and DFET
A heterojunction FET having an E / D structure in which the same is formed on the same semiconductor substrate is an electronic electron device meeting proceedings page 688 to page 691 (I
EDM88 Technical.Digest p.688-691 (1988))
Up to. A simplified sectional view is shown in FIG. 3, in which an un-GaAs buffer layer 4, an n-GaAs operating layer 1, and
un-AlGaAs barrier layer 2, un-GaAs cap layer 3, AlG
The aAs etching stop layer 11 and the un-GaAs spacer layer 9 are epitaxially grown, the DFET is provided with the gate electrode 6 on the spacer layer 9, and the EFET is removed by removing the etching stop layer 11 to form the gate electrode 6. High-concentration conductive layer for reducing the contact resistance between the operating layer 1 and the ohmic electrode 7.
The (ohmic layer) 5 is formed by ion implantation, and a wiring process is performed to complete the FET of this conventional example.

[0003]

In the above-mentioned prior art heterojunction FET, the gate forward direction allowable voltage (Vf) value can be increased by the barrier layer 2 provided between the gate electrode 6 and the channel layer 1, but the element is generated by heat generation. When the temperature rises, the conductivity of the undoped GaAs cap layer 3 and the spacer layer 9 increases to a non-negligible level, and the cap layer 3 and the spacer layer 9 serve as paths between the gate electrode 6 and the ohmic layer 5. Lateral leakage current occurs, and the gate forward voltage (V
f) and the gate breakdown voltage (BVgs) are lowered. This problem becomes more serious as the cap layer 3 and the spacer layer 9 are made thicker.

In addition, the EFET cap layer 3 or D
When the thickness of the FET spacer layer 9 is 10 nm or more,
When a reverse voltage is applied to the gate, carriers of the same conductivity type as those of the operating layer 1 are accumulated at the interface (AlGaAs / GaAs interface) between the cap layer 3 or the spacer layer 9 and the barrier layer 2, and the accumulated carriers are noise factors. There is a problem that becomes. For example, gate electrode / un-GaAs / un-AlGaAs /
When a negative gate voltage is applied to an n-channel FET having an n-GaAs structure, a two-dimensional electron gas is generated at the interface between the cap layer 3 or the spacer layer 9 and the barrier layer 2 to increase noise.

It is an object of the present invention to provide a device structure that suppresses a decrease in Vf value and BVgs and does not increase noise.

[0006]

The above object is to achieve the above-mentioned EFE.
This can be achieved by using a semiconductor material having a conductivity type opposite to that of the operating layer for the cap layer or the spacer layer in T or DFET. The impurity concentration of the cap layer or spacer layer is
Since the cap layer or the spacer layer, the barrier layer 2, and the operation layer 1 form a PIN junction to increase the gate capacitance,
It is desirable to suppress it to about 10 ¹⁵ to 10 ¹⁷ / cm ³ .

Further, as the material of the cap layer or the spacer layer, an amorphous semiconductor having a conductivity type opposite to that of the undoped or active layer or a compound semiconductor having a non-stoichiometric composition (non-stoichiometry) may be used.

[0008]

The operation of the present invention will be described below with reference to the drawings.
FIG. 1 shows an un-AlGaAs barrier layer 2 on an n-GaAs active layer 1.
And the p-GaAs cap layer 3 are provided, the impurity concentration of the cap layer 3 is 1 in order to suppress the increase of the gate capacitance.
0 ¹⁶ / cm ³ units.

When the device temperature rises, electrons diffuse from the high-concentration operating layer 1 to the cap layer 3, so that in the conventional undoped cap layer, the conductivity of the cap layer remarkably rises due to the injected electrons. In the case of the p-GaAs cap layer 3, the injected electrons are compensated. Also, p-
The interface between the GaAs cap layer 3 and the un-AlGaAs barrier layer 2 is 2
Since the dimensional electron gas is unlikely to be generated, the electrons leaked from the operating layer 1 are not accumulated as the two-dimensional electron gas. In the case of p-channel, the n-GaAs cap layer 3 and
Since two-dimensional hole gas is unlikely to be generated at the interface of the un-AlGaAs barrier layer 2, holes leaked from the operation layer 1 are not accumulated. Therefore, it is possible to suppress the decrease in Vf value and BVgs due to the lateral leakage current generated between the gate electrode 6 and the ohmic layer 5. Also, the cap layer 3
It is also possible to suppress an increase in noise due to the curia injected into the.

To specifically explain the effects of the present invention, HI
GFET (Heterostructure Insula-ted Gate FET) D
The transfer characteristics of a CFL (Direct Coupled FET Logic) inverter circuit are shown in FIG. 2A shows the case where undoped GaAs is used for the cap layer 3, and FIG. 2B shows the case where a p-type GaAs layer is used, showing the characteristics at 20 ° C., 80 ° C., and 150 ° C., respectively. Since the high level of the output voltage (V ₀ ) is clamped by the Vf value of the FET in the next stage, its temperature dependence matches the temperature dependence of the Vf value. Therefore, when an un-Al _0.3 Ga _0.7 As layer with a thickness of 10 nm is used for the barrier layer 2,
The theoretical temperature coefficient of high level voltage is about -0.8 mV / deg.
Is calculated, but in reality, the above-mentioned lateral leakage current is V
Since the f value decreases, it becomes larger than the theoretical value. For example, when undoped GaAs with a film thickness of 10 nm is used for the cap layer 3, the temperature coefficient of the high level voltage is about -1.2 mV / deg.
(Fig. 2 (a)), which is larger than the theoretical value. However, when 2 × 10 ¹⁶ / cm ³ of p-GaAs is used for the cap layer 3, the temperature coefficient is about −0.9 mV / deg ((FIG. 2 (b))), which is close to the theoretical value. .

Further, in the E / D circuit, there is a problem that carriers diffuse from the high-impurity concentration ohmic layer 5 to the spacer layer 9 to lower the gate withstand voltage of the DFET, but the spacer layer 9 is opposite to the ohmic layer 5. In the present invention using the conductive type semiconductor, the carrier diffusion can be suppressed, and the reduction of the gate withstand voltage of the DFET can be suppressed.

Further, when an amorphous semiconductor is used for the cap layer 3 and the spacer layer 9, the amorphous semiconductor has a larger bandgap and a smaller electric conductivity than the crystalline semiconductor, so that even if it is undoped. It has the effect of the present invention. Of course, the amorphous semiconductor layer may be of the conductivity type opposite to that of the operating layer 1.

Further, since the V group and VI group elements have a large electron affinity, in the case of the n-channel, the V group and VI group are excessive III.
The effect of the present invention is also obtained by using an undoped non-stoichiometric compound semiconductor of Group V or Group IIVI for the cap layer 3 or the spacer layer 9. Of course, operation layer 1
It is also possible to use the opposite conductivity type. Also, p
In the case of a channel, the effect of the present invention can be obtained by using an undoped compound semiconductor in which V group or VI group is deficient.
Of course, the conductivity type opposite to that of the operating layer 1 can be used.

[0014]

EXAMPLES Example 1 As one example of the present invention, p-GaAs / un-AlGaAs / n-
GaAs HIGFET (Heterostructure Insulated)
A cross-sectional view of the gate FET) is shown in FIG. 1, and its manufacturing process is shown in FIG.

(A) On the p-GaAs (3 × 10 ¹⁶ / cm ³ ) buffer layer 4, ¹⁵ n of n-GaAs (3 × 10 ¹⁸ / cm ³ ) operating layer 1 is formed.
m, un-AlGaAs barrier layer 2 with 10 nm, p-GaAs (1 × 10
¹⁶ / cm ³ ) Cap layer 3 with 10 nm, MBE (Molecular Bea)
m Epitaxy) method. (B) After leaving only the element formation region, other regions are separated by wet etching to form a gate electrode (WSix) 6, and a SiO ₂ film 12 is coated on the high concentration conductive layer 5 Only the region for forming is removed by dry etching.

In order to reduce the source parasitic resistance (Rs), it is also possible to ion-implant the donor impurity using the gate electrode 6 as a mask after forming the gate electrode 6.

(C) After recovering the damage of dry etching by RTA (short-time annealing), MOVPE (Metal Organic Vapor Phase Epi) is used with the SiO ₂ film 12 as a mask.
n-GaAs (3 × 10 ¹⁸ / cm ³ ) is selectively grown by the taxy method to form the high-concentration conductive layer 5, and the ohmic electrode (Au / Ni /
The present invention is completed by providing AuGe) 7 by the lift-off method.

The high concentration conductive layer 5 can also be formed by n-Ge and n-InGaAs, it is also possible to use the _{n-In X Ga 1-X} As gradient composition layer in non-alloy ohmic structure is there.

In order to improve the performance, the operation layer 1 can use InGaAs instead of GaAs, and GaAs / In
GaAs / GaAs, or InGaAs / InAs / InGaA
It is also possible to have multiple layers of s structure. Barrier layer 2 is Al
Instead of GaAs, InGaP or GaAsP may be used, and the cap layer 3 may be formed of p-InGaP, p-GaAsP, GaAs with a large As composition ratio, or amorphous GaAs.

In this embodiment, the case where the barrier layer 2 is an undoped layer has been described. However, in order to improve the Vf value, the barrier layer 2
It is also possible to use a p-type semiconductor layer of 1 × 10 ¹⁴ to 1 × 10 ¹⁷ / cm ³ . In this case, the operation layer 1 is 1 × 10
If it is an n-type semiconductor of ^{18 to} 5 × 10 ¹⁹ / cm ³ , the barrier layer 2 is depleted by the junction with the operating layer 1 and the gate capacitance is not increased.

When the barrier layer 2 has the same conductivity type as that of the operating layer 1, a heterojunction MESFET is obtained. Even in this case, however, by using a semiconductor having a conductivity type opposite to that of the operating layer 1 for the cap layer 3, the Vf value and the gate breakdown voltage are increased. Can be improved.

Although the above-mentioned embodiments have been described focusing on the AlGaAs / GaAs structure, AlGaP / GaP, InAlAs / InGa.
F of As, AlGaSb / GaSb, AlSb / InAs structure, etc.
It is also possible to apply to ET.

Although the case of the n-type channel has been described above, the present invention can also be applied to a p-type channel FET. In this case, the cap layer 3 has a low concentration of an n-type semiconductor or V.
A non-stoichiometry layer lacking a group atom or an amorphous layer may be used.

Example 2 When the gate electrode is formed by the lift-off method, the AlGaAs layer is exposed only just before the gate metal is deposited, so that the AlGaAs layer is less oxidized and the gate electrode 6 and the AlG layer are not oxidized.
It is not necessary to provide a cap layer at the interface of the aAs layer 2. However, in the E / D configuration circuit, the spacer layer 9 is necessary for the DFET, and one example thereof is shown in FIG.

In the conventional structure using the undoped layer as the spacer layer 4, when the element temperature rises, carriers diffuse from the operating layer 1 and the high-concentration conductive layer 5 to the spacer layer 9 to lower the Vf value and BVgs. However, in the present invention, the spacer layer 9
By using a semiconductor layer having a conductivity type opposite to that of the operating layer 1,
It is possible to suppress a decrease in the value and BVgs.

Embodiment 3 The present invention is based on HEMT (High Electron Mobility Transisto).
It can also be used for an element having the r) structure, and one example thereof is shown in FIG. Since the gate electrode is formed by the lift-off method in the usual HEMT, it is not necessary to provide the cap layer 3, but in the HEMT having the E / D structure, the spacer layer 9 is formed in the DFET.
Must be provided, and the above-mentioned lateral leakage current occurs when the temperature rises. However, in the present invention, as shown in FIG. 6A, p-GaAs or p-InGaAs is formed on the spacer layer 9.
The lateral leakage current can be reduced by using
In the region of the high-concentration conductive layer 5, the spacer layer 9 changes to n-type by ion implantation, so that the parasitic resistance is not increased. Further, in the conventional HEMT, a two-dimensional electron gas (2DEG) was easily generated at the interface between the spacer layer 9 and the electron supply layer 8, but in the present invention, 2DEG is not accumulated and noise can be reduced.

FIG. 6B shows a case where a p-type or amorphous cap layer 3 is stacked on the electron supply layer 8 in order to improve the gate breakdown voltage of the EFET, and the cap layer 3 and the spacer layer 9 are formed. If the same material is used, the etching stop layer 13 is required, but if the material is different, the etching stop layer 13 can be omitted.

In the InAlAs / InGaAs HEMT, the etching stop layer 13 can be omitted, and the cap layer 3 usually uses InGaAs. However, the spacer layer 9 also has InGa
When As is used, the height of the Schottky barrier is lowered. Therefore, it is necessary to use GaAs or InAlAs for the spacer layer 9. However, in the conventional undoped spacer layer, the DFET cap layer 3 forms a quantum well. However, the accumulated carriers cause noise. However, if a p-type semiconductor is used for the spacer layer 9, the holes in the spacer layer 9 can compensate the electrons in the quantum well and reduce noise.

Although the above embodiment has been described with respect to the case of the n-type channel, the present embodiment can also be applied to the HEMT of the p-type channel.

[0030]

According to the present invention, the increase of the gate current due to the temperature rise can be suppressed and the decrease of the Vf value and the gate breakdown voltage can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view of a HIGFET according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of the effect of the present invention due to the temperature dependence of the transfer characteristic of the DCFL inverter circuit.

FIG. 3 is a sectional view of a conventional heterojunction FET.

FIG. 4 is a manufacturing process diagram of the HIGFET of FIG. 1.

FIG. 5 is a HIGFET having an E / D configuration according to a second embodiment of the present invention.
FIG.

FIG. 6 is a sectional view of a HEMT according to a third embodiment of the present invention.

[Explanation of symbols]

1. Active layer, 2. Barrier layer, 3. Cap layer, 4. Semiconductor buffer layer, 5. High-concentration conductive layer, 6. Schottky electrode,
7. Ohmic electrode, 8. Carrier supply layer, 9. Spacer layer, 10.2DEG, or 2DHG, 11. Undoped layer, 12. SiO ₂ , 13. Etch stop layer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Junji Shigeta 1-280, Higashikoigokubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (6)

[Claims] 1. An n-type conductivity type first semiconductor layer, a second semiconductor layer forming a heterojunction with the first semiconductor layer, and the first semiconductor layer of the second semiconductor layer. Has a gate electrode formed on the opposite side, the electron affinity of the second semiconductor layer is smaller than the electron affinity of the first semiconductor layer, and the second semiconductor layer is intentionally doped with impurities. In the heterojunction field effect transistor, which has no or is doped with impurities exhibiting p-type conductivity to the extent that it is completely depleted by the junction with the first semiconductor layer, the second semiconductor layer and the gate electrode are provided. P-type third between
A heterojunction field effect transistor, wherein the semiconductor layer is formed. 2. A first semiconductor layer of p-type conductivity type, a second semiconductor layer forming a heterojunction with the first semiconductor layer, and the first semiconductor layer of the second semiconductor layer. Has a gate electrode formed on the opposite side, and the sum of the electron affinity and the energy gap of the second semiconductor layer is larger than the sum of the electron affinity and the energy gap of the first semiconductor layer. In a heterojunction field effect transistor, the layer is not intentionally doped with impurities or is doped with impurities exhibiting n-type conductivity to the extent that it is completely depleted by the junction with the first semiconductor layer, A heterojunction field effect transistor, wherein an n-type third semiconductor layer is formed between the second semiconductor layer and the gate electrode. 3. An n-type conductivity type first semiconductor layer, a second semiconductor layer forming a heterojunction with the first semiconductor layer, and the first semiconductor layer of the second semiconductor layer. Has a gate electrode formed on the opposite side, the electron affinity of the second semiconductor layer is smaller than the electron affinity of the first semiconductor layer, and the conductivity type of the second semiconductor layer is the first semiconductor. In a heterojunction field effect transistor having the same conductivity type as that of p type conductivity type to the extent that the second semiconductor layer is completely depleted by the junction with the second semiconductor layer between the second semiconductor layer and the gate electrode. A heterojunction field effect transistor, characterized in that a third semiconductor layer doped with an impurity is formed. 4. A first semiconductor layer of p-type conductivity type, a second semiconductor layer forming a heterojunction with the first semiconductor layer, and the first semiconductor layer of the second semiconductor layer. Has a gate electrode formed on the opposite side, and the sum of the electron affinity and the energy gap of the second semiconductor layer is larger than the sum of the electron affinity and the energy gap of the first semiconductor layer. In a heterojunction field effect transistor, the conductivity type of the layer being the same as the conductivity type of the first semiconductor,
The second semiconductor layer is formed between the second semiconductor layer and the gate electrode.
N to the extent that it is completely depleted by the junction with the semiconductor layer of
A heterojunction field effect transistor, characterized in that a third semiconductor layer doped with an impurity exhibiting a conductivity type is formed. 5. A first semiconductor layer not intentionally doped with impurities, a second semiconductor layer forming a heterojunction with the first semiconductor layer, and the first semiconductor layer of the second semiconductor layer. The second semiconductor layer has an electron affinity smaller than the electron affinity of the first semiconductor layer or an electron affinity and an energy gap of the second semiconductor layer. The sum is larger than the sum of the electron affinity and energy gap of the first semiconductor layer, and the second semiconductor layer is doped with impurities to the extent that carriers can be supplied to the first semiconductor layer. Heterojunction electric field effect In the transistor, a heterojunction field effect transistor characterized in that a third semiconductor layer having a conductivity type opposite to that of the second semiconductor layer is formed between the second semiconductor layer and the gate electrode. . 6. The heterojunction field effect transistor according to claim 1, wherein the third semiconductor layer is made of an amorphous semiconductor or a compound semiconductor having a non-stoichiometric composition.