JPH09270522A - Field-effect transistor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the source resistance and improve the current driving capability, by forming a barrier layer using a semiconductor layer with a greater band gap than a channel layer and with no impurity added thereto, and forming source and drain regions using a high-density semiconductor layer. SOLUTION: In a field-effect transistor using a III-V compound semiconductor, a barrier layer 13 and a channel layer 12 are formed in a stacked manner under a gate electrode 20. The barrier layer 13 is made of a semiconductor layer having a greater band gap than a semiconductor layer constituting the channel layer 12 and with no impurity added thereto. In the barrier layer 13, a doped layer 14 doped with impurity on one atomic surface thereof is formed. Source and drain regions 30 are made of a high-density semiconductor layer. The barrier layer 13 restrains a gate leak, and the doped layer 13 improves the currents driving capability. Also, the source and drain regions 30 realize reduction in resistance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor using a III-V compound semiconductor and a method for manufacturing the same, and more particularly, to a p-channel field effect transistor suitable for a complementary element. The present invention relates to a field effect transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art III-V represented by GaAs and InP
Field effect transistors (F) such as MESFETs and high electron mobility transistors (HEMTs) using group III compound semiconductors
ET) is widely applied to high frequency devices and low noise devices. Recently, attention has been paid to its low power consumption, and it has been used as an optical communication IC. In particular, when a complementary circuit is composed of a compound semiconductor, a high-speed and low-power-consumption circuit far exceeding the performance of a silicon CMOS can be expected, and development is being actively conducted in various places.

The problem here is the improvement of the performance of the p-type element. For example, in the case of GaAs, the mobility of electrons is several times faster than that of Si, but the mobility of holes is almost the same as that of Si. One of them is a method of forming a heterojunction to generate a two-dimensional hole gas and using the same as in a HEMT using a two-dimensional electron gas. Actually J. K. Abr
Okwah et al. and Tagawa et al. attempt to fabricate a p-channel device with this structure. The device structure of Abrokwah et al. Is based on i-AlGaAs / i-InGaAs.
ISFET (Metal-Insulater-Semiconductor FET)
Tagawa et al. Have a p-channel HFET (Heterojunction FE) composed of p-AlGaAs / InGaAs.
T). It is reported that these structures are used to improve the hole mobility and gm. (JKAbrokw
ah et al. GaAS IC Symposium Digest p127, 1993: Tagawa et al., Spring 1994 Applied Physics Preprints NO. 3 p11
87).

As another method, there is a method using a strained grating. That is, since InGaAs has a larger lattice constant than GaAs, if InGaAs is grown on GaAs with a large In composition, a strain stress is generated with GaAs. When a p-type dopant is added to such a strained layer, the mobility of the p-type impurity is improved due to a change in the band structure. Utilizing this property, a device in which a strain channel is doped has also been manufactured. (PPRuden et al. IEEE Transac
tion on Electron Devices Vol.36 p2371,1989)

[0005]

The above-mentioned prior art has the following problems. First, in an HFET utilizing a two-dimensional hole gas, AlGa is used as a hole supply layer.
Since the As layer is doped, the structure is liable to cause gate leakage. AlGa in MISFET
Since the As layer is non-doped as a barrier layer, there is little gate leakage, but there is a problem that the current driving capability is lowered because the channel is not doped.
Also, including the devices that dope the strain channel,
In the device of the conventional example, there is a problem that the resistance of the barrier layer is high, so that the source resistance Rs becomes extremely large.

[0006] An object of the present invention is to solve such a problem.
An object of the present invention is to provide a channel field effect transistor and a method of manufacturing the same.

[0007]

The field effect transistor of the present invention uses a III-V compound semiconductor substrate.
A barrier layer and a channel layer are formed in a stacked state under the gate electrode, and the barrier layer is formed of a semiconductor layer having a larger forbidden band width than a semiconductor layer forming the channel layer, without adding impurities, and a source, The drain region is formed of a high-concentration semiconductor layer. Here, the barrier layer has a structure in which an impurity serving as a hole supply layer is added to or near one atomic plane. Further, the channel layer may be formed of a semiconductor layer to which impurities are added, which has a band gap smaller than that of the substrate semiconductor and has lattice distortion.

Further, according to the manufacturing method of the present invention, a semiconductor layer serving as a buffer layer, a high-purity semiconductor layer serving as a channel layer, and a barrier layer having a band gap larger than that of the channel layer are formed on a semi-insulating semiconductor substrate. A step of sequentially epitaxially growing a semiconductor layer, a step of forming a mask on the surface of the barrier layer, and a step of selectively removing the barrier layer and the channel layer with the gate portion left, and a metal-organic vapor phase epitaxy at the removed portion. Forming a high-concentration impurity semiconductor layer by a selective growth method using a sputtering method or a metal organic molecular beam epitaxy method, forming a gate electrode on the gate portion on the surface of the barrier layer, and the surface of the high-concentration impurity semiconductor layer And a step of forming respective source and drain electrodes. Here, impurities are added to the barrier layer at or near one atomic plane. Further, as the channel layer, a semiconductor layer in which impurities are added and which has a band gap smaller than that of the substrate semiconductor and has lattice distortion is used.

[0009]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing the structure of a first embodiment of the field-effect transistor of the present invention. In FIG. 1, i-GaAs (3) is formed on a semi-insulating GaAs substrate 10.
00 nm) is formed.
A high-purity i-GaAs layer (15 n
m) is formed. Further, a barrier layer 13 made of i-Al _0.8 Ga _0.2 As (30 nm) is formed thereon. A gate electrode 20 made of WSi is formed on the surface of the barrier layer 13. Here, in order to increase the Schottky barrier, the Al of the barrier layer 13 is increased to 0.8. In the barrier layer 13, a doped layer 14 in which Be, which is a p-type impurity, is delta-doped is formed at a position 10 nm above the channel layer 12. The area density is 1
× 10 ¹³ cm ^-2 . In this case, doping is performed only on one atomic plane, but step doping may be performed in a narrow region of 10 nm or less. Further, the source and drain regions 30 are each formed by ap ⁺ -GaAs selective growth layer (500 nm, 1 × 10 ²⁰ cm ⁻³ ), and an ohmic metal electrode 40 made of Ti / Pt / Au is formed on the surface of each region 30. Have been.

According to this structure, the gate leak can be suppressed by forming the barrier layer 13 below the gate electrode 20 with a large forbidden band width and without adding impurities. In addition, the channel layer 12 has a heterojunction structure with the barrier layer 13 immediately above the channel layer 12, and the p-type impurity provided in the barrier layer 13 is added to one atomic plane or an extremely narrow region, so that the gate electrode A sufficient two-dimensional hole gas can be obtained with the non-doped layer directly under 20. Thereby, a high current driving capability can be obtained. Further, since each of the source and drain regions is formed of the low-resistance P ⁺ semiconductor layer 30, the source resistance can be reduced and the device characteristics such as gm can be improved.

In the structure of the first embodiment, when the gate length was 0.5 μm and the device characteristics were evaluated, gm = 100 ms / mm and Rs = 2 Ωmm, showing excellent characteristics as a p-channel FET. Also, the forward rise voltage Vf = −2.0 V, the gate breakdown voltage BVg
Showed a sufficiently large value of 10 V. Note that it has been confirmed that the use of an i-In _0.2 Ga _0.8 As layer as a channel layer further increases the mobility and can improve device characteristics.

FIG. 2 is a sectional view showing a method of manufacturing the field effect transistor according to the first embodiment in the order of steps. First, as shown in FIG. 2A, the semi-insulating GaAs substrate 1
0 on the surface of the substrate by molecular beam epitaxy (MBE).
Growing a GaAs buffer layer 11 to a thickness of 300 nm;
An i-In _0.2 Ga _0.8 As channel layer 15 is grown thereon to a thickness of 15 nm, and an i-Al _0.8
A Ga _0.2 As barrier layer 13 is grown to a thickness of 30 nm. Then, Be14, which is a p-type impurity, is delta-doped at a concentration of 1 × 10 ¹³ cm ⁻² to only one atomic plane at a depth of 10 nm above the channel layer. When a hole measurement was performed with this structure, a two-dimensional hole concentration of 2 × 10 ¹² c
m ^-2 and a mobility of 200 cm2 / Vs.

Next, as shown in FIG.
The barrier layer 13 and the channel layer 12 in the source and drain regions are removed by a wet or dry etching method by using only the gate portion as a mask while covering the gate portion with the SiO ₂ film 50 deposited by the above method. Next, as shown in FIG. 2C, metalorganic vapor phase epitaxy (MOVPE) or metalorganic molecular beam epitaxy (MOMBE) is used.
A p ⁺ -GaAs layer 30 is selectively grown on the removed portion. At this time, when MONBE is used, trimethylgallium (TMG) and metal arsenic (As) are used as raw materials, and if the growth temperature is 450 ° C., the carbon is automatically doped with 1 × 10 ²⁰ cm ⁻³ or more. P ⁺ -GaAs is obtained, and the selectivity is also improved. Finally, FIG. 2 (d)
As shown in FIG. 5, the SiO ₂ film 50 is removed, and WSi of the gate electrode 20 and Ti / Pt /
By depositing and patterning Au respectively, the field effect transistor of FIG. 1 is completed. Here, since the order and method of forming the gate electrode and the ohmic electrode are arbitrary, detailed description is omitted here.

FIG. 3 is a structural sectional view showing a second embodiment of the field effect transistor of the present invention. In the second embodiment, the channel layer 12 made of i-GaAs of the field-effect transistor of the first embodiment is
Doped p-In _0.3 Ga _0.7 As (15 n
m, 2 × 10 ¹⁸ cm ⁻³ ) as the channel layer 15. In addition, i-Al _0.8 Ga _0.2
The barrier layer 13 made of As (30 nm) is not doped at all. Others are the same as the configuration of FIG.

In the structure of the second embodiment, InGaAs forming the channel layer 15 has a larger lattice constant than GaAs forming the substrate 11, and strain stress is applied to the channel layer. As a result, the band structure of InGaAs changes, a heavy hole and a light hole are separated, and the use of the light hole improves the mobility of the hole. The field effect transistor having the structure according to the second embodiment exhibited gm = 80 ms / mm, and other characteristics were the same as those of the first embodiment.

[0016] The manufacturing method of a field effect transistor of the second embodiment, in the step of FIG. 2 described in the manufacturing method of the first embodiment (a), p-In _0.3 doped as a channel layer 15 Ga _0.7 As layer (15
nm, 2 × 10 ¹⁸ cm ⁻³ ), an i-Al _0.8 Ga _0.2 As layer (30 nm) is formed thereon as a barrier layer 13, and the barrier layer 13 is not doped with anything. If the subsequent steps are performed in the same manner as in the first embodiment, manufacturing is possible.

Here, the composition, thickness, dopant, and doping concentration of each layer in each embodiment described above are all arbitrary. The substrate, the buffer layer, the channel layer, and the barrier layer can be applied to other III-V compound semiconductors such as InP. Further, the electrode material on the source, drain and gate may be any suitable material. Similarly, the electrode formation method, the growth method, and the like are all arbitrary, and any method may be used.

[0018]

As described above, by using the field effect transistor and the method of manufacturing the same according to the present invention, the current driving capability, which is generated in the conventional p-channel field effect transistor, is small, and the gate leakage is easy. The problem that the source resistance is high can be solved, and the device characteristics can be improved. Therefore, by applying the present invention to a p-channel field-effect transistor included in a compound complementary circuit, a high-performance complementary element having a good balance between n and p can be obtained.

[Brief description of drawings]

FIG. 1 is a structural sectional view of a first embodiment of a field-effect transistor of the present invention.

FIG. 2 is a sectional view illustrating a method of manufacturing the field-effect transistor in FIG. 1 in the order of steps.

FIG. 3 is a structural sectional view of a second embodiment of the present invention.

[Explanation of symbols]

REFERENCE SIGNS LIST 10 semi-insulating GaAs substrate 11 i-GaAs buffer layer 12 high-purity i-GaAs channel layer 13 i-AlGaAs barrier layer 14 Be delta-doped layer 15 i-InGaAs channel layer 20 gate electrode 30 source / drain region 40 source / drain electrode 50 SiO ₂ film (mask)

Claims (6)

[Claims] 1. A field effect transistor using a III-V group compound semiconductor, wherein a barrier layer and a channel layer are formed in a laminated state under a gate electrode, and the barrier layer is formed from a semiconductor layer forming the channel layer. A field-effect transistor having a large forbidden band width, formed of a semiconductor layer to which impurities are not added, and source and drain regions formed of a high-concentration semiconductor layer. 2. The field effect transistor according to claim 1, wherein the barrier layer is doped with an impurity as a hole supply layer at or near one atomic plane. 3. The field effect transistor according to claim 1, wherein the channel layer is formed of a semiconductor layer to which impurities are added, which has a band gap smaller than that of the substrate semiconductor and has lattice distortion. 4. Field-effect transistor according to claim 1, configured as a p-channel field-effect transistor. 5. A semiconductor layer to be a buffer layer, a high-purity semiconductor layer to be a channel layer, on a semi-insulating semiconductor substrate,
A step of sequentially epitaxially growing a semiconductor layer having a forbidden band width larger than that of the channel layer and having an impurity added at or near one atomic plane to form a barrier layer; and forming a mask on the surface of the barrier layer to form the barrier layer. A step of selectively removing the layer and the channel layer leaving a gate portion, and forming a high-concentration impurity semiconductor layer on the removed portion by a selective growth method using a metal organic chemical vapor deposition method or a metal organic molecular beam epitaxial method A field effect, comprising: a step, a step of forming a gate electrode on the gate portion on the surface of the barrier layer, and a step of forming source and drain electrodes on the surface of the high-concentration impurity semiconductor layer, respectively. Manufacturing method of transistor. 6. A semiconductor layer which serves as a buffer layer on a semi-insulating semiconductor substrate, a semiconductor layer which becomes a channel layer having a band gap smaller than that of a substrate semiconductor by adding impurities, and a barrier layer. A step of sequentially epitaxially growing a semiconductor layer to be a barrier layer, a step of forming a mask on the surface of the barrier layer, and selectively removing the barrier layer and the channel layer leaving a gate portion, and an organic metal layer on the removed portion. A step of forming a high-concentration impurity semiconductor layer by a selective growth method using a vapor phase epitaxy method or a metal organic molecular beam epitaxial method; a step of forming a gate electrode at a gate portion on the surface of the barrier layer; And a step of forming respective source and drain electrodes on the surface of the semiconductor layer.