JPS6012773A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To obtain the titled element of high speed having a small contact resistance and the high mobility of a two-dimensional electron gas by a method wherein the first and second semiconductor layers of different band gaps are formed by lamination on a substrate, and the substrate temperature during the formation of a hetero junction is set less than the temperature for evaporation of a surface oxide film, when the element the channel of which is the boundary surface of the junction is manufactured by modulation doping to the first semiconductor layer. CONSTITUTION:A GaAs buffer layer 12, an AlGaAs buffer layer 13, an Si doped AlGaAs layer 14, the first semiconductor layer, with modulation doping selectively carried out, and a non-doped GaAs layer 15 the second semiconductor layer are formed by lamination on the GaAs substrate 11 by a molecular ray epitaxial method, resulting in the generation of the hetero junction 22 between the layers 14 and 15. Next, the source and drain regions 20 and 21 coming into the layer 14 are formed by a normal method. In this construction, the substrate temperature during the formation of the junction 22 is set less than the temperature for evaporation of the oxide film produced on the surface by 20-180 deg.C, which causes the increase of the mobility of the two-dimensional electron gas of the channel layer 19 in the layer 15.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a method for manufacturing a high-speed semiconductor device, particularly a semiconductor device in which a two-dimensional electron layer formed at a heterojunction interface serves as a channel.

(Description of Prior Art) High-speed integrated circuits mainly made of silicon are known. However, recently, instead of this conventional high-speed integrated circuit,
GaAs/GaAtAs formed by molecular beam epitaxy (MBE) or organometallic pyrolysis (yIDC)
Ultrahigh-speed integrated circuits using semiconductor elements that effectively utilize heterojunctions have been proposed.

Figures 1 and 2 show such an ultra-high-speed integrated circuit #11.
FIG. 2 is a cross-sectional view for explaining the structure and cavity manufacturing method of an example of a conventional semiconductor device.

Figure 1 shows the GaAs/AtGaAg heterojunction interface (
1 shows a conventional field effect transistor (hereinafter simply referred to as FET) in which a channel layer is a highly mobile two-dimensional electron gas at a heterointerface (hereinafter simply referred to as a heterointerface). This FET element has a high purity GaAs layer 2°AtGaA on a QaA3 substrate 1.
After sequentially growing the s-layer 3 by the molecular beam epitaxy method (hereinafter referred to as single MBE method), this AAGaA
sAtaAs layer electrode 4. A drain electrode 5 and a dirt electrode 6 are formed. Note that the regions surrounded by dotted lines 8 and 9 are regions that act as a source region and a drain region, respectively. The FET element configured in this way is a high-speed FET.
operates as

This is a high-purity G with a small band gap (forbidden band width).
aAS semiconductor layer and AtGa with a large band gap
In a superlattice structure in which As semiconductor layers are grown alternately or in a single heterojunction structure of amphibic conductor layers, modulated doping of impurities, that is, selective n-doping only in the AtGaAs layer.
When type doping is performed, due to the difference in electron affinity between GaAs and AtGaAs, electrons in the AtGaAs layer are transferred to the high-purity GaAs layer, creating a two-dimensional structure at the hetero interface as shown by the broken line 7 in Fig. The electron gas that spread to AA is
Since it is a GaAs layer 3, not only the properties of the Schottky junction of the gate 6 become unstable, but also the number of carriers in the AAGaAs layer 3 is large. A drawback is that the thickness of layer 3 must be precisely controlled. Furthermore, since an ohmic electrode is formed on the two-dimensional electron gas via the AtGaAs layer, there is also the drawback that contact resistance increases.

On the other hand, another conventional FET as shown in FIG. 2 in which the semiconductor layer forming the heterojunction of the FET element in FIG. 1 is replaced.
A device has been proposed, in which GaAs
On the substrate 11, -9, one GaAs buffer layer J 2 , one AAGaAs buffer layer 13 . n-type A
tGaAs layer 14. After continuously growing the high purity GaAs layer 15, a source electrode 16 is placed on the high purity GaAs layer 15.
, a drain electrode 17 and a dart electrode 18 are formed, respectively. Here, the regions surrounded by dotted lines 20 and 2 are the sources and drains formed by normal semiconductor manufacturing technology, and are the FE of the structure shown in FIG. 2.
Although the T element eliminates the drawbacks of the FET with the structure shown in FIG.
Applied Physics J Vol, 53
゜1(r, 2'-February 1982, pages 1030-1
Published on page 033 H, Morkoc, T, J-Dr.
As is clear from the description in the paper by ummond, R. Fi 5cher, etc. (particularly in FIG. 3), the mobility of the two-dimensional electron gas 19 is higher than that of F in FIG. 1 grown under the same conditions.
It is much lower than the mobility of the two-dimensional electron gas 7 of the ET element,
For example, the average mobility of the latter qk obtained with the substrate at 614 degrees during growth in the range of 600-680 degrees Celsius is approximately 90,000.
cm2/V+, whereas the former's mobility of 78°I (obtained in the range up to a substrate temperature of 680°C is 2,00
0 (about 7n2/Vs, and 8.500 Crn2/Vs at a maximum substrate temperature of 700°C. In particular, the former, that is, the mobility of the FET element with the structure shown in Figure 2, is MBE
It was found that the growth rate was significantly dependent on the substrate temperature during growth by the method.

Conventionally, when growing a GaAs or AtGaAs film on a GaAs substrate by the MBFJ method, the film was grown after confirming that the surface oxide film on the GaAs substrate had evaporated.
, Judaprawira, C. E., C. Wood, F. Eastman et al. and r Appl.
ied Physics Letter J Vol.

38, A6, March 15, 1981, pp. 427-4
Published on page 29 P, D, Kirchner, J, M
,WoodatA,J',L.

As is clear from the paper by Freeo'ut, G., D., and Pettit, it has been reported that the higher the substrate temperature, the better the growth of AtGaAs films.

However, in the case of the FET element with the structure shown in Fig. 2, even if the substrate temperature during growth is set as high as 700°C as described above, the mobility at 78° is 8,500t1n2/v.
However, the mobility is too low for this device to be applied to high-speed semiconductor devices.

(Objects of the Invention) The present invention was made in view of the above-mentioned drawbacks of conventional semiconductor devices, and its purpose is to eliminate the need for precise control of the thickness of the high-purity GaAs layer, to reduce contact resistance, and to provide two-dimensional electronic An object of the present invention is to provide a method for manufacturing a high-speed semiconductor device with high gas mobility.

(Structure of the Invention) In order to achieve the object 1, method-7 according to the present invention;
, 11. Organic means that the substrate temperature during the formation of a heterojunction is lower than the evaporation temperature of the oxide film of this substrate.

・This substrate temperature is approximately 20°C to 18°C based on the evaporation temperature.
It is preferable to set the temperature to a temperature range lower than 0°C. 1 Also, this substrate is a GaAs substrate, and the first semiconductor layer is Ai.
The second semiconductor layer can be an 8-layer GaA layer.

(Explanation of Examples) Embodiments of the present invention will be described below with reference to the drawings.

The present invention relates to the manufacture of a semiconductor element having a structure corresponding to the FET element having the structure shown in FIG.
Therefore, referring to FIG. 2 again, an FET element which is an embodiment of the present invention will be explained.

As shown in FIG. 2, using the MBE method, a layer of about 1000X thick G is sequentially placed on the GaAS substrate 11 from this substrate side.
aAs buffer layer 12. AAGaA of about 1 o, o OX
a no guffa layer 13. Approximately 500X as the second semiconductor layer
a silicon-doped AAGaAs layer 14. A non-doped GaAs layer 15 having a thickness of about 5,000 x is continuously grown as a second semiconductor layer to form a heterojunction 22 between the silicon-doped ALGaAs layer 14 and the non'+y old doped GaAs layer 15.

Using ordinary semiconductor device manufacturing technology, 71 cups4
; and a drain region (region surrounded by dotted lines 20. and 21), and a source electrode 16. on the non-doped GaAs layer 15. A drain electrode 17 and a right electrode 18 are formed. In the semiconductor device formed in this way, a channel layer is formed by the two-dimensional electron gas 19 existing at the interface of the heterojunction 22, and this channel layer is connected to the gate electrode 1.
The current flowing from the source electrode 16 to the drain electrode 17 can be modulated by controlling the applied voltage of 8.

By the way, as already explained, in order to make this semiconductor device a high-speed device, it is necessary to increase the mobility of the two-dimensional electron gas forming the channel layer 19. It was related to temperature. Therefore, the inventor of this application conducted an experiment to investigate the relationship between this mobility and the substrate temperature during growth, and found that there is a relationship as shown in FIG. In this Figure 3, the horizontal axis represents the substrate temperature (°C) at the time of formation of the hetero interface where a two-dimensional electron gas is formed, and the vertical axis represents the number of sheet carriers 5 X I O” cIn
This is a diagram plotting the hole mobility of the two-dimensional electron gas at -2 at the liquid nitrogen temperature (77°K).
-1 In this case, the GaAs surface oxide film evaporates when the substrate temperature is 6
! 14+, 'm degrees (To) are shown as a reference. The result of this experiment is 19. The substrate temperature is about To-20℃~'ro-i8
The Hall mobility at 77° in Koa at Q℃ is 40.000
It was found that an2/V-5ee-8'l.

The relationship shown in Figure 3 is obtained because the surface accumulation effect of silicon dopant (Si) during growth by the MBE method decreases as the substrate temperature decreases, and as the substrate temperature decreases, the effect increases accordingly. This is thought to be due to the fact that the mobility increases, and when the substrate temperature is further lowered, the flatness of the hetero interface deteriorates, causing the mobility to decrease.

Therefore, in the present invention, the silicon-doped AAGaAs layer 14 and the non-doped GaAs layer J are formed using the above-mentioned MBE method.
The substrate temperature when growing the hetero interface with GaAs
It is preferable to set the temperature lower than the evaporation temperature based on the temperature at which the surface oxide film evaporates, particularly in the range of about 20° C. to 180° C. below the evaporation temperature.

(Effects of the Invention) According to the present invention, the n-type AtGaAs layer 14, which is the first semiconductor layer with a large band gap, and the second semiconductor layer with a small band gap are formed on the upper side of the substrate from the substrate side of the MBE method. The substrate temperature when growing the heterointerface with the high-purity GaAs layer 15 is kQ, which is about T! compared to the evaporation temperature of the surface oxide film. , or 1°C to 180°C, it is possible to increase the mobility of the two-dimensional electron gas that reaches the hetero-interface of the semiconductor element formed by this cell p. A high-speed semiconductor layer +1 using the dimensional electron layer or electron gas layer 9 as a channel layer can be realized.

Further, in the structure of a semiconductor device, such as an FET device, manufactured according to the method according to the present invention, the date electrode 18 is made of a high purity Q
Since it is formed on the aAs layer 15, the voltage applied to the dart electrode is not reduced by ionized donor impurities, unlike when a dart electrode is formed on the surface of the n-type AAGaAs layer 14, and this applied voltage is directly applied to the two-dimensional The electrons are transmitted to the gas layer. Therefore, there is no need to precisely control the thickness of the high-purity GaAs layer 15, and high mutual conductance can be obtained.Also, since the FET element surface is the GaAs layer 15, the Schottky junction characteristics of the dart electrode 18 are stabilized. , source electrode 16. Drain electrode 170 It is easy to form an ohm electrode, and its resistance value can be easily reduced. Furthermore, GaAs is more stable than AtGaAs, and a highly reliable device can be realized.

(Description of Modifications) It is clear that the present invention is not limited to the embodiments described above and can be modified and modified in many ways! There is a field.

For example, although the invention has been described with reference to field effect transistors, it can also be applied to other high mobility devices and very high wave devices.

Further, unlike the above-described embodiments, the first semiconductor layer may be formed directly on the substrate, or the heterojunction may have a superlattice structure.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a conventional field effect transistor having a high mobility two-dimensional electron gas as a channel layer at the GaAs-AB:1aAg heterointerface. FIG. 2 is an explanation of the conventional method and the method of manufacturing a semiconductor device according to the present invention. FIG. 3 is a diagrammatic enlarged sectional view showing an embodiment of a field effect transistor similar to that in FIG. 1 but having a structure different from that in FIG. 1; FIG. 3 is a characteristic curve diagram showing the relationship between substrate temperature and yarn mobility during manufacture of the field effect transistor shown in the figure. 11... Substrate (e.g. GaAa substrate), 12... One buffer layer (e.g. GaAa), 13... One buffer layer (e.g. ALGaAs), 14... First semiconductor layer (e.g. n-type AtGaAs layer), 15 ...Second semiconductor layer (for example, high-purity GaAs layer), 16...Source electrode 4L J 7...Drain electrode, 18...Ri) IE
4tlii, '19... Two-dimensional electron gas (i, '+,
<% channel layer), 2o... Indicates the boundary of the source region I
Embroidery N, 21...A line indicating the boundary of the dirt area. Patent applicant: Director of the Agency of Industrial Science and Technology Kawa 1) Hirobe Figure 1

Claims (1)

[Claims] 1. A step of forming a first and second semiconductor layer having different bandgaps in this order from the substrate side using molecular beam epitaxy on the upper side of the substrate to form a heterojunction between both conductor layers. , selectively modulating doping the first semiconductor layer, and manufacturing a peninsula device having a two-dimensional electron layer at the heterojunction interface as a channel. A method for manufacturing a semiconductor device, characterized in that the substrate temperature is approximately 1 lower than the evaporation temperature of the surface oxide film of the substrate. -2. Manufacturing of a semiconductor device according to claim 1, characterized in that the substrate temperature is set in a temperature range approximately 20°C to 180°C lower than the surface oxide film evaporation temperature. Method. 3. Claim 1 or 2, characterized in that the substrate is a GaAs substrate, the first semiconductor layer is an AtGaAs layer, and the second semiconductor layer is a GaAs layer.
A method for manufacturing a semiconductor device as described in Section 1.