JPH028450B2 - - Google Patents

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Publication number
JPH028450B2
JPH028450B2 JP58119507A JP11950783A JPH028450B2 JP H028450 B2 JPH028450 B2 JP H028450B2 JP 58119507 A JP58119507 A JP 58119507A JP 11950783 A JP11950783 A JP 11950783A JP H028450 B2 JPH028450 B2 JP H028450B2
Authority
JP
Japan
Prior art keywords
layer
gaas
substrate
algaas
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58119507A
Other languages
Japanese (ja)
Other versions
JPS6012773A (en
Inventor
Seiji Nishi
Haruhisa Kinoshita
Masahiro Akyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP11950783A priority Critical patent/JPS6012773A/en
Publication of JPS6012773A publication Critical patent/JPS6012773A/en
Publication of JPH028450B2 publication Critical patent/JPH028450B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7781Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Description

【発明の詳細な説明】 (発明の技術分野) 本発明は高速半導体素子特にヘテロ接合境界面
に形成された二次元電子層をチヤネルとする半導
体素子の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a method for manufacturing a high-speed semiconductor device, particularly a semiconductor device in which a two-dimensional electron layer formed at a heterojunction interface is used as a channel.

(従来技術の説明) 従来より珪素を主体とした高速集積回路が知ら
れている。しかしながら最近この従来の高速集積
回路の代わり、分子線エピタキシー(MBE)法
或いは有機金属熱分解(MOCVD)法で形成し
たGaAs/GaAlAsのヘテロ接合を有効に利用し
た半導体素子を用いた超高速集積回路が提案され
ている。
(Description of Prior Art) High-speed integrated circuits mainly made of silicon have been known. However, recently, instead of this conventional high-speed integrated circuit, ultra-high-speed integrated circuits using semiconductor elements that effectively utilize GaAs/GaAlAs heterojunctions formed by molecular beam epitaxy (MBE) or metal organic pyrolysis (MOCVD) have been developed. is proposed.

第1図及び第2図はこのような超高速集積回路
に用いられる従来の半導体素子の一例の構造及び
その製造方法を説明するための断面図である。
FIGS. 1 and 2 are cross-sectional views for explaining the structure and manufacturing method of an example of a conventional semiconductor element used in such an ultra-high-speed integrated circuit.

第1図はGaAs/AlGaAsのヘテロ接合境界面
(以下単にヘテロ界面と称する)における高移動
二次元電子ガスをチヤネル層とする従来の電界効
果トランジスタ(以下単にFETと称する)を示
す。このFET素子はGaAs基板1上に高純度
GaAs層2、AlGaAs層3を分子線エピタキシー
法(以下単にMBEと称する)により順次に連続
成長させた後、このAlGaAs層3上にソース電極
4、ドレイン電極5及びゲート電極6を形成して
いる。尚、点線8及び9で囲まれた領域はソース
領域及びドレイン領域として夫々作用する領域で
ある。このように構成されたFET素子は高速
FETとして動作する。これは、バンドギヤツプ
(禁制帯幅)の小さい高純度GaAsの半導体層と、
バンドギヤツプの大きいAlGaAsの半導体層とを
交互に成長させた超格子構造又は両半導体層の単
一のヘテロ接合構造において、不純物の変調ドー
ピングすなわちAlGaAs層にのみ選択的にn型の
ドーピングを行うGaAsとAlGaAsとの電子親和
力の差によりAlGaAs層の電子が高純度GaAs層
に移り、ヘテロ界面に第1図に破線7で示すよう
に二次元的に広がつた電子ガスの層が出来、この
電子ガスはイオン化したドナー不純物と空間的に
離れているためクーロン散乱が少なく従つて特に
低温において電子移動度が高くなりよつて高速動
作すると説明されている。
FIG. 1 shows a conventional field effect transistor (hereinafter simply referred to as FET) in which a channel layer is a highly mobile two-dimensional electron gas at a GaAs/AlGaAs heterojunction interface (hereinafter simply referred to as heterointerface). This FET element is mounted on a GaAs substrate 1 with high purity.
After a GaAs layer 2 and an AlGaAs layer 3 are successively grown by molecular beam epitaxy (hereinafter simply referred to as MBE), a source electrode 4, a drain electrode 5, and a gate electrode 6 are formed on the AlGaAs layer 3. . Note that the regions surrounded by dotted lines 8 and 9 are regions that act as a source region and a drain region, respectively. The FET element configured in this way has high speed
Operates as a FET. This uses a high-purity GaAs semiconductor layer with a small bandgap (forbidden band width),
In a superlattice structure in which AlGaAs semiconductor layers with a large bandgap are grown alternately, or in a single heterojunction structure of both semiconductor layers, modulation doping of impurities, that is, n-type doping selectively only in the AlGaAs layer, is performed. Due to the difference in electron affinity with AlGaAs, electrons in the AlGaAs layer transfer to the high-purity GaAs layer, forming a layer of electron gas that spreads two-dimensionally at the hetero interface as shown by the broken line 7 in Figure 1. It is explained that since the electron beam is spatially separated from the ionized donor impurity, there is less Coulomb scattering, and therefore the electron mobility is high especially at low temperatures, resulting in high-speed operation.

しかしながら、この第1図のFET素子では表
面がAlGaAs層であるため、ゲート6のシヨツト
キ接合の特性が不安定となるばかりか、AlGaAs
層3のキヤリア数が多いため、ゲート電圧によつ
て二次電子ガスの濃度を変調するためには
AlGaAs層3の厚さを精密に制御しなくてはなら
ないという欠点があつた。さらに、AlGaAs層を
介して二次元電子ガスにオーム性電極を形成する
ため、接触抵抗が大きくなるという欠点もあつ
た。
However, since the surface of the FET element shown in Fig. 1 is an AlGaAs layer, not only the characteristics of the shot junction of the gate 6 become unstable, but also the AlGaAs
Since the number of carriers in layer 3 is large, in order to modulate the concentration of secondary electron gas by gate voltage,
There was a drawback that the thickness of the AlGaAs layer 3 had to be precisely controlled. Furthermore, since an ohmic electrode is formed on the two-dimensional electron gas via the AlGaAs layer, there is also the drawback of increased contact resistance.

他方、第1図のFET素子のヘテロ接合を形成
する半導体層を入れ替えた第2図に示すような従
来の他のFET素子が提案されており、この素子
においては、GaAs基板11上に、MBE法によ
り、GaAsバツフアー層12、AlGaAsバツフア
ー層13、n型AlGaAs層14、高純度GaAs層
15を連続的に成長させた後、高純度GaAs層1
5上にソース電極16、ドレイン電極17及びゲ
ート電極18を夫々形成した構造となつている。
ここにおいて、点線20及び21で囲まれた領域
は通常の半導体製造技術で形成されているソース
及びドレインとして作用する領域である。そして
このFET素子では高純度GaAs15とその下側n
型AlGaAs層14とのヘテロ界面に破線19で示
すようなチヤネル層すなわち二次元電子層(ガ
ス)が形成される。
On the other hand, another conventional FET device as shown in FIG. 2 has been proposed in which the semiconductor layer forming the heterojunction of the FET device in FIG. After successively growing the GaAs buffer layer 12, AlGaAs buffer layer 13, n-type AlGaAs layer 14, and high-purity GaAs layer 15 by the method, the high-purity GaAs layer 1
It has a structure in which a source electrode 16, a drain electrode 17, and a gate electrode 18 are formed on the 5, respectively.
Here, the regions surrounded by dotted lines 20 and 21 are regions that act as a source and a drain, which are formed using normal semiconductor manufacturing techniques. In this FET element, high-purity GaAs15 and its lower n
A channel layer, that is, a two-dimensional electron layer (gas) as shown by a broken line 19 is formed at the hetero interface with the type AlGaAs layer 14.

この第2図に示す構造のFET素子は第1図に
示した構造のFETの有する欠点を除去するが、
文献刊行物「Journal of Applied Physics」
Vol.53、No.2、1982年2月の第1030頁〜1033頁に
掲載されたH.Morkoc、T.J.Drummond及びR.
Fischer等による論文の記載(特に第3図)から
も明らかなように、二次元電子ガス19の移動度
は同一条件下で成長させた第1図のFET素子の
二次元電子ガス7の移動度より遥かに低く、例え
ば、成長時の基板温度600−680℃の範囲で得られ
た後者の78〓の平均移動度は90000cm2/Vsである
のに対し、前者の680℃の基板温度までの範囲で
得られた78〓の移動度は2000cm2/Vs程度で、最
大700℃ろ基板温度での8500cm2/Vsであり、特に
前者のすなわち第2図に示す構造のFET素子の
移動度はMBE法による成長時の基板温度に著し
く依存することが判つた。
The FET element with the structure shown in FIG. 2 eliminates the drawbacks of the FET with the structure shown in FIG.
Literature publication "Journal of Applied Physics"
H. Morkoc, TJ Drummond and R. Vol. 53, No. 2, February 1982, pp. 1030-1033.
As is clear from the description in the paper by Fischer et al. (particularly FIG. 3), the mobility of the two-dimensional electron gas 19 is the same as the mobility of the two-dimensional electron gas 7 of the FET device shown in FIG. 1 grown under the same conditions. For example, the average mobility of the latter 78〓 obtained at a substrate temperature in the range of 600-680℃ during growth is 90000 cm 2 /Vs, whereas the average mobility of the former 78〓 obtained up to a substrate temperature of 680℃ during growth is much lower. The mobility of 78〓 obtained in the range is about 2000cm 2 /Vs, and it is 8500cm 2 /Vs at the maximum filter substrate temperature of 700℃. In particular, the mobility of the former, that is, the FET element with the structure shown in Figure 2, is It was found that the growth rate significantly depends on the substrate temperature during growth using the MBE method.

従来、MBE法によつてGaAs基板上にGaAs或
いはAlGaAsの膜を成長させる場合、GaAs基板
上の表面酸化膜が蒸発するのを確認して膜の成長
を行つている。この表面酸化膜の蒸発温度は約
580℃程度であるので、この成長時の基板温度を
580℃以上に設定している。他方、文献刊行物
「Applied Physics Letter」Vol.38、No.9、1981
年5月1日の第708頁〜第710頁に掲載されたW.I.
Wang、S.Judaprawira、C.E.C.Wood及びL.F.
Eastman等による論文及び「Applied Physcs
Letter」Vol.38、No.6、1981年3月15日の第427
頁〜第429頁に掲載されたP.D.Kirchner、J.M.
Woodall、J.L.Freeout及びG.D.Pettit等による論
文からも明らかなように、AlGaAs膜の成長に関
しては基板温度が高いほど良い膜が出来ることが
報告されている。しかしながら、第2図に示す構
造のFET素子の場合には前述したように成長時
の基板温度を700℃と高く設定しても78〓での移
動度は8500cm2/Vs程度であり、この素子を高速
度半導体素子に適用するには移動度が低すぎる欠
点がある。
Conventionally, when growing a GaAs or AlGaAs film on a GaAs substrate by the MBE method, the film is grown after confirming that the surface oxide film on the GaAs substrate evaporates. The evaporation temperature of this surface oxide film is approximately
The temperature of the substrate during this growth is approximately 580℃.
The temperature is set to 580℃ or higher. On the other hand, the literature publication "Applied Physics Letter" Vol.38, No.9, 1981
WI published on pages 708 to 710 on May 1, 2018
Wang, S. Judaprawira, CECWood and LF.
The paper by Eastman et al. and “Applied Physcs
Letter” Vol. 38, No. 6, No. 427, March 15, 1981
PDKirchner, JM, published on pages ~429
As is clear from papers by Woodall, JL Freeout, GDPettit, etc., it has been reported that the higher the substrate temperature, the better the growth of AlGaAs films. However, in the case of the FET element with the structure shown in Fig. 2, even if the substrate temperature during growth is set as high as 700°C, the mobility at 78〓 is about 8500 cm 2 /Vs, and this element The drawback is that the mobility is too low to be applied to high-speed semiconductor devices.

(発明の目的) 本発明は上述した従来の半導体素子の欠点に鑑
みなれたもので、その目的は高純度GaAs層の厚
さの精密な制御を必要とせず、接触抵抗が小さく
しかも二次元電子ガスの移動度が高い高速半導体
素子の製造方法を提供することにある。
(Purpose of the Invention) The present invention was developed in view of the above-mentioned drawbacks of conventional semiconductor devices.The purpose of the present invention is to eliminate the need for precise control of the thickness of the high-purity GaAs layer, provide low contact resistance, and provide two-dimensional electronic An object of the present invention is to provide a method for manufacturing a high-speed semiconductor device with high gas mobility.

(発明の構成) この目的の達成を図るため、本発明による方法
ではヘテロ接合形成時の基板温度を、この基板の
表面酸化膜の蒸発温度より低い温度とすることを
特徴とする。
(Structure of the Invention) In order to achieve this object, the method according to the present invention is characterized in that the substrate temperature during the formation of the heterojunction is set to a temperature lower than the evaporation temperature of the surface oxide film of the substrate.

この基板温度は蒸発温度を基準として約20℃〜
180℃低い温度範囲に設定するのが好適である。
This substrate temperature is approximately 20℃~ based on the evaporation temperature.
It is preferable to set the temperature range to 180°C lower.

又、この基板をGaAs基板とし、第一半導体層
をAlGaAs層とし、第二半導体層をGaAs層とす
ることが出来る。
Further, this substrate can be a GaAs substrate, the first semiconductor layer can be an AlGaAs layer, and the second semiconductor layer can be a GaAs layer.

(実施例の説明) 以下、図面により本発明の実施例につき説明す
る。
(Description of Examples) Examples of the present invention will be described below with reference to the drawings.

本発明は上述した第2図に示す構造のFET素
子に対応する構造を有する半導体素子の製造に係
るものであり、従つてこの第2図を再び用いて本
発明の一実施例であるFET素子につき説明する。
The present invention relates to the manufacture of a semiconductor element having a structure corresponding to the FET element having the structure shown in FIG. I will explain about it.

第2図に示すように、MBE法を用いて、
GaAs基板11上にこの基板側から順次に約1000
Åの厚さのGaAsバツフア層12、約1000Åの
AlGaAsバツフア層13、第一半導体層としての
約500Åの厚さの珪素ドープAlGaAs層14、第
二半導体層としての約5000Åの厚さのノンドープ
GaAs層15を連続させ、珪素ドープAlGaAs層
14とノンドープGaAs層15とのヘテロ接合2
2を形成する。そして通常の半導体装置の製造技
術を用いて、ソース及びドレイン用の領域(点線
20,21で囲まれた領域)と、ノンドープ
GaAs層15上のソース電極16、ドレイン電極
17及びゲート電極18とを形成する。このよう
に形成された半導体素子では、ヘテロ接合22の
境界面に存在する二次元電子ガス19によりチヤ
ネル層が形成され、このチヤネル層をゲート電極
18の印加電圧により制御してソース電極16か
らドレイン電極17に流れる電流を変調すること
が出来る。
As shown in Figure 2, using the MBE method,
Approximately 1000 cells are placed on the GaAs substrate 11 sequentially from this substrate side.
GaAs buffer layer 12 with a thickness of about 1000 Å
AlGaAs buffer layer 13, a silicon-doped AlGaAs layer 14 with a thickness of about 500 Å as a first semiconductor layer, and a non-doped AlGaAs layer 14 with a thickness of about 5000 Å as a second semiconductor layer.
A heterojunction 2 between a silicon-doped AlGaAs layer 14 and a non-doped GaAs layer 15 by making the GaAs layer 15 continuous
form 2. Then, using normal semiconductor device manufacturing technology, the source and drain regions (areas surrounded by dotted lines 20 and 21) and non-doped
A source electrode 16, a drain electrode 17, and a gate electrode 18 are formed on the GaAs layer 15. In the semiconductor device formed in this way, a channel layer is formed by the two-dimensional electron gas 19 existing at the interface of the heterojunction 22, and this channel layer is controlled by the voltage applied to the gate electrode 18 to form a channel layer from the source electrode 16 to the drain. The current flowing through the electrode 17 can be modulated.

ところで、既に説明した通り、この半導体素子
を高速素子とするためにはチヤネル層19を形成
する二次形電子ガスの移動度を高くすることが必
要であり、この移動度は成長時の基板温度と関係
するものであつた。そこでこの出願の発明者はこ
の移動度と成長時の基板温度との関係を実験によ
り調べたところ、第3図に示すような関係がある
ことが判つた。この第3図は横軸を二次元電子ガ
スが形成されるヘテロ界面形成時の基板温度
(℃)とし、縦軸をシートキヤリア数5×10″cm-2
の二次元電子ガスの液体窒素温度(77〓)におけ
るホール移動度としてプロツトして示した図であ
る。この場合、基板温度をGaAs表面酸化膜が蒸
発する温度(T0)を基準として示す。この実験
結果より、基板温度を約T0−20℃〜T0−180℃の
範囲で77〓のホール移動度が40000cm2/V・sec以
上となることが判つた。
By the way, as already explained, in order to make this semiconductor device a high-speed device, it is necessary to increase the mobility of the secondary electron gas forming the channel layer 19, and this mobility depends on the substrate temperature during growth. It was related to. Therefore, the inventor of this application conducted an experiment to investigate the relationship between this mobility and the substrate temperature during growth, and found that there is a relationship as shown in FIG. 3. In this Figure 3, the horizontal axis is the substrate temperature (°C) at the time of the formation of the hetero interface where a two-dimensional electron gas is formed, and the vertical axis is the number of sheet carriers 5×10″cm -2
This is a diagram plotting the hole mobility of the two-dimensional electron gas at the liquid nitrogen temperature (77〓). In this case, the substrate temperature is expressed based on the temperature (T 0 ) at which the GaAs surface oxide film evaporates. From the results of this experiment, it was found that the hole mobility of 77〓 becomes 40000 cm 2 /V·sec or more when the substrate temperature is in the range of about T 0 -20°C to T 0 -180°C.

この第3図に示すような関係が得られるのは、
MBE法による成長中の珪素ドーパント(Si)の
表面蓄積効果が基板温度の低下に従つて少なくな
り、この基板温度を下げるとこれに応じて移動度
が上がり、又基板温度をさらに下げるとヘテロ界
面の平坦さが悪くなり移動度が下がることに起因
すると思われる。
The relationship shown in Figure 3 is obtained because
The surface accumulation effect of silicon dopant (Si) during growth by the MBE method decreases as the substrate temperature decreases, and lowering the substrate temperature increases the mobility accordingly, and further lowering the substrate temperature increases the hetero-interface. This is thought to be due to the fact that the flatness of the surface becomes worse and the mobility decreases.

そこで本発明においては、上述したMBE法を
用いて珪素ドープAlGaAs層14とノンドープ
GaAs層15とのヘテロ界面を成長させる時の基
板温度をGaAsの表面酸化膜が蒸発する温度を基
準としてこの蒸発温度よりも低い温度、特にこの
蒸発温度を基準として約20℃〜180℃下の温度範
囲に設定するのが好適である。
Therefore, in the present invention, the silicon-doped AlGaAs layer 14 and the non-doped AlGaAs layer 14 are formed using the above-mentioned MBE method.
The substrate temperature when growing the heterointerface with the GaAs layer 15 is set at a temperature lower than the evaporation temperature, especially about 20°C to 180°C below the evaporation temperature, based on the temperature at which the surface oxide film of GaAs evaporates. It is preferable to set the temperature within a range.

(発明の効果) このように本発明によれば基板の上側にMBE
法でこの基板側からバンドギヤツプの大きい第一
半導体層であるn型AlGaAs層14とバンドギヤ
ツプの小さい第二半導体層である高純度GaAs層
15とのヘテロ界面を成長させる時の基板温度を
上述したように表面酸化物である膜の蒸発温度よ
り約20℃〜180℃低い温度範囲に設定するので、
このようにして形成された半導体素子のヘテロ界
面における二次元電子ガスの移動度を高くするこ
とが出来、従つてこの二次元電子層すなわち電子
ガス19をチヤネル層として使用する高速度の半
導体素子を実現することが出来る。
(Effects of the Invention) According to the present invention, the MBE is placed on the upper side of the substrate.
As described above, the substrate temperature is set when growing the heterointerface between the n-type AlGaAs layer 14, which is the first semiconductor layer with a large band gap, and the high-purity GaAs layer 15, which is the second semiconductor layer with a small band gap, from the substrate side using the method. The temperature is set at a temperature range of approximately 20℃ to 180℃ lower than the evaporation temperature of the surface oxide film.
The mobility of the two-dimensional electron gas at the hetero-interface of the semiconductor device thus formed can be increased, and therefore a high-speed semiconductor device using this two-dimensional electron layer, that is, the electron gas 19, as a channel layer can be realized. It can be realized.

又、本発明による方法に従つて製造された半導
体素子例えばFET素子の構造では、ゲート電極
18を高純度GaAs層15上に形成するので、n
型のAlGaAs層14の表面にゲート電極を形成し
たようにゲート電極に加えた電圧がイオン化した
ドナー不純物によつて減少することはなく、この
印加電圧が直接二次元電子ガス層に伝えられる。
このため高純度GaAs層15の厚さを精密に制御
する必要はなく、高い相互コンダクタンスが得ら
れる。又FET素子表面がGaAs層15であるため
ゲート電極18のシヨツトキ接合の特性が安定に
なると共に、ソース電極16、ドレイン電極17
のオーム性電極を形成しやすく、その抵抗値も小
さくしやすい。さらに、GaAsはAlGaAsに対し
て安定であり、信頼性の高い素子を実現出来る。
Furthermore, in the structure of a semiconductor device, such as an FET device, manufactured according to the method according to the present invention, since the gate electrode 18 is formed on the high-purity GaAs layer 15, n.
Unlike when the gate electrode is formed on the surface of the AlGaAs layer 14 of the mold, the voltage applied to the gate electrode is not reduced by the ionized donor impurities, and this applied voltage is directly transmitted to the two-dimensional electron gas layer.
Therefore, there is no need to precisely control the thickness of the high-purity GaAs layer 15, and high mutual conductance can be obtained. In addition, since the surface of the FET element is the GaAs layer 15, the characteristics of the shot junction of the gate electrode 18 are stabilized, and the characteristics of the shot junction of the gate electrode 18 are stabilized.
It is easy to form an ohmic electrode, and its resistance value can be easily reduced. Furthermore, GaAs is more stable than AlGaAs, making it possible to realize highly reliable devices.

(変形例の説明) 本発明は上述した実施例にのみ限定されるもの
ではなく多くの変更又は変形を行い得ること明ら
かである。例えば本発明を電界効果トランザスタ
につき説明したが、他の高移動度デバイスや超高
周波デバイスにも適用出来る。
(Description of Modifications) It is clear that the invention is not limited only to the embodiments described above, but can be modified and modified in many ways. For example, although the present invention has been described with respect to field effect transistors, it can also be applied to other high mobility devices and very high frequency devices.

又、上述した実施例とは異なり、基板上に直接
第一半導体層を形成した構造としてもよいし、或
いは又ヘテロ接合を超格子構造としてもよい。
Further, unlike the above-described embodiments, the first semiconductor layer may be formed directly on the substrate, or the heterojunction may have a superlattice structure.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のGaAs−AlGaAsヘテロ界面に
おける高移動度二次元電子ガスをチヤネル層とす
る電界効果トランジスタを示す断面図、第2図は
従来及び本発明による半導体素子の製造方法の説
明に供する第1図と同様な電界効果トランジスタ
ではあるが第1図とは構造が異なる電界効果トラ
ンジスタの一実施例を示す図式的拡大断面図、第
3図は本発明の説明に供する第2図に示した電界
効果トランジスタの製造時における基板温度とホ
ール移動度との開係を示す特性曲線図である。 11……基板(例えばGaAs基板)、12……
バツフアー層(例えばGaAs)、13……バツフ
アー層(例えばAlGaAs)、14……第一半導体
層(例えばn型AlGaAs層)、15……第二半導
体層(例えば高純度GaAs層)、16……ソース
電極、17……ドレイン電極、18……ゲート電
極、19……二次元電子ガス(又はチヤネル層)、
20……ソース領域の境界を示す線、21……ゲ
ート領域の境界を示す線。
FIG. 1 is a cross-sectional view showing a conventional field effect transistor in which a high-mobility two-dimensional electron gas at a GaAs-AlGaAs heterointerface is used as a channel layer, and FIG. 2 is used to explain methods for manufacturing semiconductor devices according to the conventional method and the present invention. A schematic enlarged sectional view showing an embodiment of a field effect transistor similar to that shown in FIG. 1 but having a different structure from that shown in FIG. 1; FIG. 3 is shown in FIG. FIG. 3 is a characteristic curve diagram showing the relationship between substrate temperature and hole mobility during manufacturing of a field effect transistor. 11...Substrate (e.g. GaAs substrate), 12...
Buffer layer (e.g. GaAs), 13... Buffer layer (e.g. AlGaAs), 14... First semiconductor layer (e.g. n-type AlGaAs layer), 15... Second semiconductor layer (e.g. high purity GaAs layer), 16... Source electrode, 17...Drain electrode, 18...Gate electrode, 19...Two-dimensional electron gas (or channel layer),
20... A line indicating the boundary of the source region, 21... A line indicating the boundary of the gate region.

Claims (1)

【特許請求の範囲】[Claims] 1 GaAs基板上に分子線エピタキシー法で、
AlGaAsからなる第一半導体層及びGaAsからな
る第二半導体層をこの順序で成長し、両半導体層
間にヘテロ接合を形成する工程と、前記第一半導
体層に変調ドーピングを選択的に行なう工程とを
用い、ヘテロ接合境界面の二次元電子層をチヤネ
ルとする半導体素子を製造するに当り、前記ヘテ
ロ接合形成時の基板温度を該基板の表面酸化膜の
蒸発温度より20℃〜180℃低い温度とすることを
特徴とする半導体素子の製造方法。
1 Using molecular beam epitaxy on a GaAs substrate,
A step of growing a first semiconductor layer made of AlGaAs and a second semiconductor layer made of GaAs in this order to form a heterojunction between the two semiconductor layers, and a step of selectively performing modulation doping on the first semiconductor layer. In manufacturing a semiconductor device using a two-dimensional electron layer at a heterojunction interface as a channel, the substrate temperature at the time of forming the heterojunction is set to a temperature 20 to 180 degrees Celsius lower than the evaporation temperature of the surface oxide film of the substrate. A method for manufacturing a semiconductor device, characterized in that:
JP11950783A 1983-07-02 1983-07-02 Manufacture of semiconductor element Granted JPS6012773A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11950783A JPS6012773A (en) 1983-07-02 1983-07-02 Manufacture of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11950783A JPS6012773A (en) 1983-07-02 1983-07-02 Manufacture of semiconductor element

Publications (2)

Publication Number Publication Date
JPS6012773A JPS6012773A (en) 1985-01-23
JPH028450B2 true JPH028450B2 (en) 1990-02-23

Family

ID=14762969

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11950783A Granted JPS6012773A (en) 1983-07-02 1983-07-02 Manufacture of semiconductor element

Country Status (1)

Country Link
JP (1) JPS6012773A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2921835B2 (en) * 1988-02-04 1999-07-19 松下電器産業株式会社 Heterojunction field effect transistor
JP2650411B2 (en) * 1989-04-17 1997-09-03 日立電線株式会社 Field effect transistor
JPH081955B2 (en) * 1991-08-21 1996-01-10 ヒューズ・エアクラフト・カンパニー Method of manufacturing an inverted modulation-doped heterostructure
JP3301357B2 (en) * 1997-08-26 2002-07-15 株式会社村田製作所 Parallel plate type plasma CVD equipment

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5752126A (en) * 1980-09-16 1982-03-27 Oki Electric Ind Co Ltd Compound semiconductor device
JPS5913376A (en) * 1982-07-13 1984-01-24 Nippon Telegr & Teleph Corp <Ntt> Semiconductor thin film having hetero junction
JPS59106158A (en) * 1982-12-10 1984-06-19 Fujitsu Ltd Manufacture of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5752126A (en) * 1980-09-16 1982-03-27 Oki Electric Ind Co Ltd Compound semiconductor device
JPS5913376A (en) * 1982-07-13 1984-01-24 Nippon Telegr & Teleph Corp <Ntt> Semiconductor thin film having hetero junction
JPS59106158A (en) * 1982-12-10 1984-06-19 Fujitsu Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS6012773A (en) 1985-01-23

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