JP2703885B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device using two-dimensional conduction at a heterojunction interface between semiconductors having different electron affinities or semiconductors having different sums of an electron affinity and an energy gap. (Prior Art) A field-effect transistor (FET) using two-dimensional electrons or holes accumulated at a heterojunction interface of a semiconductor having a different electron affinity or a semiconductor having an energy gap different from the electron affinity has a function of the accumulated electrons or positive electrons. In recent years, pores have attracted increasing attention due to their high mobility, especially at low temperatures. For example, gallium arsenide (hereinafter referred to as GaA
s) and a semiconductor layer having a lower electron affinity than the n-type doped GaAs layer, for example, aluminum gallium arsenide (hereinafter, Al).
2 accumulated on the GaAs layer side of the heterojunction interface with the GaAs layer
It operates by controlling the two-dimensional electron channel with the voltage of the gate electron. In such a transistor, the surface charge density of the two-dimensional electrons accumulated at the interface is determined by the discontinuity of the energy band of GaAs and GaAlAs and the doping amount of the n-type impurity in the GaAlAs layer. As the amount increases, the surface charge density of electrons increases, which leads to a reduction in resistance between the gate and the source in the operation of the transistor. Therefore, aluminum (hereinafter Al) of the GaAlAs layer
Increasing the composition increases the discontinuity of the energy band. However, when the Al composition is around 0.4, the energy band of AlGaAs becomes indirect transition type rather than direct transition type, and the discontinuity amount of the energy band does not increase. Moreover, the aluminum composition is 0.
In the vicinity of 3, even if it is a direct transition, an uncontrollable impurity level is formed under the influence of the indirect transition, causing hysteresis in the current-voltage characteristics of the transistor. Further, a GaAlAs layer having a large Al composition has a high possibility of taking in oxygen during crystal growth, and may deteriorate electrical characteristics such as an increase in contact resistance. Therefore, in the case of a field effect transistor (FET) using two-dimensional electrons accumulated at the heterojunction interface between AlGaAs and GaAs, the Al composition of AlGaAs is about 0.3. Similarly, when two-dimensional holes are used, the Al composition of AlGaAs is about 0.5. (Problems to be Solved by the Invention) When two-dimensional electrons or holes are accumulated at a semiconductor heterojunction interface, an electron or hole trapping center such as an interface state exists near the junction interface. should not. Therefore, when two kinds of semiconductors having different electron affinities or two kinds of semiconductors having different sums of the electron affinity and the energy gap are used, the lattice constants of the two are almost the same in order to suppress the generation of lattice dislocation which causes a trapping center. Choose Therefore, for example, in the case of group III and group V compound semiconductor crystals, two types of semiconductors that are lattice-matched with the substrate, especially GaAs and indium substrates, and have different electron affinities or two types of semiconductors having different electron affinities and energy gaps are used. The difference in the electron affinity or the difference in the sum of the electron affinity and the energy gap is naturally restricted. An object of the present invention is to provide a semiconductor device having two types of semiconductors having different electron affinities or different electron affinities and the sum of the energy gaps, which have a larger difference in the electron affinities without being restricted by lattice matching, or a difference in the sum of the electron affinities and the energy gap. It is therefore possible to provide a semiconductor device such as an FET having a small source resistance, for example, by making it possible to increase the interface electron concentration accumulated at the heterojunction interface. (Means for Solving the Problems) According to the present invention, a high-purity or p-type second semiconductor layer having a higher electron affinity than the first semiconductor is provided on the first semiconductor,
Further, a third semiconductor layer having a smaller electron affinity was provided on the second semiconductor layer, and an electron channel was formed on the interface between the second and third semiconductor layers on the side of the second semiconductor layer. In the semiconductor device, the second semiconductor layer is indium gallium arsenide, the first semiconductor layer is gallium arsenide or gallium aluminum arsenide, the third semiconductor layer is gallium aluminum arsenide, and the second and third semiconductor layers are gallium aluminum arsenide. The semiconductor layer and the first and second semiconductor layers are not lattice-matched, the thickness of the second semiconductor layer is less than the minimum thickness at which dislocations occur, and the conduction band of the second semiconductor layer and the third semiconductor layer are different. The discontinuity of the conduction band is characterized by being larger than the discontinuity of the conduction band formed by the gallium aluminum arsenide layer having a gallium arsenide and aluminum composition of 0.3. According to the present invention, a high-purity or n-type second semiconductor layer having a smaller sum of the electron affinity and the energy gap is provided on the first semiconductor, and the electron affinity and the energy are further reduced on the second semiconductor layer. In a semiconductor device in which a third semiconductor layer having a large sum of gaps is provided and a hole channel is formed on an interface between the second and third semiconductor layers on the side of the second semiconductor layer, the second semiconductor layer Is indium gallium arsenide, the first semiconductor layer is gallium arsenide or gallium aluminum arsenide, the third semiconductor layer is gallium aluminum arsenide, and the second and third semiconductor layers and the first and second The semiconductor layer is not lattice-matched and the thickness of the second semiconductor layer is less than the minimum thickness at which dislocations occur, and the valence band of the second semiconductor layer and the valence band of the third semiconductor layer are different. Continuous quantity is characterized by greater than discontinuity of the valence band of gallium arsenide and aluminum composition is formed from gallium aluminum arsenide layer of 0.5. (Operation) A second semiconductor layer having a higher electron affinity is provided on the first semiconductor, and a third semiconductor layer having a lower electron affinity is provided on the second semiconductor layer. Accordingly, electrons form an electron channel on the second semiconductor side at the interface between the second and third or the first and second semiconductor layers. At this time, the second semiconductor layer is lattice-matched as in the related art. Absent.
However, the thickness of the second semiconductor layer is not more than a certain thickness, and no dislocation occurs due to lattice mismatch. Therefore, two types of semiconductors can be selected such that there is no restriction on the amount of discontinuity in the conduction band due to lattice matching as in the related art, and the amount of discontinuity is larger. In addition, no dislocation is generated, and no electron capture center such as an interface level is generated. Moreover,
In the case of two-dimensional electrons, the electron density increases only when the difference in electron affinity is at least the conventional GaAlAs / GaAs heterojunction system and the aluminum composition is 0.25 or more, and the Al composition ratio is controlled by controlling the In composition. Can be lowered. Therefore, the AlGaAs layer can be made to be a direct transition type conventionally, the possibility of taking in oxygen during crystal growth is reduced, the contact resistance is improved, and the sheet resistance and the contact resistance are improved by improving the electron concentration. Are reduced, and the characteristics of the transistor are improved. (Example 1) In the following, GaAs, indium gallium arsenide having an indium composition of 0.3 (hereinafter referred to as In _0.3 Ga _0.7 As) and an Al composition of 0.
25 or more, for example, 0.3 aluminum gallium arsenide (hereinafter, Al _0.3
The present invention will be described using an example of a semiconductor device composed of Ga _0.7 As). FIG. 1 shows high purity as the first semiconductor layer.
An element end face epitaxially grown on a semi-conductive GaAs substrate 4 using a GaAs layer 1, a high-purity In _0.3 Ga _0.7 As layer 2 as a second semiconductor layer, and an n-type Ga _0.7 Al _0.3 As layer 3 as a third semiconductor layer. FIG. In the figure, 5 is a source electrode, 6 is a gate electrode, and 7 is a drain electrode. The epitaxial method is a molecular beam epitaxial method in which high-purity gallium arsenide layer 1 is approximately 8000 angstroms, In _0.3 Ga _0.7 As layer 2 is 80 angstroms, and silicon is doped with 2 × 10 ¹⁸ cm ^-3 Al.
_{A 0.3} Ga _0.7 As layer is grown by 400 angstroms, and a gate electrode 6 is formed from aluminum, and ohmic electrodes 5 and 7 are formed from gold, germanium and nickel. FIG. 2 is an energy band diagram in a thermal equilibrium state in a depth direction below a gate in the case of a normally-on type transistor, for example. Here, E _C , E _V , and E _F are the energy level at the bottom of the conduction band, the energy level at the top of the valence band, and the Fermi level, respectively, and ΔE _C1 is In _0.3 Ga.
Difference of electron affinity at _0.7 As and Ga _0.7 Al _0.3 As interface, ΔE _C2
The difference between the electron affinity of GaAs and In _0.3 Ga _0.7 As surfactants, phi _B is the gate Schottky barrier height of the barrier, 9 is the charge of an electron, has a donor ionized GaAlAs layer schematically represents . In such a state, as a result of observation with a transmission electron microscope, no crystal transition higher than that of the GaAs substrate was observed in the In _0.3 Ga _0.7 As layer. On the other hand, the thickness of In _0.3 Ga _0.7 As is 100
At Å, crystal dislocations larger than the substrate were observed, and it was found that 100 Å was the minimum thickness for dislocation generation. In such a structure, the Ga _0.7 Al _0.3 As layer 3 is entirely depleted, and two-dimensional electrons accumulate at the boundary between the Ga _0.7 Al _0.3 As layer 3 and the In _0.3 Ga _0.7 As layer 2.
Higher becomes an In _0.3 Ga as _C1 larger _0.7 As and Ga _0.7 Al _0.3 As and discontinuity is 2 valence thirds of the difference in band gap between an In _0.3 Ga _0.7 As 1.1 eV further GaAlAs layer band gap of the Assuming a discontinuity in the electronic band, it is estimated to be about 0.45 eV. As a result, compared to the discontinuity of 0.25 eV when the conventional GaAs and Ga _0.7 Al _0.3 As were used, the Δ
E _C1 is considered to be about 80% larger. Further, in the structure shown in FIG. 2, the surface charge density of the two-dimensional electron measured by the Shubonnikov-de Haas effect was 1.5 × 10 ¹² cm ⁻² . On the other hand, the conventional structure, that is, In _0.3 Ga _0.7 As
In the case of the structure excluding the layer 2, the measured surface charge density of two-dimensional electrons was 1.1 × 10 ¹² cm ^−2, which is about 70% of the present invention. Further, in the FET shown in FIG. 1, the source resistance was 0.4 ohm per millimeter. On the other hand, in the FET manufactured by the same process with the structure excluding the In _0.3 Ga _0.7 As layer 2, the source resistance was 0.6 ohm per millimeter. Also In _0.3 Ga
_The source resistance did not decrease when the _0.7 As layer was 100 Å or more. In this embodiment, the indium composition is 0.
Although it was 3, for example, in the case of indium compositions 0.15 and 0.23, the sheet resistance obtained the same value as in the case of 0.3,
The indium composition of the present invention is not limited to 0.3. (Embodiment 2) A description will be given using an embodiment of a semiconductor device made of GaAs, InGaAs, and AlGaAs having a structure similar to that of Embodiment 1. This embodiment is different from the first embodiment in that Al is used as the third semiconductor layer.
Ga _0.8 Al _0.2 As having a composition of 0.2 is used. As shown in FIG. 1, a high-purity GaAs layer as a first semiconductor layer, a high-purity In _0.3 Ga _0.7 As2 and a Ga _0.8 Al _0.2 As as a second semiconductor layer.
And epitaxially grown on a semi-insulating GaAs substrate 4. In such a structure, the band gap of In _0.3 Ga _0.7 As is assumed to be 1.1 eV, and assuming that two thirds of the band gap difference from the Ga _0.8 Al _0.2 As layer is discontinuous in the valence band, about 0.36 eV It is estimated to be. Therefore, as in the case of the first embodiment, when the conventional GaAs and Ga _0.7 Al _0.3 As are used, the discontinuity amount is 0.1 mm.
ΔE _C1 is larger than that of 25 eV. The surface charge density of two-dimensional electrons was found to be 1.4 × 10 ¹² cm ^−3, which was larger than the surface charge density of two-dimensional electrons in the conventional structure. In the FET, a reduction in the source resistance was observed as compared with Example 1. In the above description, the case where the carrier is an electron has been described. The present invention can be applied to the case where the carrier is a hole. In this case, since holes are accumulated on the valence band side, a second semiconductor in FIG. 1 having a smaller sum of electron affinity and energy gap than the first semiconductor is used, and the second semiconductor in FIG. As the third semiconductor, a semiconductor whose sum of electron affinity and energy gap is larger than that of the second semiconductor is used, and the third semiconductor layer is doped with an acceptor at a high density. Here, the energy band diagram in the thermal equilibrium state is as shown in FIG. Here, θ is a schematic representation of an ionized acceptor, and 2 ′ is a two-dimensional hole layer. In this embodiment, a semi-insulating GaAs substrate is used, a high-purity GaAs layer as a first semiconductor layer, and a second semiconductor layer as a second semiconductor layer.
Al _0.5 Ga _0.5 As is used for the In _0.3 Ga _0.7 As layer and the third semiconductor layer. In the present embodiment, the indium composition was 0.3, but the indium composition of the present invention is not limited to 0.3. (Effects of the Invention) As is apparent from the above description, the present invention uses a semiconductor with reduced dislocation and lattice matching by reducing the thickness of the semiconductor layer despite using semiconductors having different lattice constants. A heterojunction with a larger difference in electron affinity or a difference in the sum of the electron affinity and the energy gap can be formed as compared with the case, and there is an advantage that the source resistance can be reduced in the FET using this, The effect that the performance of the semiconductor element can be improved is remarkable as compared with the case of FIG.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing the structure of a semiconductor device according to the present invention;
2 and 3 are energy band diagrams. DESCRIPTION OF SYMBOLS 1 ... High-purity gallium arsenide, 2 ... High-purity indium gallium arsenide, 3 ... N-type gallium aluminum arsenide, 4 ... Semi-leading gallium arsenide substrate, 5 ... Source electrode, 6 ... Gate electrode, 7 …… Drain electrode, 2 ′… 2D hole layer.

Claims (1)

(57) [Claims] A high-purity or p-type second semiconductor layer having a higher electron affinity is provided on the first semiconductor, and a third semiconductor layer having a lower electron affinity is provided on the second semiconductor layer. A semiconductor device having an electron channel formed on the interface between the second and third semiconductor layers on the second semiconductor layer side, wherein the second semiconductor layer is indium gallium arsenide, and the first semiconductor layer is gallium. Arsenic or gallium aluminum arsenide, the third semiconductor layer is gallium aluminum arsenide, and the second and third semiconductor layers and the first and second semiconductor layers are not lattice-matched and the second semiconductor layer The thickness is less than the minimum thickness at which dislocations occur, and the discontinuity between the conduction band of the second semiconductor layer and the conduction band of the third semiconductor layer is gallium arsenide and gallium aluminum having an aluminum composition of 0.3. Wherein a greater than discontinuity of the conduction band formed from um arsenide layer. 2. A high-purity or n-type second semiconductor layer having a smaller sum of the electron affinity and the energy gap is provided on the first semiconductor, and further, a sum of the electron affinity and the energy gap is further formed on the second semiconductor layer. In a semiconductor device in which a large third semiconductor layer is provided and a hole channel is formed on a side of the second semiconductor layer at an interface between the second and third semiconductor layers, the second semiconductor layer is formed of indium gallium arsenide. Wherein the first semiconductor layer is gallium arsenide or gallium aluminum arsenide, the third semiconductor layer is gallium aluminum arsenide, and the second and third semiconductor layers and the first and second semiconductor layers are grids. Mismatching and making the thickness of the second semiconductor layer less than the minimum thickness at which dislocations occur,
The discontinuity between the valence band of the second semiconductor layer and the valence band of the third semiconductor layer is smaller than the discontinuity of the valence band formed by the gallium arsenide and the gallium aluminum arsenide layer whose aluminum composition is 0.5. A semiconductor device characterized by having a large size.