JPS62276882A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve performances of a semiconductor element by providing a 2nd semiconductor layer on a 1st semiconductor layer, while electron affinity in the 2nd semiconductor layer is larger than that of the 1st semiconductor layer and furthermore, providing a 3rd semiconductor layer on the 2nd semiconductor layer, while electron affinity in the 3rd semiconductor layer is smaller than that of the 2nd semiconductor layer. CONSTITUTION:A high purity or p-type 2nd semiconductor layer 2 is provided on a 1st semiconductor layer 1, while electron affinity in the 2nd semiconductor layer is larger than that of the 1st semiconductor layer and furthermore, a 3rd semiconductor layer 3 is provided on the 2nd semiconductor layer 2, while electron affinity in the 3rd semiconductor layer is smaller than that of the 2nd semiconductor layer and thickness of 2nd semiconductor layer 2 shall be minimum or less enough for a disposition to be developed. The 2nd semiconductor layer consists of indium gallium arsenide, while the 1st and 3rd semiconductor layers 1 and 3 consist of gallium arsenide or gallium aluminium arsenide and further, one discontinuous amount at least out of energy discontinuous amounts ranging from a quantum level formed in the 2nd semiconductor layer 2 to conductive bands of the 1st and 3rd semiconductor layers 1 and 3 is in a state that a composition of gallium arsenide and aluminium is larger than an energy discontinuous amount of conductive band formed by a gallium aluminium arsenide layer of 0.25. Thus, such a preparation for the 3rd semiconductor layer in addition to 1st and 2nd semiconductor layers reduces the source resistance and improves performances of semiconductor element in comparison with conventional ones.

Description

[Detailed Description of the Invention] Detailed Description of the Invention (Field of Industrial Application) The present invention uses two-dimensional conduction at the heterojunction interface of semiconductors with different electron affinities or with different sums of electron affinities and energy gaps. related to semiconductor devices.

(Prior art) A field effect transistor (FET) uses two-dimensional electrons or holes accumulated at the heterojunction interface of semiconductors with different electron affinities or semiconductors with different electron affinities and energy gaps. Holes have attracted increasing attention in recent years because they have a high mobility, especially at low temperatures.

For example, two-dimensional electrons accumulated on the GaAs layer side of the heterojunction interface between gallium arsenide (hereinafter referred to as GaAs) and a semiconductor layer that has a lower electron affinity than an n-type doped GaAs layer, such as an aluminum gallium arsenide (hereinafter referred to as AIGaAs) layer. It operates by controlling the channel with the voltage of gate electrons.

Now, in such a transistor, the surface charge density of two-dimensional electrons accumulated at the interface is determined by the amount of discontinuity in the energy bands of GaAs and GaAlAs and the amount of n-type impurity doped into the GaAlAs layer. The larger the amount, the higher the surface charge density of electrons, which leads to a reduction in the resistance between the gate and source in transistor operation. Therefore, if the aluminum (hereinafter referred to as AI) composition of the GaAlAs layer is increased, the amount of discontinuity in the energy band increases, but when the Al composition is around 0.4, the energy band of AlGaAs becomes indirect transition type rather than direct transition type, and the energy band increases. The amount of band discontinuity does not increase. Furthermore, a GaAlAs layer with a high Al composition has a high possibility of incorporating oxygen during crystal growth, which may deteriorate its electrical characteristics. Therefore, in a field effect transistor (FET) using two-dimensional electrons accumulated at the heterojunction interface of AlGaAs and GaAs, AlGaAs
The A1 composition of As is about 0.3. Similarly, when two-dimensional holes are used, the A1 composition of AlGaAs is about 0.5.

(Problems to be Solved by the Invention) When two-dimensional electrons or holes are accumulated at a semiconductor heterojunction interface, an electron or hole trapping center such as an interface level exists near the junction interface. Do not. Therefore, when using two types of semiconductors with different electron affinities or two types of semiconductors with different sums of electron affinities and energies choose something. Therefore, for example, in the case of TII group and group II compound semiconductor crystals, by using two types of semiconductors that are lattice matched with the substrate, especially GaAs and indium substrates, and have different electron affinities, or two types of semiconductors that have different sums of electron affinities and energy gaps. Naturally, it is constrained by the difference in electron affinity or the difference in the sum of electron affinity and energy band.

The purpose of the present invention is to enable two types of semiconductors with different electron affinities or with different sums of electron affinities and energy gaps to have a larger difference in electron affinities, or a difference in the sum of electron affinities and energy gaps, without being limited by lattice matching. It is an object of the present invention to provide a semiconductor device such as an FET, which makes it possible to increase the concentration of interfacial electrons accumulated at a heterojunction interface, and therefore has a small source resistance.

(Means for Solving the Problems) The present invention is characterized in that a high purity or p-type second semiconductor layer having a higher electron affinity is provided on the first semiconductor layer, and a second semiconductor layer is further provided on the second semiconductor layer. A semiconductor in which a third semiconductor layer having a smaller electron affinity is provided and an electron channel is formed on the second semiconductor side of the second interface between the second and third semiconductor layers or the first and second semiconductor layers. In the device, the second
A semiconductor device characterized in that the thickness of the semiconductor layer is less than the minimum thickness at which dislocations occur.

Further, the second semiconductor layer is indium gallium arsenide, and the first or third semiconductor layer is gallium arsenide or gallium aluminum arsenide, and the electron quantum level formed in the second semiconductor layer and the first and third semiconductor layers are At least one of the energy discontinuities up to the conductive band of the semiconductor layer is larger than the energy discontinuity of the conductive band formed from the gallium arsenide and gallium aluminum arsenide layer with an aluminum composition of 0.25. It is a feature.

The present invention also provides a high purity or n-type second semiconductor having a smaller sum of electron affinity and energy gap than the first semiconductor.
A third semiconductor layer having a larger sum of electron affinity and energy gap is provided on the second semiconductor layer.
semiconductor layers are provided and the second and third or first and second semiconductor layers are provided.
A semiconductor device in which a hole channel is formed on the second semiconductor side of an interface of a semiconductor layer, characterized in that the thickness of the second semiconductor layer is less than the minimum thickness at which dislocations occur.

Further, the second semiconductor layer is indium gallium arsenide, and the first or third semiconductor layer is gallium arsenide or gallium aluminum arsenide. Of the energy discontinuities up to the valence band of the semiconductor layer, at least one discontinuity is greater than the energy discontinuity of the valence band formed from a gallium arsenide and gallium aluminum arsenide layer with an aluminum composition of 0.4. It is characterized by its large size.

(Function) A second semiconductor layer having a higher electron affinity than the first semiconductor layer is provided, and a third semiconductor layer having a lower electron affinity is further provided on the second semiconductor layer. Therefore, an electron channel is formed on the second semiconductor side of the interface between the second and third semiconductor layer or the first and second semiconductor layer, but at this time, the second semiconductor layer is not lattice matched as in the conventional case. do not have. However, since the thickness of the second semiconductor layer is below a certain thickness, dislocations do not occur due to lattice mismatch. Therefore, the conventional restriction on the amount of discontinuity in the conduction band due to lattice matching is eliminated, and two types of semiconductors that provide a larger amount of discontinuity can be selected. However, no dislocations occur, and therefore no electron trapping centers such as interface states are generated.

(Example 1) As shown in the figure, GaAs, indium gallium arsenide with an indium composition of 0.3 (hereinafter referred to as In.3Gao7As), and AIJfl composition of 0.25 or more, for example, 0.3 aluminum gallium arsenide (hereinafter referred to as Alo, aGao, 7AS) The present invention will be explained using an example of a semiconductor device comprising the following. FIG. 1 shows high-purity GaAs1 as the first semiconductor layer, high-purity Iuo, aGao7AS2, and
This figure shows an end view of a device epitaxially grown on a semiconducting wire type GaAs substrate 4 using n-type Gao7Al and 3As3 as the third semiconductor layer. 5 in the figure is a source electrode,
6 is a gate electrode, and 7 is a drain electrode. The epitaxial method is a molecular beam epitaxial method to form a high purity gallium arsenide layer 1 with a thickness of approximately 8000 angstroms, Iuo3Gao7.
As layer 2 is 80 angstroms, silicon is 2x10
""cm = 4 doped Alo3Gao7As layers
The gate electrode 6 is made of aluminum, and the ohmic electrode 5.7 is made of gold, germanium, and nickel.

FIG. 2 is an energy band phase diagram in a thermal equilibrium state in the depth direction under the gate in the case of a normally-on type transistor, for example. Here Ec2Ev, E
, are the energy level values t and Ki at the lower end of the conduction band, respectively
The energy level at the upper end is the Fermi level, which is 8EC
I is Ino3Gao7As and Gao, 7A1o, 3A
The difference in electron affinity at the S interface, ΔEC2, is between GaAs and Iu.
0B is the barrier height of the gate Schottky barrier, 9 is the electron charge amount, and e schematically represents the ionized donor in the GaAlAs layer.

As a result of observation using a transmission electron microscope in such a state, no crystal transition exceeding that of the GaAs substrate was observed in the Ino 3Gao and 7AS layers. On the other hand, Iu. 3G
When the thickness of aO,7AS was 100 angstroms, crystal dislocations exceeding that of the substrate were observed, and it was found that 100 angstroms was the minimum thickness at which dislocations occurred.

In such a structure, the Gao7A1o3AS layer 3 is completely depleted, and Gao7A1o3As3 and Iuo3G
Two-dimensional electrons accumulate at the boundary of ao7As2, and this surface charge density increases as 8EC□ increases, and Iuo3Ga
The amount of discontinuity between o7As and Gao, 7Alo 3As is I
uo 3Gao, 7AS band gap 1.1eV
Furthermore, 3 out of the band gap differences with the GaAlAs layer
Assuming that 2/2 is the amount of discontinuity in the valence band, approximately 0
．． It is estimated to be 45 eV. As a result, conventional GaAs, Gao, and 7Al. , the amount of discontinuity when using 3As is 0.
Compared to 25 eV, the ΔECI using the present invention is about 8
It is considered to be 0% larger. Also, in the structure shown in Fig. 2, 2
The surface charge density of dimensional electrons is 1.5 x 1012 cm-2
Met. On the other hand, in the conventional structure, that is, in Fig. 2, Iuo
, 3Gao, and 7AS2, the measured two-dimensional electron surface charge density is 1. I x 1012cm-
2, which was about 70% of the present invention. Further, in the FET shown in FIG. 1, the source resistance was 0.4 ohms per millimeter. On the other hand, in the Iuo3Ga (1,7As layer 2 excluded) FET fabricated using the same process, the source resistance was 0.6 ohm per millimeter.
, 3Gao, and 7AS layers having a thickness of 100 angstroms or more, no reduction in source resistance was observed.

(Example 2) GaAs and IuGaAs have the same structure as in Example 1.

An example of a semiconductor device made of AlGaAs will be explained.

This example differs from Example 1 in that A1 is used as the third semiconductor layer.
GaO, BAlo, and 2As with a composition of 0.2 are used. As shown in FIG. 1, high purity Qa is used as the first semiconductor layer.
Asl and high purity Iu as the second semiconductor layer. ,3Gao
7AS2 and Gao8A1°, 2As were epitaxially grown on a semi-insulating GaAs substrate 4.

In such a structure Iu. Assuming that the band gap of 5Gao, qAs is 1.1 eV and that two-thirds of the difference in band gap with the Gao8A1o2As layer is a discontinuity in the valence band, it is estimated to be about 0.36 eV. Therefore, as in Example 1, conventional GaAs and GaO
, discontinuity amount 0.25 eV when using 7Alo3As
ΔEC1 is larger than that. It was also found that the surface charge density of two-dimensional electrons is 1.4×10 12 cm −3 , which is larger than the surface charge density of two-dimensional electrons in the conventional structure.

A reduction in source resistance was also observed in FETs.

In the above explanation, the case where the carrier is an electron has been explained. The present invention is equally applicable to the case where the carrier is a hole. In this case, holes are accumulated on the valence band side, so a semiconductor with a sum of electron affinity and energy gap smaller than that of the first semiconductor is used as the second semiconductor in FIG. Using a semiconductor having a larger sum of electron affinity and energy gap than the second semiconductor as the third semiconductor, the third semiconductor layer is doped with an acceptor at high density. Here, the energy band phase diagram in the thermal equilibrium state is as shown in FIG. Here, θ is a schematic representation of an ionized acceptor, and 2' is a two-dimensional hole.

In this example, the substrate is made of semi-insulating GaAs, the first semiconductor layer is a high purity GaAs layer, and the second semiconductor layer is Iu. Alo5Gao5As is used as the 3Gao7As layer and the third semiconductor layer.

(Effects of the Invention) As is clear from the above explanation, the present invention suppresses the occurrence of dislocations by reducing the thickness of the semiconductor layer despite using semiconductors with different lattice constants, and uses a semiconductor with lattice matching. This has the advantage that it is possible to form a heterojunction with a larger difference in electron affinity or a difference in the sum of electron affinity and energy gap compared to conventional cases, and it is possible to reduce the source resistance in FETs using this. The effect of improving the performance of semiconductor devices is remarkable compared to that of conventional methods.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of a semiconductor device according to the present invention;
FIGS. 2 and 3 are energy band state diagrams thereof. 1... High purity gallium arsenide, 220. High purity indium gallium arsenide, 3... n-type gallium aluminum arsenide, 401. Semiconductor wire type gallium arsenide substrate, 5... source electrode, 6..., gate electrode,
7... Drain electrode, Figure 1, Figure 5 Source electrode, Figure 2, Figure 3, Procedural amendment (voluntary) 2. Name of the invention Semiconductor device 3. Person making the amendment Relationship to the Akihiko Okamoto case Inventor Applicant Tokyo Metropolitan Government 5-33-1 Shiba, Minato-ku (423) NEC Co., Ltd. Representative Shihiro Sekimoto 4, Agent: 1 (Contact address: Patent Department, NEC Co., Ltd.) 5. Specification subject to amendment Detailed Description of the Invention Column 6, Contents of Amendment 1) The following sentence is inserted after the 18th line on page 11 of the specification. “In this example, the indium composition was 0.3,
For example, in the case of indium compositions of 0.15 and 0.23, the same sheet resistance as in the case of 0.3 is obtained, and the indium composition of the present invention is not limited to 0.3. 2) Page 9, line 13 of the specification and page 10, 6, 13.19
Line 14 and page 11. Line 17 and page 12 1, 7.
rIuJ on line 10 and line 16 on page 11.
Corrected as In J. 3) Insert the following sentence after line 17 on page 13 of the specification. "In this example, the indium composition was 0.3, but the indium composition of the present invention is not limited to 0.3." 4) "High Purity GaAs 1 J is corrected as "high purity GaAs layer 1". 5) Page 9, line 7 and page 10, line 17 and 1 of the specification
``IuO,3GaO,7AS2J'' on page 1, line 10 is corrected to rInO,3Ga(1,7AS layer 2j). 6) In the specification, page 9, line 8 and page 10, line 17, r G
a0.7A1 (1,3AS3 J is r GaO
, 7A1g, and 3As layer 3j.

Claims (4)

[Claims] (1) A high-purity or p-type second semiconductor layer with a higher electron affinity is provided on the first semiconductor layer, and a third semiconductor layer with a lower electron affinity is provided on the second semiconductor layer.
In a semiconductor device in which a semiconductor layer is provided and an electron channel is formed on the second semiconductor side of the interface between the second and third semiconductor layers or the first and second semiconductor layer, the thickness of the second semiconductor layer is A semiconductor device characterized in that the thickness is less than the minimum thickness at which dislocations occur. (2) The second semiconductor layer is indium gallium arsenide, and the first or third semiconductor layer is gallium arsenide or gallium aluminum arsenide. At least one of the energy discontinuities up to the conductive band of the semiconductor layer in step 3 is larger than the energy discontinuity of the conductive band formed from the gallium arsenide and gallium aluminum arsenide layer having an aluminum composition of 0.25. A semiconductor device according to claim 1, characterized in that: (3) A high-purity or n-type second semiconductor layer with a smaller sum of electron affinity and energy gap is provided on the first semiconductor layer, and a second semiconductor layer with a smaller sum of electron affinity and energy gap is provided on the second semiconductor layer. In a semiconductor device in which a third semiconductor layer having a large sum of A semiconductor device characterized in that the thickness of the semiconductor layer is less than the minimum thickness at which dislocations occur. (4) The second semiconductor layer is indium gallium arsenide, and the first or third semiconductor layer is gallium arsenide or gallium aluminum arsenide. At least one of the energy discontinuities up to the valence band of the third semiconductor layer is the energy discontinuity of the valence band formed from gallium arsenide and a gallium aluminum arsenide layer with an aluminum composition of 0.4. 4. The semiconductor device according to claim 3, wherein the semiconductor device is larger than .