JPS594085A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS594085A JPS594085A JP11283982A JP11283982A JPS594085A JP S594085 A JPS594085 A JP S594085A JP 11283982 A JP11283982 A JP 11283982A JP 11283982 A JP11283982 A JP 11283982A JP S594085 A JPS594085 A JP S594085A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gate electrode
- xas
- composition ratio
- gaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 39
- 239000000203 mixture Substances 0.000 claims abstract description 19
- 239000012535 impurity Substances 0.000 claims description 12
- 230000007704 transition Effects 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 14
- 238000003860 storage Methods 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 3
- 238000005036 potential barrier Methods 0.000 abstract 2
- 238000005275 alloying Methods 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 11
- 239000013078 crystal Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 101100046352 Mus musculus Tjap1 gene Proteins 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000002109 crystal growth method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- HDDJZDZAJXHQIL-UHFFFAOYSA-N gallium;antimony Chemical compound [Ga+3].[Sb] HDDJZDZAJXHQIL-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
(n) 発明の技術分野
本発明は半導体装置に関し、特に本特許出願人が先に特
願昭55−82035号により提案した半導体装置の改
良に関する。DETAILED DESCRIPTION OF THE INVENTION (n) Technical Field of the Invention The present invention relates to a semiconductor device, and more particularly to an improvement of a semiconductor device previously proposed by the applicant of the present patent in Japanese Patent Application No. 82035/1982.
(I])技術の背景
情報処理装置の能力及びコストパフォーマンスの一層の
向上はこれにイi−用される半導体装置にがかっている
と目され、論理演算装置の高速化、低消費電力化及び記
憶装置の大容量化が強力に推進されている。(I) Background of the technology It is believed that further improvements in the performance and cost performance of information processing devices depend on the semiconductor devices used for them, and the improvement in the speed, lower power consumption, and There is a strong push toward increasing the capacity of storage devices.
現在は専らシリコン(St)半導体装置が実用化されて
いるが、si半導体装置の高速化はキャリアの移動度な
どのStの物性により制約されるために、キャリア移動
度がSiより遥かに大きいガリウム・砒素(GaAs)
などの化合物半導体を用いて、高速化、低消費電力化を
実現する努力が重ねられている。Currently, only silicon (St) semiconductor devices are in practical use, but the speedup of Si semiconductor devices is limited by the physical properties of St, such as carrier mobility.・Arsenic (GaAs)
Efforts are being made to achieve higher speeds and lower power consumption using compound semiconductors such as.
従来の構造のStもしくはGaAs等の化合物を用いた
半導体装置においては、キャリアは不純物イオンが存在
している空間を移動する。この移動に際してキャリアは
格子振動および不純物イオンによって散乱を受けるが、
格子振動による散乱の確率を小さくするために塩度を低
下させると。In a semiconductor device using a compound such as St or GaAs having a conventional structure, carriers move in a space where impurity ions are present. During this movement, carriers are scattered by lattice vibrations and impurity ions,
When the salinity is lowered to reduce the probability of scattering due to lattice vibrations.
不純物イオンによる散乱の確率が大きくなって。The probability of scattering by impurity ions increases.
キャリアの移動度がこれによって制限される。This limits carrier mobility.
この不純物散乱効果を排除するために不純物が添加され
る領域と、キャリアが移りJする領域とを空間的に分離
して、特に低温におけるキャリアの移動度を増大・已し
めたものが本発明の対象とする半導体装置である。In order to eliminate this impurity scattering effect, the region to which impurities are added and the region to which carriers are transferred are spatially separated, thereby increasing carrier mobility especially at low temperatures. This is the target semiconductor device.
(C1従来技術と問題点
半導体装置の従来知られている構造の一例を第1図fn
+に示す断面図を参照して説明する。ず絶縁性GaΔS
基板1−1−にノンドープGaAs層2とこれより電子
親和力の小さいn型アルミニウム・ガリウム・砒素(Δ
IGaΔS)層3とが設けられて2両層の界面はへテロ
エピタキシャル接合を形成している。n型ΔI G a
A s層3 (電子供給層という)からノンドープG
aAs層2 (ヂャネル屓という)へ電子が遷移される
ことによって生成される電子蓄積層(2次元電子層)4
の電子濃度を、ケート電極5に印加される電圧によって
制御するーとによって、ソース電極6とドレイン電)・
翫7との間の電子蓄積層4によって形成される伝導路の
インピーダンスが制御される。なお8は抵抗性接続(オ
ーミックコンタクト)領域である。(C1 Prior Art and Problems An example of a conventionally known structure of a semiconductor device is shown in Figure 1 fn
This will be explained with reference to the cross-sectional view shown at +. Insulating GaΔS
A non-doped GaAs layer 2 and an n-type aluminum/gallium/arsenic (Δ
IGaΔS) layer 3 is provided, and the interface between the two layers forms a heteroepitaxial junction. n-type ΔI G a
Non-doped G from A s layer 3 (referred to as electron supply layer)
an electron storage layer (two-dimensional electron layer) 4 generated by electrons being transferred to the aAs layer 2 (called a channel layer);
By controlling the electron concentration of the source electrode 6 and the drain voltage by controlling the voltage applied to the gate electrode 5,
The impedance of the conduction path formed by the electron storage layer 4 between the electrode 7 and the electron storage layer 4 is controlled. Note that 8 is a resistive connection (ohmic contact) region.
以上説明した構造の半導体装置において、ゲート電極5
は最も一般的にはアルミニウム(Al)によって構成さ
れて、n型A l xGal −xAS層3との間にシ
ョソ1−キハリアが形成されている。In the semiconductor device having the structure explained above, the gate electrode 5
is most commonly made of aluminum (Al), and a shozo 1-kihalia is formed between it and the n-type AlxGal-xAS layer 3.
このn型Δ1xGa1−xΔs Ti43は、この層全
体が必ずしもドナ゛−不純物を含ます、Ga八へM2と
のへテロエビクキシャル接合界面近傍がノンドープのバ
ッファとされる場合がある。この場合を含めて、n型も
しくはノン1−−プのΔIX(Jal−xASM3のA
Iの組成比Xば従来0. 3程度であり、第1図fal
の各層に対応させて第1図(blに例示する如く、AI
xGa t−xAsFt全体を通じてAIの組成比X
が一定である構造が普通である。In this n-type Δ1xGa1-xΔs Ti43, the entire layer does not necessarily contain a donor impurity, but the vicinity of the heteroepitaxial junction interface with Ga8 and M2 may be used as a non-doped buffer. Including this case, n-type or non-1-type ΔIX (Jal-xASM3 A
If the composition ratio of I is X, then conventionally 0. 3, and Figure 1 fal
As illustrated in Figure 1 (bl), AI
The composition ratio of AI throughout xGa t-xAsFt
A structure where is constant is common.
これはAI・の組成比Xを0.3程度より大きくするな
らば、 (イ)へテロ接合におりる格子整合が悪化して
接合界面に乱れを生じ易い。(ロ)ΔIxGa1−xA
s層中に八1に件って酸素が混入し、キャリアのトラッ
プとして作用する深いレヘルが形成されて結晶の電子的
特性に悪影響を与え易い等の問題を生ずるためである。This is because if the composition ratio X of AI is made larger than about 0.3, (a) the lattice matching at the heterojunction deteriorates, which tends to cause disturbances at the junction interface. (b)ΔIxGa1-xA
This is because oxygen is mixed into the s-layer, forming deep layers that act as carrier traps, which tends to adversely affect the electronic properties of the crystal.
しかしこのAIの組成比0.3程度のΔ1xGal−x
As層3上にゲート電極5が配設されている場合には、
Al xGa 1−xASAsF3−ト電極界面でのピ
ルティングポテンシャルが比較的低い為にデー1−電極
5から八1%Gal −XAS層3へ流れるリーク電流
を生じ、ゲート電極に印加する電圧に制限を受けてしま
うという問題力5ある。However, this AI has a composition ratio of about 0.3, Δ1xGal-x.
When the gate electrode 5 is arranged on the As layer 3,
Since the pilt potential at the Al xGa 1-xASAsF3- electrode interface is relatively low, a leakage current flows from the electrode 5 to the 81%Gal-XAS layer 3, which limits the voltage applied to the gate electrode. There is a problem power 5 of being accepted.
(d+ 発明の目的
本発明は、ゲート電極に於けるリーク電流を低減し、ゲ
ート電極に印加される電圧に余裕をもたせることが可能
な半導体装置を提供するにある。(d+ OBJECTS OF THE INVENTION The present invention provides a semiconductor device that can reduce leakage current in a gate electrode and provide a margin for the voltage applied to the gate electrode.
te)発明の構成
本発明の前記目的は、第1の半導体層と、該第1の半導
体層より電子親和力が小であり、かつn型不純物を含む
第2の半導体層とを有して、前記第1の半導体層と前記
第2の半導体層とがへテロ接合を形成し、前記第2の半
導体層から前記第1の半導、体層に遷移する電子によっ
て構成される2次元電子層を電流路とする半導体装置で
あって。te) Structure of the Invention The object of the present invention is to have a first semiconductor layer and a second semiconductor layer having a lower electron affinity than the first semiconductor layer and containing an n-type impurity, A two-dimensional electronic layer in which the first semiconductor layer and the second semiconductor layer form a heterojunction, and the electrons transition from the second semiconductor layer to the first semiconductor layer and the body layer. A semiconductor device having a current path as a current path.
前記第2の半導体層を構成する元素の組成比がケート電
極近傍においてビルティンクポテンシャルが高くなる如
くされてなることにより達成される。This is achieved by adjusting the composition ratio of the elements constituting the second semiconductor layer such that the Biltink potential is high in the vicinity of the gate electrode.
すなわち本発明は、従来2次元電子層の特性の最適化条
件のみに従って構成されている前記例におりるAlGa
As層に一ついて、2次元電子層の特性を支配するのは
この△lGaΔSI′Fiの不純物をドープされた領域
のうちの僅少な部分2例えばヘテロ接合界面より厚さ6
(nm’l稈度のノントa−3
一プ領域を介して濃度2XlO(Cm )程度の領域
が形成されている場合に、2次元電子Hの特性は、不純
物をドープされた領域のうらノン1−−プ領域に隣接す
る厚さ3(’nm)程度の部分のめによって支配される
事実に基づいて、△IGa△sMの前記部分よりヘテロ
接合界面までの7jl−分については電子供給層として
の最適北条イノ1.△IGaΔskiの残る表面側の部
分について電極か形成されてこれと能動Qliとを接続
する表面制御層としての最適化条件に従って構成するも
のである。。That is, the present invention is directed to the above-mentioned AlGa
In the As layer, the characteristics of the two-dimensional electronic layer are controlled by a small portion 2 of the impurity-doped region of △lGaΔSI'Fi, for example, a thickness 6 below the heterojunction interface.
(When a region with a concentration of about 2XlO (Cm Based on the fact that the portion of △IGa△sM with a thickness of about 3 ('nm) adjacent to the 1--p region is dominated by the electron supply layer, the 7jl-min. Optimal Hojo Ino 1.An electrode is formed on the remaining surface side portion of ΔIGaΔski and is constructed in accordance with optimization conditions as a surface control layer connecting this with active Qli.
混晶系化合物半導体の物性を制御するパラメータとして
は混晶の組成比と、これにドープされる不純物濃度とが
挙げられるが2本発明は混晶の組成比について前記のそ
れぞれ独立した最適化を実施するものである。Parameters that control the physical properties of mixed crystal compound semiconductors include the composition ratio of the mixed crystal and the concentration of impurities doped therein.2 The present invention is capable of independently optimizing the composition ratio of the mixed crystal as described above. It is to be implemented.
ffl 発明の実施例
以下本発明を実施例により図面を参照して具体的に説明
する。ffl Embodiments of the Invention The present invention will be specifically described below by way of embodiments with reference to the drawings.
第2図(alはGaAs及びAIxG、at −xAs
を用いて構成された本発明の実施例の断面図、第2図(
blは本実施例におけるAIの組成比Xの分布例を第2
図(alの各層に対応させて示す図表である。Figure 2 (al is GaAs and AIxG, at -xAs
FIG. 2 is a sectional view of an embodiment of the present invention constructed using
bl is the second distribution example of the composition ratio X of AI in this example.
(This is a chart shown in correspondence to each layer of Al.
本実施例の半導体装置は大略下記の如くに製造される。The semiconductor device of this embodiment is manufactured approximately as follows.
半絶縁性のGaAs基板11上に分子線結晶成長法(M
olecular Beam Epitaxy:以
下MBE法と略称する。)によって実質的に不純物を含
有せず、厚さ1 〔μm〕程度のcaAs層’(チャネ
ル層)12と、AlxC;a】−xAs層の実質的に不
純物を含有しない厚さ6(nm)程度の領域13. 2
X I Q” (cm−3)程度の濃度に例えばシリ
コン(Si)がドープされた厚さ3 (nm)以上の領
域14及び同一ドーピング濃度の厚さ50乃至1010
0(n程度の領域15とを順次形成する。A molecular beam crystal growth method (M
Olecular Beam Epitaxy: Hereinafter abbreviated as MBE method. ), the caAs layer' (channel layer) 12 is substantially free of impurities and has a thickness of approximately 1 [μm], and the AlxC;a]-xAs layer is substantially free of impurities and has a thickness of 6 (nm). Area of degree 13. 2
A region 14 with a thickness of 3 (nm) or more doped with silicon (Si), for example, to a concentration of about
0 (n regions 15) are sequentially formed.
本実施例においてAlxGa1−xAs層の八lの組成
比Xは、第1の不純物を含有しない領域13及び第2の
不純物をドープした領域14についてはX=0.3程度
の一定値であり、最後の不純物をドープした領域15に
ついては、前記領域14に接する端においては領域14
に等しく1次第にXが増大すなわちAlの組成比が増大
して。In this example, the composition ratio X of the AlxGa1-xAs layer is a constant value of about 0.3 for the first impurity-free region 13 and the second impurity-doped region 14, Regarding the last region 15 doped with impurities, at the end touching the region 14, the region 14
As X gradually increases, that is, the composition ratio of Al increases.
第2の半導体層の上表面においてはX=0.4程度に到
っている。At the upper surface of the second semiconductor layer, X=approximately 0.4.
前記エピタキシャル成長層を形成した後に、金・ゲルマ
ニウム(AuGe)/金(Au)層をソース電極16及
びドレイン電極17を配設する位置に選択的に蒸着し、
更に温度450(”C)時間3分間程度の熱処理を施し
てこれを合金化し、チャネル層であるGaAs層12と
の抵抗性接続領域18を形成する。次いでゲート電極1
9を例えばアルミニウム(AI)を用いて従来技術によ
って形成する。なお20は電子蓄積層を示す。After forming the epitaxial growth layer, a gold/germanium (AuGe)/gold (Au) layer is selectively deposited at the positions where the source electrode 16 and the drain electrode 17 are to be provided,
Further, heat treatment is performed at a temperature of 450° C. for about 3 minutes to alloy this, forming a resistive connection region 18 with the GaAs layer 12 which is a channel layer.
9 is formed by conventional techniques using, for example, aluminum (AI). Note that 20 indicates an electron storage layer.
以上説明した製造方法によって得られる本実施例の半導
体装置のエネルギ帯を第3図に示す。ただし第3図にお
いては第2図ta+と同一符号によって対応部分を示し
、一点鎖線にて示したEfはフェルミ準位、実線にて示
したEcは伝導帯、 EVは価電子帯の従来技術によっ
てA 1 xGal−xAs層全体についてA1の組成
比Xが0.3程度一定値である場合を示し、領域15に
示した破線は本発明の前記実施例において従来例と異な
る状態を示す。FIG. 3 shows the energy band of the semiconductor device of this example obtained by the manufacturing method described above. However, in Fig. 3, corresponding parts are indicated by the same symbols as ta+ in Fig. 2, Ef shown by a dashed-dotted line is the Fermi level, Ec shown by a solid line is the conduction band, and EV is the valence band according to the conventional technology. This shows a case where the composition ratio X of A1 is a constant value of about 0.3 for the entire A 1 xGal-xAs layer, and the broken line shown in region 15 shows a situation in the embodiment of the present invention that is different from the conventional example.
第3図より明らかなる如く1本発明の構造においては、
ゲート電極19とAIGaz −xAs層の領域15と
の接触界面におけるバリアの大きさが従来より増大し、
ピルティングポテンシャル■biが増大する為、ゲート
電極19からAlxGar xAs層の領域15へ流れ
るリーク電流を低減でき、従来よりも高いゲート電圧を
設定できる。As is clear from FIG. 3, in the structure of the present invention,
The size of the barrier at the contact interface between the gate electrode 19 and the region 15 of the AIGaz-xAs layer is increased compared to the conventional one,
Since the pilting potential ■bi increases, the leakage current flowing from the gate electrode 19 to the region 15 of the AlxGarxAs layer can be reduced, and a higher gate voltage can be set than before.
なお先に述べた如<、AlxGax−xAs層のAIの
組成比Xを増加することは格子整合については不利な条
件ではあるが、このことは2組成比Xの増加勾配の選択
によって容易に解決することができ、酸素の混入による
キャリアのトラップの増加もMBE成長法の改良によっ
てかなり改善できる。As mentioned above, increasing the Al composition ratio X of the AlxGax-xAs layer is a disadvantageous condition for lattice matching, but this can be easily resolved by selecting the increasing slope of the composition ratio X. The increase in carrier trapping due to the incorporation of oxygen can also be significantly improved by improving the MBE growth method.
なお、ソース及びドレイン電極をゲート電極とは異なる
半導体面上に形成しても良い。Note that the source and drain electrodes may be formed on a different semiconductor surface than the gate electrode.
更に以上の説明はGaAs/AlGa八Sを用いた半導
へ装置を例としたが、半導体装置は例えばガリウム・ア
ンチモン(GaSb)とアルミニウム・ガリウム・アン
チモン(AIyGal−ysb)との組合せ等によって
も構成することが可能であって、この様なGaAs/A
lGaAs系以外の材料による半導体装置についても本
発明を同様に適用することが可能である。Furthermore, although the above explanation has taken as an example a semiconductor device using GaAs/AlGa8S, semiconductor devices can also be made using a combination of gallium antimony (GaSb) and aluminum gallium antimony (AIyGal-ysb). It is possible to construct such a GaAs/A
The present invention can be similarly applied to semiconductor devices made of materials other than lGaAs.
(gl 発明の効果
本発明によれば以上説明した如く、ゲート電極近傍での
半導体層の元素の組成比をピルティングポテンシャルが
高くなるように選択することにより、ゲート電極に於け
るリーク電流を低減でき。(gl Effects of the Invention According to the present invention, as explained above, by selecting the composition ratio of the elements of the semiconductor layer in the vicinity of the gate electrode so as to increase the pilt potential, leakage current in the gate electrode can be reduced. I can do it.
ゲート電極に印加する電圧に余裕をもたせることができ
る。It is possible to provide a margin for the voltage applied to the gate electrode.
第1図(alは従来例を示す断面図、第1図(blはそ
の各層のAIの組成比Xを示す図表、第2図falは本
発明の実施例を示す断面図、第2図(blはその各層の
AIの組成比Xを示す図表、第3図はそのエネルギ帯を
示す図表である。
図において1はGaAs基板、2はGaAs層。
3はΔIxGa]−xAs層、4は電子蓄積層。
5はゲート電極、6はソース電極、7はドレイン電極、
8ば抵抗性接続領域、11はGaAs基板。
12はノン・ドープGaAs層、13はAIXGaz−
xAs層のノンドープ領域、14はAlxQal−XA
S層の電子供給領域、15はAlxGa1−xAs層の
表面制御領域、16はソース電極、17はドレイン電極
、18は抵抗性接続領域、19はゲート電極、20は電
子蓄積層を示す。
第 1 図
(a)(1))
第 2 図
(a) (b)第 3 図Figure 1 (al is a sectional view showing the conventional example, Figure 1 (bl is a chart showing the composition ratio X of AI in each layer), Figure 2 fal is a sectional view showing the embodiment of the present invention, Figure 2 ( bl is a chart showing the composition ratio X of AI in each layer, and Fig. 3 is a chart showing its energy band. In the figure, 1 is a GaAs substrate, 2 is a GaAs layer, 3 is a ΔIxGa]-xAs layer, and 4 is an electron Storage layer. 5 is a gate electrode, 6 is a source electrode, 7 is a drain electrode,
8 is a resistive connection region, and 11 is a GaAs substrate. 12 is a non-doped GaAs layer, 13 is an AIXGaz-
Non-doped region of xAs layer, 14 is AlxQal-XA
An electron supply region of the S layer, 15 a surface control region of the AlxGa1-xAs layer, 16 a source electrode, 17 a drain electrode, 18 a resistive connection region, 19 a gate electrode, and 20 an electron storage layer. Figure 1 (a) (1)) Figure 2 (a) (b) Figure 3
Claims (1)
小であり、かつn型不純物を含む第2の半導体層とを有
して、前記第1の半導体層と前記第2の半導体層とがへ
テロ接合を形成し、前記第2の半導体層から前記第1の
乎導体層に遷移する電子によって構成される2次元電子
層を電流路とする半導体装置であって、前記第2の半導
体層を構成する元素の組成化がゲート電極近傍において
ビルティングポテンシャルが高くなる如くされてなるこ
とを特徴とする半導体装置。a first semiconductor layer and a second semiconductor layer having a lower electron affinity than the first semiconductor layer and containing an n-type impurity; A semiconductor device in which the current path is a two-dimensional electron layer formed by electrons that form a heterojunction with the second semiconductor layer and transition from the second semiconductor layer to the first conductor layer, the semiconductor device comprising: 1. A semiconductor device, characterized in that the composition of elements constituting the semiconductor layer is such that the building potential is high in the vicinity of the gate electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11283982A JPS594085A (en) | 1982-06-30 | 1982-06-30 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11283982A JPS594085A (en) | 1982-06-30 | 1982-06-30 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS594085A true JPS594085A (en) | 1984-01-10 |
JPH0371774B2 JPH0371774B2 (en) | 1991-11-14 |
Family
ID=14596818
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11283982A Granted JPS594085A (en) | 1982-06-30 | 1982-06-30 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS594085A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6154673A (en) * | 1984-08-25 | 1986-03-18 | Fujitsu Ltd | Field-effect type semiconductor device |
EP0201873A2 (en) * | 1985-05-09 | 1986-11-20 | Sumitomo Electric Industries Limited | A method of the production of a metal semiconductor field effect transistor and said transistor |
JPS6490565A (en) * | 1987-10-01 | 1989-04-07 | Mitsubishi Electric Corp | Field-effect transistor |
US5140386A (en) * | 1991-05-09 | 1992-08-18 | Raytheon Company | High electron mobility transistor |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58147158A (en) * | 1982-02-26 | 1983-09-01 | Oki Electric Ind Co Ltd | Compound semiconductor field effect transistor |
-
1982
- 1982-06-30 JP JP11283982A patent/JPS594085A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58147158A (en) * | 1982-02-26 | 1983-09-01 | Oki Electric Ind Co Ltd | Compound semiconductor field effect transistor |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6154673A (en) * | 1984-08-25 | 1986-03-18 | Fujitsu Ltd | Field-effect type semiconductor device |
EP0201873A2 (en) * | 1985-05-09 | 1986-11-20 | Sumitomo Electric Industries Limited | A method of the production of a metal semiconductor field effect transistor and said transistor |
JPS6490565A (en) * | 1987-10-01 | 1989-04-07 | Mitsubishi Electric Corp | Field-effect transistor |
US5140386A (en) * | 1991-05-09 | 1992-08-18 | Raytheon Company | High electron mobility transistor |
Also Published As
Publication number | Publication date |
---|---|
JPH0371774B2 (en) | 1991-11-14 |
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