JPS594085A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a leak current and to raise a gate voltage, by superposing n type AlxGa1-xAs on GaAs to form a heterojunction and by adjusting a composition ratio x to raise a potential barrier in the vicinity of a gate electrode. CONSTITUTION:A non-added GaAs channel 12, AlxGa1-xAs and Si-added Alx Ga1-xAs 14 and 15 are superposed on a half-insulating GaAs substrate 11. A composition ratio x is set at a fixed value of about 0.3 for the layers 13 and 14. The ratio of the layer 15 to the layer 14 is at the same value on the interface with the latter, and it increases gradually to x=0.4 on the surface. Electrodes 16 and 17 of AuGe/Au are attached for alloying, resistance connction layers 18 are provided on the channel 12, and an A gate electrode 19 is attached. A layer 20 is an electron storage layer. According to this constitution, the potential barrier on a contact interface between the gate electrode 19 and an electron supplying layer 15 is made larger than usual, and a leak current from the electrode 19 to the layer 15 is reduced. Thus, some margin can be left by setting a high gate voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION (n) Technical Field of the Invention The present invention relates to a semiconductor device, and more particularly to an improvement of a semiconductor device previously proposed by the applicant of the present patent in Japanese Patent Application No. 82035/1982.

(I) Background of the technology It is believed that further improvements in the performance and cost performance of information processing devices depend on the semiconductor devices used for them, and the improvement in the speed, lower power consumption, and There is a strong push toward increasing the capacity of storage devices.

Currently, only silicon (St) semiconductor devices are in practical use, but the speedup of Si semiconductor devices is limited by the physical properties of St, such as carrier mobility.・Arsenic (GaAs)
Efforts are being made to achieve higher speeds and lower power consumption using compound semiconductors such as.

In a semiconductor device using a compound such as St or GaAs having a conventional structure, carriers move in a space where impurity ions are present. During this movement, carriers are scattered by lattice vibrations and impurity ions,
When the salinity is lowered to reduce the probability of scattering due to lattice vibrations.

The probability of scattering by impurity ions increases.

This limits carrier mobility.

In order to eliminate this impurity scattering effect, the region to which impurities are added and the region to which carriers are transferred are spatially separated, thereby increasing carrier mobility especially at low temperatures. This is the target semiconductor device.

(C1 Prior Art and Problems An example of a conventionally known structure of a semiconductor device is shown in Figure 1 fn
This will be explained with reference to the cross-sectional view shown at +. Insulating GaΔS
A non-doped GaAs layer 2 and an n-type aluminum/gallium/arsenic (Δ
IGaΔS) layer 3 is provided, and the interface between the two layers forms a heteroepitaxial junction. n-type ΔI G a
Non-doped G from A s layer 3 (referred to as electron supply layer)
an electron storage layer (two-dimensional electron layer) 4 generated by electrons being transferred to the aAs layer 2 (called a channel layer);
By controlling the electron concentration of the source electrode 6 and the drain voltage by controlling the voltage applied to the gate electrode 5,
The impedance of the conduction path formed by the electron storage layer 4 between the electrode 7 and the electron storage layer 4 is controlled. Note that 8 is a resistive connection (ohmic contact) region.

In the semiconductor device having the structure explained above, the gate electrode 5
is most commonly made of aluminum (Al), and a shozo 1-kihalia is formed between it and the n-type AlxGal-xAS layer 3.

In this n-type Δ1xGa1-xΔs Ti43, the entire layer does not necessarily contain a donor impurity, but the vicinity of the heteroepitaxial junction interface with Ga8 and M2 may be used as a non-doped buffer. Including this case, n-type or non-1-type ΔIX (Jal-xASM3 A
If the composition ratio of I is X, then conventionally 0. 3, and Figure 1 fal
As illustrated in Figure 1 (bl), AI
The composition ratio of AI throughout xGa t-xAsFt
A structure where is constant is common.

This is because if the composition ratio X of AI is made larger than about 0.3, (a) the lattice matching at the heterojunction deteriorates, which tends to cause disturbances at the junction interface. (b)ΔIxGa1-xA
This is because oxygen is mixed into the s-layer, forming deep layers that act as carrier traps, which tends to adversely affect the electronic properties of the crystal.

However, this AI has a composition ratio of about 0.3, Δ1xGal-x.
When the gate electrode 5 is arranged on the As layer 3,
Since the pilt potential at the Al xGa 1-xASAsF3- electrode interface is relatively low, a leakage current flows from the electrode 5 to the 81%Gal-XAS layer 3, which limits the voltage applied to the gate electrode. There is a problem power 5 of being accepted.

(d+ OBJECTS OF THE INVENTION The present invention provides a semiconductor device that can reduce leakage current in a gate electrode and provide a margin for the voltage applied to the gate electrode.

te) Structure of the Invention The object of the present invention is to have a first semiconductor layer and a second semiconductor layer having a lower electron affinity than the first semiconductor layer and containing an n-type impurity, A two-dimensional electronic layer in which the first semiconductor layer and the second semiconductor layer form a heterojunction, and the electrons transition from the second semiconductor layer to the first semiconductor layer and the body layer. A semiconductor device having a current path as a current path.

This is achieved by adjusting the composition ratio of the elements constituting the second semiconductor layer such that the Biltink potential is high in the vicinity of the gate electrode.

That is, the present invention is directed to the above-mentioned AlGa
In the As layer, the characteristics of the two-dimensional electronic layer are controlled by a small portion 2 of the impurity-doped region of △lGaΔSI'Fi, for example, a thickness 6 below the heterojunction interface.
(When a region with a concentration of about 2XlO (Cm Based on the fact that the portion of △IGa△sM with a thickness of about 3 ('nm) adjacent to the 1--p region is dominated by the electron supply layer, the 7jl-min. Optimal Hojo Ino 1.An electrode is formed on the remaining surface side portion of ΔIGaΔski and is constructed in accordance with optimization conditions as a surface control layer connecting this with active Qli.

Parameters that control the physical properties of mixed crystal compound semiconductors include the composition ratio of the mixed crystal and the concentration of impurities doped therein.2 The present invention is capable of independently optimizing the composition ratio of the mixed crystal as described above. It is to be implemented.

ffl Embodiments of the Invention The present invention will be specifically described below by way of embodiments with reference to the drawings.

Figure 2 (al is GaAs and AIxG, at -xAs
FIG. 2 is a sectional view of an embodiment of the present invention constructed using
bl is the second distribution example of the composition ratio X of AI in this example.
(This is a chart shown in correspondence to each layer of Al.

The semiconductor device of this embodiment is manufactured approximately as follows.

A molecular beam crystal growth method (M
Olecular Beam Epitaxy: Hereinafter abbreviated as MBE method. ), the caAs layer' (channel layer) 12 is substantially free of impurities and has a thickness of approximately 1 [μm], and the AlxC;a]-xAs layer is substantially free of impurities and has a thickness of 6 (nm). Area of degree 13. 2
A region 14 with a thickness of 3 (nm) or more doped with silicon (Si), for example, to a concentration of about
0 (n regions 15) are sequentially formed.

In this example, the composition ratio X of the AlxGa1-xAs layer is a constant value of about 0.3 for the first impurity-free region 13 and the second impurity-doped region 14, Regarding the last region 15 doped with impurities, at the end touching the region 14, the region 14
As X gradually increases, that is, the composition ratio of Al increases.

At the upper surface of the second semiconductor layer, X=approximately 0.4.

After forming the epitaxial growth layer, a gold/germanium (AuGe)/gold (Au) layer is selectively deposited at the positions where the source electrode 16 and the drain electrode 17 are to be provided,
Further, heat treatment is performed at a temperature of 450° C. for about 3 minutes to alloy this, forming a resistive connection region 18 with the GaAs layer 12 which is a channel layer.
9 is formed by conventional techniques using, for example, aluminum (AI). Note that 20 indicates an electron storage layer.

FIG. 3 shows the energy band of the semiconductor device of this example obtained by the manufacturing method described above. However, in Fig. 3, corresponding parts are indicated by the same symbols as ta+ in Fig. 2, Ef shown by a dashed-dotted line is the Fermi level, Ec shown by a solid line is the conduction band, and EV is the valence band according to the conventional technology. This shows a case where the composition ratio X of A1 is a constant value of about 0.3 for the entire A 1 xGal-xAs layer, and the broken line shown in region 15 shows a situation in the embodiment of the present invention that is different from the conventional example.

As is clear from FIG. 3, in the structure of the present invention,
The size of the barrier at the contact interface between the gate electrode 19 and the region 15 of the AIGaz-xAs layer is increased compared to the conventional one,
Since the pilting potential ■bi increases, the leakage current flowing from the gate electrode 19 to the region 15 of the AlxGarxAs layer can be reduced, and a higher gate voltage can be set than before.

As mentioned above, increasing the Al composition ratio X of the AlxGax-xAs layer is a disadvantageous condition for lattice matching, but this can be easily resolved by selecting the increasing slope of the composition ratio X. The increase in carrier trapping due to the incorporation of oxygen can also be significantly improved by improving the MBE growth method.

Note that the source and drain electrodes may be formed on a different semiconductor surface than the gate electrode.

Furthermore, although the above explanation has taken as an example a semiconductor device using GaAs/AlGa8S, semiconductor devices can also be made using a combination of gallium antimony (GaSb) and aluminum gallium antimony (AIyGal-ysb). It is possible to construct such a GaAs/A
The present invention can be similarly applied to semiconductor devices made of materials other than lGaAs.

(gl Effects of the Invention According to the present invention, as explained above, by selecting the composition ratio of the elements of the semiconductor layer in the vicinity of the gate electrode so as to increase the pilt potential, leakage current in the gate electrode can be reduced. I can do it.

It is possible to provide a margin for the voltage applied to the gate electrode.

[Brief explanation of the drawing]

Figure 1 (al is a sectional view showing the conventional example, Figure 1 (bl is a chart showing the composition ratio X of AI in each layer), Figure 2 fal is a sectional view showing the embodiment of the present invention, Figure 2 ( bl is a chart showing the composition ratio X of AI in each layer, and Fig. 3 is a chart showing its energy band. In the figure, 1 is a GaAs substrate, 2 is a GaAs layer, 3 is a ΔIxGa]-xAs layer, and 4 is an electron Storage layer. 5 is a gate electrode, 6 is a source electrode, 7 is a drain electrode,
8 is a resistive connection region, and 11 is a GaAs substrate. 12 is a non-doped GaAs layer, 13 is an AIXGaz-
Non-doped region of xAs layer, 14 is AlxQal-XA
An electron supply region of the S layer, 15 a surface control region of the AlxGa1-xAs layer, 16 a source electrode, 17 a drain electrode, 18 a resistive connection region, 19 a gate electrode, and 20 an electron storage layer. Figure 1 (a) (1)) Figure 2 (a) (b) Figure 3

Claims (1)

[Claims] a first semiconductor layer and a second semiconductor layer having a lower electron affinity than the first semiconductor layer and containing an n-type impurity; A semiconductor device in which the current path is a two-dimensional electron layer formed by electrons that form a heterojunction with the second semiconductor layer and transition from the second semiconductor layer to the first conductor layer, the semiconductor device comprising: 1. A semiconductor device, characterized in that the composition of elements constituting the semiconductor layer is such that the building potential is high in the vicinity of the gate electrode.