JPS61147577A - Complementary semiconductor device - Google Patents

Abstract

PURPOSE:To enable to easily manufacture a complementary semiconductor device and to improve the characteristics thereof by a method wherein the complementary semiconductor device consisting of an n-channel heterojunction FET and a p-channel heterojunction FET is made into the prescribed structure. CONSTITUTION:An N-type GaAlAs layer 2 with the wide forbidden band gap, an undoped GaAs layer 3 with the narrow forbidden band gap and a large electron affinity and a P-type GaAlAs layer 4 with the wide forbidden band gap are laminated in order on a semiisulative GaAs substrate 1. The gate elec trode 6 and the input and output electrodes 7 and 8 of the p-channel heterojunc tion FET are provided on the layer 4 to control the concentration of positive holes 5 and the gate electrode 10 and the input and output electrodes 11 and 12 of the n-channel heterojunction FET are provided on the layer 4 and the layer 3, from which a part thereof is removed, to control the concentration of electrons. 9. A connection is performed on each electrode so that a comple mentary inverter circuit is constituted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a complementary semiconductor device comprising an n-channel heterojunction field effect transistor and a p-channel heterojunction field effect transistor.

[Technical background of the invention and its problems]

Heterojunction field effect transistor (heterojunction FET)
) is a field effect transistor that utilizes a two-dimensionally distributed high-mobility electron gas generated at the heterojunction interface between different types of semiconductors. A typical structure is shown in Figure 2. r,
'Ga-4-/-AI compared to the electron affinity of HAB.
Since the electron affinity of 23 is smaller, n-type Ga
The electrons in the hlA layer are 22 undoped GaAs
The '1' electrons are implanted into the GaAs layer and accumulated on the GaAB side of the heterojunction interface between GaAs and GB II to form a channel. Since the concentration of electrons is controlled by the 24 gate electrodes, the input/output electrodes, that is, the source and drain electrodes 25 provided on both sides of the gate electrode.
The current between 26° and 26° can be controlled by the voltage applied to the gate electrode.

On the other hand, FIG. 3 shows an example of a p-channel heterojunction FET that has the opposite characteristics. The difference from the n-channel heterojunction FET is that the Ga layer 23' is p-doped and holes are accumulated at the heterojunction interface.

By the way, these heterojunction FETs have a GaAs layer 22
Whether the GaAJJl layer 23 is formed above or below, transistor operation can be achieved by appropriately adjusting conditions such as film thickness and carrier doping amount. Further, a normally-on type and a normally-off type can be manufactured by appropriately selecting these conditions.

A feature of a heterojunction field effect transistor is that carriers have high mobility because the carrier supply layer is separated from the channel region in which carriers travel.

Therefore, if a complementary circuit is constructed using this, it is possible to obtain very good performance.

By the way, in general, when manufacturing a heterojunction FET, a laminated film is grown in advance by the molecular beam epitaxy (MBE) method, and then steps such as etching and electrode formation are performed. Therefore, it is very difficult to dope one part of the same wafer p-type and the other part nfi. In addition, in the n-channel heterojunction PET, the electron supply layer Ga 1-XA-txA- has X of 0.
While the FET exhibits good characteristics near 3, the p-channel heterojunction FET exhibits good characteristics in the region where X is larger. Therefore, the n-channel heterojunction FET
and p-channel heterojunction FET and QBAJ
It is desirable to vary the M concentration of the AH layer.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned difficulties and provide a complementary semiconductor device composed of an n-channel heterojunction FET and a p-channel heterojunction FgT, which is easy to manufacture and has good characteristics.

[Summary of the invention]

The outline of this invention will be explained using the drawings. FIG. 1 schematically shows the basic structure of this invention. 1 in the diagram
2 is a high-resistance semiconductor substrate such as a semi-insulating GaAg substrate, 2 is a first semiconductor with a wide bandgap such as GaA, /7 to 8, and is doped n-type;
This layer serves as an electron supply layer. 3 has a narrower band gap and higher electron affinity than the first semiconductor, for example, G
A second semiconductor, such as aAs, which is undoped or slightly put or n-type doped. 4 is the second
It is doped p-type with a third semiconductor, such as GaAm S, which has a wider bandgap than the semiconductor,
This layer serves as a hole supply layer. 5 is p-type GaAtAs
GaAa at the heterojunction interface between and undoped GaAs
The holes are accumulated on the side. 6 is a p-type gate electrode that controls the hole concentration under the gate. 7 and 8 are p
The p-type input/output electrodes are placed on both sides of the type gate electrode.
~8 forms a p-channel heterojunction FET. 9 is n-type GaAIA s and undoped GaA
These are electrons accumulated on the GaAm side of the heterojunction interface with s. 10 is an n-type gate' electrode, which is made of p-type GaA
After removing J@ and a part of the undoped GaAg, it is provided above the undoped QB s and s to control the electron concentration directly under the i-type gate.

11 and 12 are n-type input/output electrodes arranged on both sides of the n-type control electrode, and 9 to 2 are n-channel heterojunction FETs.
is formed.

These two heterojunction FETs are made of n-type GaALS, a layer, p-type QBAt, and have normally-off characteristics.
Ag layer and and-ZGaAs layer and undoped G
The thickness of the portion where the aAs layer is removed and the amount of impurity doping are adjusted.

If these heterojunction FETs are connected, for example, as shown in FIG. 1, they will operate as a complementary inverter circuit.

Although the N-channel heterojunction FET is placed on the bottom side and the P-channel heterojunction FET is placed on the top side in Figure 1, it is also possible to have a structure in which the two are upside down. In that case, a laminated film in which p-type GaA-/As is laminated, then undoped GaAs, and then n-type GaAt-kg may be used on a semi-insulating substrate.

In addition, we will also discuss the efforts being made to improve the characteristics of heterojunction FETs, such as undoped GaAAAa.
undoped GaAs and doped GaAjAa
It is also possible to insert it in between.

〔Effect of the invention〕

Next, the effects of the present invention will be explained with reference to FIG. Heterojunction FETs can only operate with a high-quality heterojunction interface and precisely controlled film thickness and doping amount for each layer, so it is generally necessary to etch or attach electrodes to a laminated film grown by molecular beam copytaxy. Therefore, silicon MOS
It is very difficult to dope a part of the same Unibar to be p-type and the other part to be n-type by diffusion or the like as in FET. The structure according to the present invention eliminates this difficulty and makes it possible to easily form an n-channel heterojunction FFJT and a p-channel heterojunction FET on a laminated film.

Well, Il-type GaAjAs (2) and p-type G (4) in the figure
Since the concentration of At in a-'JAt+ can be selected arbitrarily, p-channel heterojunction FET and n
The channel heterojunction FET exhibits the best characteristics.4(t) concentration can be selected.Generally, the barrier height of the t-key junction is different between the p-type doped layer and the n-type doped layer. The breakdown voltages in the forward and reverse directions are also different. If the structure is as shown in Figure 1, a p-channel hetero junction FgT and an n-channel hetero It is also possible to make the breakdown voltages of junction FETs the same.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG.

First, a laminated film as shown in FIG. 4 (,) was formed by molecular beam epitaxy. In the figure, 41 is a Cr-doped semi-insulating substrate, and 42 is 81-doped Ga6.7! ¥zo-s”
43 is the carrier supply layer of the n-channel het uJ combination FET, 3
A-Spacer single layer, 44 undoped GaAs, 45
is undoped Gao-5A14-sAll, a layer that serves as an etching stopper, undoped GaAs from 46 companies,
47 is undoped Ga6. , A4. , As:x-pacer layer, 48 is Be-doped p-type Gao*s''-1!
-o-sAll, p-channel heterojunction FET
This layer serves as a carrier supply layer.

Next, the p-type Ga6.5Ato, s was etched using a mixture of 0-carboxylic acid, water, and hydrogen peroxide, which was etched only in the portion that would form the n-Nayanel heterojunction FET using the following method.
A11 and undoped Ga6. After removing part of the undoped Gaps and CC4F!
Dry etching was performed using gas. This etching method selectively etches only GaAs. , Etching stopped at the As layer. Furthermore, 45 Ga (1,5A41.6As+
was removed. Next, AuGe 15001 was used as the source and drain electrodes 51 and 52 of the n-channel heterojunction FET.
and Au aoooX are evaporated, and the source drain of the p-channel heterojunction FET ``X pole 499s o,!
: L teAuZn'k 1soox ト、Au
After evaporating 3000λ, heat treatment was performed at 400°C for 5 minutes.

gate dengakure s3. Both heterojunction FETs are used as s4
In both cases, Ti, Pt, and Au were used to form a structure as shown in FIG. 4(b).

Next, 50,000 ml of StO was deposited as an insulating film, and contact holes were made on each of the source, drain, and gate electrodes, and then Ti, Pt, and Au were evaporated to conduct wiring. It has been confirmed that it works as

[Brief explanation of drawings]

FIG. 1 is a basic conceptual diagram of a semiconductor device of the present invention. l... Semi-insulating substrate, 2... n-type doped j-th semiconductor layer, 3... undoped or lightly doped second semiconductor layer, 4... p-type doped third semiconductor layer, 5...
Hole storage layer under the gate, 6... p-type gate electrode, 7.
...p-type input electrode, 8...p-type output electrode, 9...electron storage layer under the gate, 10...electron storage layer under the gate, 1no...n-type input electrode, 12 ...nm output electrode. Agent Patent Attorney Noriyuki Chika (and 1 other person) Figure 1 N Figure 2 Figure 4 (4 N

Claims (4)

[Claims] (1) A first layer that serves as an electron supply layer on a semi-insulating semiconductor substrate
an undoped or lightly doped second semiconductor layer with a narrower bandgap than the first semiconductor layer forming a channel layer, and a second semiconductor layer with a wider bandgap than the second semiconductor layer forming a hole supply layer. 3 semiconductor layers are laminated, and has a control electrode provided in a partial area on the third semiconductor layer and an input/output electrode provided on the third semiconductor layer sandwiching the control electrode. channel heterojunction FE
A portion of the third semiconductor layer and the second semiconductor layer in a region different from the region where the T and the p-channel heterojunction FET are formed is removed, and a portion of the third semiconductor layer and a portion of the second semiconductor layer are removed. It has an n-channel heterojunction FET having a control electrode and an input/output electrode provided on the second semiconductor layer with the control electrode in between, and the control electrodes of the two types of heterojunction FETs are connected to each other. the two types of heterojunction FETs form an input electrode, the output electrodes of the two types of heterojunction FETs are connected to each other to form an output electrode, and the input electrodes of the two types of heterojunction FETs form a power supply electrode. Complementary semiconductor device. (2) The first claim in which the substrate is semi-insulating GaAs, the first semiconductor layer is n-type GaAlAs, the second semiconductor layer is GaAs, and the third semiconductor layer is p-type GaAlAs.
Complementary semiconductor device as described in . (3) The substrate is semi-insulating GaAs, the first semiconductor layer is n-type GaAlAs, and the third semiconductor layer is GaAs and GaAlA.
2. The complementary semiconductor device according to claim 1, wherein the third semiconductor layer is p-type GaAlAs. (4) A third layer that serves as a hole supply layer on the semi-insulating semiconductor substrate
an undoped or lightly doped second semiconductor layer with a narrower bandgap than the third semiconductor layer forming the channel layer, and a first semiconductor layer with a wider bandgap than the second semiconductor layer forming the electron supply layer. an n-channel, which is formed by laminating semiconductor layers, and has a control electrode provided in a partial region on the first semiconductor layer, and an input/output electrode provided on the first semiconductor layer sandwiching the control electrode. heterojunction FE
T and a portion of the first semiconductor layer and the second semiconductor layer in a region different from the region where the n-channel heterojunction FET is formed, and A p-channel heterojunction FET has a control electrode and an input/output electrode provided on the second semiconductor layer sandwiching the control electrode, and the control electrodes of the two types of heterojunction FETs are connected to each other. The output electrodes of the two types of heterojunction FETs are connected to each other to form an output electrode, and the input electrodes of the two types of heterojunction FETs form a power supply electrode. Complementary semiconductor device.