JPS6242569A - Field effect transistor - Google Patents

Field effect transistor

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Publication number
JPS6242569A
JPS6242569A JP18219885A JP18219885A JPS6242569A JP S6242569 A JPS6242569 A JP S6242569A JP 18219885 A JP18219885 A JP 18219885A JP 18219885 A JP18219885 A JP 18219885A JP S6242569 A JPS6242569 A JP S6242569A
Authority
JP
Japan
Prior art keywords
layer
type
layers
channel
sqw
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18219885A
Other languages
Japanese (ja)
Other versions
JPH0328065B2 (en
Inventor
Yasumi Hikosaka
康己 彦坂
Yasutaka Hirachi
康剛 平地
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18219885A priority Critical patent/JPS6242569A/en
Priority to DE86401845T priority patent/DE3689433T2/en
Priority to EP86401845A priority patent/EP0214047B1/en
Publication of JPS6242569A publication Critical patent/JPS6242569A/en
Priority to US07/593,502 priority patent/US5023674A/en
Publication of JPH0328065B2 publication Critical patent/JPH0328065B2/ja
Granted legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To reduce a short channel effect significantly by a method wherein a doped layer is provided in a single quantum well to be utilized as a channel and the carriers are confined by the hetero junctions of the single quantum well to have two-dimensional mobility. CONSTITUTION:An I-type AlGaAs layer 2, a single quantum well SQW, an I-type AlGaAs layer 6 and an I-type GaAs layer 7 are laminated on a semi- insulating GaAs substrate 1 wherein molar (x) ratios of Al in the layers 2 and 6 are selected to be 0.2-0.3. The SQW consists of an I-type GaAs layer 3, an N-type GaAs layer 4 and an I-type GaAs layer 5. The N-type layer 4 is formed by providing a layer of Se atoms of the concentration of 10<19>cm<-3> or higher or a doped layer of the concentration of about 10<18>cm<-3> between the two I-type layers 3 and 5 and the two I-type layers 3 and 5 protect the I-type layers 2 and 6 from impurity diffusion. N<+> type source and drain layers 8 and 9 are formed to complete an FET. With this constitution, as the doping concentration of the channel is high and, moreover, electrons are confined by the hetero junctions of the SQW, a narrow channel can be obtained and a short channel effect can be reduced significantly.

Description

【発明の詳細な説明】 〔概要〕 電界効果型トランジスタにおけるチャネル構造として、
単一量子井戸(SQW)を持つ素子であって、その井戸
内のドーピングした層により形成されるチャネルをSQ
Wのへテロ接合により2次元性をもたせるようにする。
[Detailed Description of the Invention] [Summary] As a channel structure in a field effect transistor,
A device with a single quantum well (SQW), in which a channel formed by a doped layer within the well is called SQ
Two-dimensionality is provided by the W heterojunction.

それにより、短チヤネル効果を低減、素子特性の線形性
改良、サブスレッショルド特性改良及び閾値の温度によ
る変動減少を図る。
Thereby, short channel effects are reduced, linearity of device characteristics is improved, subthreshold characteristics are improved, and fluctuations in threshold values due to temperature are reduced.

〔産業上の利用分野〕[Industrial application field]

本発明は、電界効果型トランジスタに係り、特に単一量
子井戸(SQW)をチャネル構造として備え、該井戸内
に形成されるチャネルにSQWのへテロ接合により2次
元性を持たせた素子に関する。
The present invention relates to a field effect transistor, and more particularly to an element having a single quantum well (SQW) as a channel structure, and a channel formed in the well having two-dimensionality due to a heterojunction of the SQW.

〔従来の技術〕[Conventional technology]

従来、高い相互コンダクタンス(!I1.n)、短チャ
ネル効果の低減等電界効果型トランジスタの特性改善が
種々試みられている。
Conventionally, various attempts have been made to improve the characteristics of field effect transistors, such as increasing mutual conductance (!I1.n) and reducing short channel effects.

第3図に、従来のGaAsMESFETを示す。図にお
いて、31は半絶縁性GaAs基板、32はn−GaA
s層、33.34はソース、ドレインのコンタクトのた
めのn+層、36.37はソース、ドレイン電極、35
はゲート電極である。ゲート電極35にバイアス電圧を
印加することにより延びる空乏層38でチャネルを制御
することによりFET動作を行なうが、その際、チャネ
ル長が短くしたとき第5図に示す短チヤネル効果が問題
になる。第5図に示すように、チャネル長が1μm程度
乃至それ以下になると、図のように、電界効果型トラン
ジスタの閾値vthが変動する。この変動は、チャネル
の活性層の不純物濃度Nが大な程少ない。そのため、従
来、短チヤネル効果の低減を図ることから活性層の高ド
ープ化がなされている。また、活性層の高ドープ化を行
なうと、第4図にエネルギ・ハンドを示すように、空乏
層41が薄くなり変調するキャリア42の数(単位ゲー
トバイアス変化に対して誘起できるチャージの量)が大
きくなり9.を向上できることになる。
FIG. 3 shows a conventional GaAs MESFET. In the figure, 31 is a semi-insulating GaAs substrate, 32 is an n-GaA substrate.
s layer, 33.34 is n+ layer for source and drain contacts, 36.37 is source and drain electrode, 35
is the gate electrode. FET operation is performed by controlling the channel with the depletion layer 38 extending by applying a bias voltage to the gate electrode 35, but in this case, when the channel length is shortened, the short channel effect shown in FIG. 5 becomes a problem. As shown in FIG. 5, when the channel length becomes about 1 μm or less, the threshold value vth of the field effect transistor changes as shown in the figure. This variation becomes much smaller as the impurity concentration N of the active layer of the channel decreases. Therefore, conventionally, the active layer has been highly doped in order to reduce the short channel effect. Furthermore, when the active layer is highly doped, the depletion layer 41 becomes thinner as shown in the energy hand in FIG. becomes larger9. This means that you can improve your performance.

〔発明が解決しようとする問題点〕 ところが、なお従来の素子においては、活性層の高ドー
プ化に伴う素子耐圧の低下、或は移動度の低下等の問題
がある。本発明はこれらの問題を解決して、優れた特性
の素子を提供しようとするものである。
[Problems to be Solved by the Invention] However, conventional devices still have problems such as a decrease in device breakdown voltage or a decrease in mobility due to highly doped active layers. The present invention aims to solve these problems and provide an element with excellent characteristics.

〔問題点を解決するための手段〕[Means for solving problems]

本発明においては、単一量子井戸(SQW)内にドーピ
ングした層を形成して該量子井戸層をチャネルとして利
用し、該チャネルを単一量子井戸(SQW)のへテロ接
合により2次元性をもたせるようにしている。
In the present invention, a doped layer is formed in a single quantum well (SQW), the quantum well layer is used as a channel, and the channel is made two-dimensional by a heterojunction of the single quantum well (SQW). I try to let it stand.

第2図の本発明の実施例の素子のエネルギ・バンド図を
採って本発明を説明すると、図において1−AI!Ga
As  (6)、1−AI!GaAs  (2)の間に
単一量子井戸(SQW)が形成されている。該単一量子
井戸(SQW)内にはブレーナ・ドープ又は高ドープし
た層dを形成してあり、この層より供給される電子ガス
eをヘテロ接合により閉じ込めて2次元性を持たせてい
る。単一量子井戸(SQW)の幅としては2次元性を持
たせるために100人程成長内が望ましい。
The present invention will be explained using the energy band diagram of the device according to the embodiment of the present invention shown in FIG. 2. In the figure, 1-AI! Ga
As (6), 1-AI! A single quantum well (SQW) is formed between GaAs (2). A Brehner-doped or highly doped layer d is formed in the single quantum well (SQW), and the electron gas e supplied from this layer is confined by a heterojunction to give it two-dimensionality. The width of the single quantum well (SQW) is preferably within about 100 layers in order to provide two-dimensionality.

〔作用〕[Effect]

上記発明構成によれば、チャネルのドーピング濃度が高
い上、更にSQWのへテロ接合で電子を閉じ込めるので
狭いチャネルとなり、従来の前記改良されたMESFE
Tよりも短チヤネル効果が防止でき、著しい短チヤネル
効果の低減が可能になる。
According to the above-mentioned structure of the invention, the doping concentration of the channel is high, and electrons are further confined by the SQW heterojunction, resulting in a narrow channel.
The short channel effect can be prevented more than T, and the short channel effect can be significantly reduced.

また、下側の1−AItGaAs  (2)とのへテロ
接合の比較的高い障壁により電子系が閉じ込められるた
め、ピンチ・オフ近傍でもサブスレッショルドの特性が
非常に良好になる。これに対して、従来のMESFET
ではホモ接合であるり障壁が低く、第6図に示すように
、ゲート電圧Vgsとドレイン電流1dの特性図におい
てbのようにならずaに示すように閉りが悪く、サブス
レッショルドが生ずることになる。
Furthermore, since the electronic system is confined by the relatively high barrier of the heterojunction with the lower 1-AItGaAs (2), the subthreshold characteristics are very good even in the vicinity of pinch-off. In contrast, conventional MESFET
In this case, it is a homojunction or has a low barrier, and as shown in Fig. 6, in the characteristic diagram of gate voltage Vgs and drain current 1d, it does not close as shown in b but as shown in a, and a subthreshold occurs. become.

また、同様な理由および、ゲート容量が一定であること
により、素子特性の線形性が良好になりGaAsであり
、ここからチャネルの電子が供給されるので温度による
電子供給量の変動が少なく、闇値の温度に対する変動が
少なくなる。
In addition, for the same reason and because the gate capacitance is constant, the linearity of the device characteristics is good, and the channel electrons are supplied from GaAs, so there is little variation in the amount of electrons supplied due to temperature, and the The fluctuation of the value with respect to temperature is reduced.

これに対して、従来のHEMT (高電子移動度トラン
ジスタ)においては、ドナレベルが深くかつDXセンタ
ーを含むAlGaAsを電子供給層としているので、温
度により電子供給量が変り易く闇値の温度による変化が
大きい。
On the other hand, in conventional HEMTs (high electron mobility transistors), the electron supply layer is AlGaAs with a deep donor level and a DX center, so the amount of electron supply changes easily depending on the temperature, and the dark value changes with temperature. big.

〔実施例〕〔Example〕

第1図に本発明の実施例の素子の要部を示している。図
において、半絶縁性(Sr)C,aAs基板1上に、そ
れぞれ非ドープの1−A7!GaAs層2.単一量子井
戸(SQW) 、1−AlGaAs6.1−GaAs7
の各層が形成しである。1−AIGaAs層2,6のA
jl!のモル比Xは0゜2〜1. 0であり、本例では
0.2〜0.3とする。
FIG. 1 shows the main parts of a device according to an embodiment of the present invention. In the figure, each undoped 1-A7! on a semi-insulating (Sr)C, aAs substrate 1! GaAs layer 2. Single quantum well (SQW), 1-AlGaAs6.1-GaAs7
Each layer is formed. 1-A of AIGaAs layers 2 and 6
jl! The molar ratio X is 0°2 to 1. In this example, it is set to 0.2 to 0.3.

単一量子井戸(SQW)層は1−GaAs3゜n−Ga
As4及び1−GaAs5から形成している。単一量子
井戸(SQW)のドーピング層の4の層はプレーナ・ド
ープ又は高ドープとする。
Single quantum well (SQW) layer is 1-GaAs3゜n-Ga
It is formed from As4 and 1-GaAs5. The four layers of single quantum well (SQW) doping layers are planar doped or highly doped.

上記各層を以下に例示する。Examples of each of the above layers are shown below.

2.6 : 1−AlGaAs層  非ドープ、膜厚数
百人(キャリアがトンネル不可の厚さ)3.5 : 1
−GaAs層 非ドープ、膜厚数十人4:n−GaAs
層 プレーナ・ドープ(アトミック・プレーナ・ドープ:t
−GaAs層間にSt又はSe原子層を介在している。
2.6:1-AlGaAs layer, undoped, several hundred thick (thickness where carriers cannot tunnel) 3.5:1
-GaAs layer undoped, film thickness several tens of 4:n-GaAs
Layer planar dope (atomic planar dope: t
- An atomic layer of St or Se is interposed between the GaAs layers.

)の場合ドーピング濃度10I9cIII−3以上、膜
厚数十人、高ドープの場合ドーピング濃度I Q ” 
C11−3程度とする。ドーピング層のn−GaAS 
4の両側に非ドープの1−GaAs層3.5を設けてい
るのは拡散により、ドーパントがi −G a 、A 
I A 3層2.6へ拡散するのを防止するためである
。尚、3,4.5の各層から成るSQWの厚さは2次元
性を確保するため100Å以下とする。7 : 1−G
aAs層 非ドープ、膜ff数数百 上の他、第1図において、8.9はSi+のイオン注入
で形成したn+領領域1017〜10181018Cで
あり、10.11はソース、ドレイン電極(AuGe/
Au)、12はゲート電極(AN)である。
), the doping concentration is 10I9cIII-3 or more, the film thickness is several tens of layers, and the doping concentration is I Q ” in the case of high doping.
It should be about C11-3. Doping layer n-GaAS
The undoped 1-GaAs layer 3.5 is provided on both sides of 4 because the dopant is diffused into i-Ga, A
This is to prevent diffusion into the I A 3 layer 2.6. Incidentally, the thickness of the SQW consisting of the 3rd and 4.5th layers is 100 Å or less in order to ensure two-dimensionality. 7: 1-G
In addition to several hundreds of aAs layers, undoped, and over several hundred films, 8.9 in FIG.
12 is a gate electrode (AN).

〔発明の効果〕〔Effect of the invention〕

以上の説明から明らかなように、本発明によれば以下の
効果が得られる。
As is clear from the above description, the following effects can be obtained according to the present invention.

■上記発明構成によれば、チャネルのドーピング濃度が
高い上、更にSQWのへテロ接合で電子を閉じ込めるの
で狭いチャネルとなり、従来の前記改良されたME S
 F ETよりも短チヤネル効果が防止でき、著しく短
チヤネル効果を低減することが可能になる。
■According to the above-mentioned structure of the invention, not only the doping concentration of the channel is high, but also the electrons are confined by the SQW heterojunction, resulting in a narrow channel, which is different from the conventional improved ME S
The short channel effect can be prevented more than the FET, and the short channel effect can be significantly reduced.

■下側のへテロ接合の比較的高い障壁により電子系が閉
じ込められるため、ピンチ・オフ近傍でもサブスレッシ
ョルドの特性が非常に良好になる。
■Since the electronic system is confined by the relatively high barrier of the lower heterojunction, the subthreshold characteristics are very good even near pinch-off.

■同様な理由、および、ゲート容量が一定であることに
より、素子特性の線形性が良好になり、等91化を図る
ことができる。
(2) For the same reason and because the gate capacitance is constant, the linearity of the device characteristics becomes good and it is possible to achieve equalization.

■ドーピング層が比較的にドナーレベルが浅いGaAs
等であり、ここからチャネルの電子が供給されるので温
度による電子供給量の変動が少なく、闇値の温度に対す
る変動が少なくなる。
■GaAs doping layer with relatively shallow donor level
etc., and since the channel electrons are supplied from here, there is little variation in the amount of electron supply due to temperature, and the variation of the dark value with respect to temperature is reduced.

これに対して、従来のHEMT (高電子移動度トラン
ジスタ)においては、ドナレベルが深いAlGaAsを
電子供給層としているので、温度により電子供給量が変
り易く闇値の温度による変化が大きい。
On the other hand, in a conventional HEMT (high electron mobility transistor), the electron supply layer is made of AlGaAs with a deep donor level, so the amount of electron supply changes easily depending on the temperature, and the dark value changes greatly depending on the temperature.

■チャネルが2次元性を持っていること、及び不純物の
ドープがチャネルを構成する単一量子井戸(SQW)の
一部に限られることから、キャリアの移動度が従来のM
ESFETなどより向上する。
■Since the channel has two-dimensionality and impurity doping is limited to a part of the single quantum well (SQW) that constitutes the channel, carrier mobility is lower than that of conventional M
Better than ESFET etc.

■ゲート電極は1−GaAs層等の高抵抗層上社形成で
きるので、耐圧の劣化がない。
(2) Since the gate electrode can be formed on top of a high resistance layer such as a 1-GaAs layer, there is no deterioration in breakdown voltage.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例の要部断面図、第2図は本発明
の実施例のエネルギ・バンド図、第3図は従来のMES
FETの概要を示す断面図、第4図は従来のME S 
F ETのエネルギ・バンド図、第5図は短チヤネル効
果の説明図、第6図はサブスレッショルドを示す図であ
る。 主な符号 1・・・半絶縁性(Sl)GaAs基板2 ・−・1−
AlGaAs層 3 ・・−1−Qa、6.s層 4−・・n−GaAs層 5・・・1−GaA3層 6・・・1−GaAlAs層 7 ・−−1−GaAs層 8.9・・・n+領域 ]、0.11・・・ソース、ドレイン電極12・・・ゲ
ート電極
Fig. 1 is a sectional view of the main part of the embodiment of the present invention, Fig. 2 is an energy band diagram of the embodiment of the present invention, and Fig. 3 is a conventional MES.
A cross-sectional view showing the outline of the FET, Figure 4 is a conventional ME S
The energy band diagram of the FET, FIG. 5 is an explanatory diagram of the short channel effect, and FIG. 6 is a diagram showing the subthreshold. Main code 1... Semi-insulating (Sl) GaAs substrate 2 ・-・1-
AlGaAs layer 3...-1-Qa, 6. s layer 4-...n-GaAs layer 5...1-GaA3 layer 6...1-GaAlAs layer 7 .--1-GaAs layer 8.9...n+ region], 0.11... Source, drain electrode 12...gate electrode

Claims (1)

【特許請求の範囲】 1 半導体基板上に第1及び第2の半導体層と、該両半
導体層間に禁止帯幅がこれより狭く単一量子井戸(SQ
W)を形成する第3の半導体層を備え、該第3の半導体
層内にドーピング層を形成し、該単一量子井戸(SQW
)をチャネルとして用いたことを特徴とする電界効果型
トランジスタ。 2 前記半導体基板が半絶縁性GaAsでなり、第1及
び第2の半導体層がAlGaAsでなり、第3の半導体
層がGaAsであって、前記ドーピング層はプレーナ・
ドープ又は高ドープ層であってその両側に非ドープのG
aAs層が介在していることを特徴とする特許請求の範
囲第1項記載の電界効果型トランジスタ。
[Claims] 1. First and second semiconductor layers on a semiconductor substrate, and a single quantum well (SQ) having a narrower band gap between the two semiconductor layers.
W), a doping layer is formed in the third semiconductor layer, and a doping layer is formed in the third semiconductor layer, and the single quantum well (SQW)
) is used as a channel. 2. The semiconductor substrate is made of semi-insulating GaAs, the first and second semiconductor layers are made of AlGaAs, the third semiconductor layer is made of GaAs, and the doped layer is a planar layer.
Doped or highly doped layer with undoped G on both sides
The field effect transistor according to claim 1, characterized in that an aAs layer is interposed therebetween.
JP18219885A 1985-08-20 1985-08-20 Field effect transistor Granted JPS6242569A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP18219885A JPS6242569A (en) 1985-08-20 1985-08-20 Field effect transistor
DE86401845T DE3689433T2 (en) 1985-08-20 1986-08-20 Field effect transistor.
EP86401845A EP0214047B1 (en) 1985-08-20 1986-08-20 Field effect transistor
US07/593,502 US5023674A (en) 1985-08-20 1990-10-04 Field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18219885A JPS6242569A (en) 1985-08-20 1985-08-20 Field effect transistor

Publications (2)

Publication Number Publication Date
JPS6242569A true JPS6242569A (en) 1987-02-24
JPH0328065B2 JPH0328065B2 (en) 1991-04-17

Family

ID=16114063

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18219885A Granted JPS6242569A (en) 1985-08-20 1985-08-20 Field effect transistor

Country Status (1)

Country Link
JP (1) JPS6242569A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01268070A (en) * 1988-04-20 1989-10-25 Toshiba Corp Heterojunction type field-effect transistor
JPH021138A (en) * 1987-11-06 1990-01-05 Foerderung Der Wissenschaft Ev:G Semiconductor device
JPH02284434A (en) * 1989-04-26 1990-11-21 Nec Corp Field-effect transistor
JPH04314328A (en) * 1991-04-12 1992-11-05 Nec Corp Method of doping iii-v compound semiconductor
JPH0794758A (en) * 1991-09-12 1995-04-07 Pohang Iron & Steel Co Ltd Manufacture of delta-doped quantum well type field-effect transistor
JP2008507122A (en) * 2004-07-16 2008-03-06 ザ・ユニバーシティ・オブ・マンチェスター Self-switching memory device
JP2008535546A (en) * 2005-03-17 2008-09-04 オンテック デラウェア インク. Container with integrated module for heating or cooling the contents

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117680A (en) * 1983-11-29 1985-06-25 Nippon Telegr & Teleph Corp <Ntt> High-speed field effect transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117680A (en) * 1983-11-29 1985-06-25 Nippon Telegr & Teleph Corp <Ntt> High-speed field effect transistor

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH021138A (en) * 1987-11-06 1990-01-05 Foerderung Der Wissenschaft Ev:G Semiconductor device
JPH01268070A (en) * 1988-04-20 1989-10-25 Toshiba Corp Heterojunction type field-effect transistor
JPH02284434A (en) * 1989-04-26 1990-11-21 Nec Corp Field-effect transistor
JPH04314328A (en) * 1991-04-12 1992-11-05 Nec Corp Method of doping iii-v compound semiconductor
JPH0794758A (en) * 1991-09-12 1995-04-07 Pohang Iron & Steel Co Ltd Manufacture of delta-doped quantum well type field-effect transistor
JP2008507122A (en) * 2004-07-16 2008-03-06 ザ・ユニバーシティ・オブ・マンチェスター Self-switching memory device
JP2008535546A (en) * 2005-03-17 2008-09-04 オンテック デラウェア インク. Container with integrated module for heating or cooling the contents

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JPH0328065B2 (en) 1991-04-17

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