JP2911075B2 - Field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly to an AlInAs / GaInAs HE.
The present invention relates to a field-effect transistor having a heterojunction such as an MT (high electron mobility transistor).

[0002]

2. Description of the Related Art HEMT is known as one of field effect transistors utilizing a heterojunction. HEMT
Is an object of research and development aimed at analog and digital applications, because electrons as carriers can travel at a higher speed in a channel layer than MESFETs (metal semiconductor field effect transistors). Among them, an AlInAs / GaInAs HEMT has recently been receiving attention.

Conventional AlInAs / GaInAs HEMTs
Has a structure as shown in FIG. This AlInA
The s / GaInAs HEMT has a multi-layer growth layer 2 on the surface of a semi-insulating InP substrate 1. The multilayer growth layer 2 is:
I-type AlIn without intentionally adding impurities formed on the main surface of the InP substrate 1 by molecular beam epitaxy.
As layer 3, i-type GaInAs layer 4, and i-type AlInAs layer 5
An n-type AlInAs layer 6 to which impurities are intentionally added;
It is composed of a type AlInAs layer 7 and an n-type GaInAs layer 8.
(Each epitaxial layer 3, ..., 8 has a thickness of several nm to several hundred nm.
It is. ). A recess groove 14 is formed at the center of the n-type GaInAs layer 8, and a gate Schottky electrode 10 is formed on the i-type AlInAs layer 7 exposed at the bottom of the recess groove 14. On the n-type GaInAs layer 8 on both sides of the gate Schottky electrode 10, a source electrode 11 and a drain electrode 12 which are in ohmic contact are formed, respectively. The source electrode 11 and the drain electrode 12 are i-type AlIn
The reason why the Al-type GaInAs layer (cap layer) is provided via the n-type GaInAs layer (cap layer) 8 instead of directly on the As layer 7 is that an ohmic electrode (source electrode 11, drain electrode 12) Is difficult to form.

The above AlInAs / GaInAs HEMT is
In principle, the i-type GaInAs layer 4 and the n-type
A two-dimensional electron gas 9 generated in the surface layer of the i-type GaInAs layer 4 is controlled by the gate electrode 10 by forming a heterojunction with the type AlInAs layer (electron supply layer) 6.

[0005]

The above AlInAs / GaI
Although the nAs HEMT has many features, it has a problem that the reverse breakdown voltage between the gate and the drain is low and the source resistance is large. That is, the AlInAs / GaInAs based HEM
At T, when the n-type impurity concentration of the AlInAs layer 6 is high, a gate current flows through the n-type AlInAs layer 6. For this reason,
The gate leakage current increases, and the reverse breakdown voltage between the gate and the drain decreases. To avoid this problem, the above AlInA
On the s layer 6, a low impurity concentration i-type AlInAs layer (gate Schottky electrode forming layer) 7 having an n-type impurity concentration set to 10 ¹⁵ cm ⁻³ or less is provided. However, sufficient reverse withstand voltage between the gate and the drain has not been obtained.

The above AlInAs / GaInAs based HEM
At T, to reduce the resistance between the source and gate, n
A mold GaInAs layer (cap layer) 8 is formed. However, since the i-type AlInAs layer (gate Schottky electrode forming layer) 7 is provided, a series resistance (indicated by R1 and R2 in FIG. 3) is added to the ohmic path between the source electrode 11 and the drain electrode 12. As a result, the source resistance and the drain resistance increase. Most of the source resistance is the series resistance between the source and the gate, and the resistance R shown in FIG.
1, R2, R3. An increase in the source resistance results in a decrease in transconductance and an increase in noise figure, which is not preferable in characteristics. In an actual circuit, the source is grounded, so if the source resistance is high, the gate voltage is divided by the source resistance, and the voltage actually applied to the gate decreases. As a result, the transconductance decreases.

Hitherto, as one means for reducing the source resistance, an attempt has been made to increase the electron concentration of the two-dimensional electron gas 9. Thereby, the resistance R3 shown in FIG. 3 decreases. However, in this case, since the ionization collision or the tunnel current component between the gate and the drain where the electric field is concentrated increases, the gate leakage current increases and the reverse breakdown voltage between the gate and the drain decreases. As another means for reducing the source resistance, n-type GaIn
Attempts have been made to implant high-concentration impurities into the entire region below the As layer 8. As a result, the source resistance can be reduced, but ionization collision, surface leakage, or a tunnel current component increases on the drain side. As in the case described above, the gate leakage current increases, and the reverse breakdown voltage between the gate and the drain increases. Decrease. That is, the reverse breakdown voltage between the gate and the drain is the same as that of the n-type AlInAs
This is strongly affected by the structure of the layer (electron supply layer) 6, and the higher the impurity concentration, the lower the impurity concentration.

As described above, in the prior art, AlInAs /
The requirements for the source resistance of the GaInAs-based HEMT and the reverse breakdown voltage between the gate and the drain could not be satisfied at the same time.

It is an object of the present invention to provide a field effect transistor having a heterojunction, which can increase the gate-drain reverse breakdown voltage and reduce the source resistance.

[0010]

To achieve the above object, a field effect transistor according to the present invention comprises a multilayer growth layer having a heterojunction inside, a gate electrode provided on the multilayer growth layer, and a gate electrode. A field-effect transistor having a source electrode and a drain electrode provided on a substrate on both sides of the electrode and spaced apart from the gate electrode, wherein the multilayer growth layer comprises a source electrode and a source electrode on both sides of the gate electrode. And an uppermost layer made of n-type GaInAs extending directly below the drain electrode, and a region between the source electrode and the gate electrode in the multilayer growth layer is higher than the remaining region of the multilayer growth layer. While the impurity of the concentration is ion-implanted, the impurity is not ion-implanted in a region of the multi-layer growth layer immediately below the source electrode.

Preferably, a two-dimensional electron gas is formed near the heterojunction in the multilayer growth layer.

The multi-layer growth layer includes an electron supply layer for supplying electrons to the two-dimensional electron gas, and the layer thickness d _D and the impurity concentration n _{D of the} electron supply layer are different from each other when the high concentration impurity is an ion. _{D D} · n _D ≦ 1 ×
It is desirable to satisfy the relationship of 10 ¹² cm ^-2 .

[0013]

In the multi-layer growth layer, a region (high-concentration implantation region) between the source electrode and the gate electrode is ion-implanted with a higher concentration impurity than the remaining region of the multi-layer growth layer. The resistivity of the high-concentration injection region decreases, and the source resistance decreases. Moreover, the remaining region of the multilayer growth layer, particularly the region between the drain electrode and the gate electrode, is kept at a normal (conventionally similar) impurity concentration. Therefore, there is no increase in ionization collision, surface leak, or tunnel current component on the drain side, and an increase in gate leak current is suppressed. Therefore, the reverse breakdown voltage between the gate and the drain does not decrease. In the present invention, the drain resistance is not reduced. However, this is not very important to the performance of the device. As long as the drain resistance is used in the current saturation region of the static characteristics,
This is because it does not affect the drain current.

When a two-dimensional electron gas is formed near the hetero junction in the multilayer growth layer, a HEMT is constituted by the multilayer growth layer and each electrode.
In this HEMT, the concentration of the two-dimensional electron gas is higher in the high-concentration implantation region into which the high-concentration impurity is ion-implanted than in the remaining region. Therefore, the source resistance further decreases, and the transconductance increases. In addition,
In the region directly below the gate electrode in the multilayer growth layer, the concentration of the two-dimensional electron gas is kept at a normal (conventional) concentration, so that the reverse breakdown voltage between the gate and the drain does not decrease.

Further, the multilayer growth layer includes an electron supply layer for supplying electrons to the two-dimensional electron gas, and the layer thickness d _D and impurity concentration n _{D of the} electron supply layer excluding the high concentration injection region are different. When the relationship of d _D · n _D ≦ 1 × 10 ¹² cm ⁻² is satisfied in the region where the gate voltage and the drain voltage are reversed, the reverse breakdown voltage between the gate and the drain becomes 10 V (volt) or more. This was confirmed by the present inventors through experiments (described later).

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the field effect transistor of the present invention will be described in more detail with reference to embodiments.

FIG. 1 shows an embodiment of the present invention.
FIG. 2 shows a cross-sectional structure of a GaInAs-based HEMT, and FIG.
4 shows an InAs / GaInAs HEMT manufacturing process.
For the sake of simplicity, the same components as those shown in FIG. 3 are denoted by the same reference numerals.

As shown in FIG. 1, the HEMT is provided on a multi-layer growth layer 2 formed on a semi-insulating InP substrate 1 by molecular beam epitaxy, and on the multi-layer growth layer 2 (recess groove 14). And a source electrode 11 and a drain electrode 1 provided on both sides of the gate electrode 10 at a distance from the gate electrode 10, respectively.
Two. A high-concentration injection region 13 is provided between the source electrode 11 and the gate electrode 10.

The multilayer growth layer 2 is formed by, for example, a molecular beam epitaxial growth method. That is, the i-type AlInAs layer 3 on which the impurity is not intentionally added is formed on the InP substrate 1.
500 nm, i-type GaInAs without intentionally adding impurities
Layer 4 of 50 nm, i-type AlIn without intentionally adding impurities
The As layer 5 is 5 nm, the n-type AlInAs layer 6 doped with impurities during epitaxial growth is 10 nm, the i-type AlInAs layer 7 not intentionally doped with impurities is 250 nm, and the n-type GaInAs layer 8 doped with impurities during epitaxial growth is the most. The layers are laminated in order of 10 nm as an upper layer. The i-type GaInAs layer 4 and the i-type Al
The InAs layer 5 and the n-type AlInAs layer (electron supply layer) 6 form a heterojunction. As a result, a two-dimensional electron gas 9 is generated in the surface layer of the i-type GaInAs layer 4. The n-type AlInAs layer 6 and the n-type GaInAs layer (cap layer) 8 have an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ and 5 × 10 ¹⁸ cm ⁻³ , respectively. The n-type AlInAs layer 6 and the n-type GaInAs layer 8
The nAs composition ratios are 0.52 and 0.53, respectively.

The high-concentration injection region 13 and each electrode 1
0, 11, and 12 are formed as follows. First, FIG.
As shown in (a), a photoresist 20 is provided in a region other than a region to be the high-concentration implantation region 13. Then, as shown in FIG. 1B, ions of an n-type impurity ²⁸ Si + are implanted under the conditions of an acceleration energy of 30 keV and a dose of 1 × 10 ¹³ cm ⁻² . Subsequently, the photoresist 20 is removed, and annealing is performed at a temperature of 950 ° C. for 4 seconds to form an n-type high concentration implantation region 13. Next, as shown in FIG.
After a normal photolithography process, the source electrode 11
And a drain electrode 12 are formed. Next, as shown in FIG. 3D, a recess groove 14 reaching the i-type AlInAs layer (gate Schottky electrode forming layer) 7 is formed at the center of the surface of the multilayer growth layer 2, and a Ti groove is formed at the bottom of the recess groove 14. A gate electrode 10 of / Pt / Au having a thickness of 300 nm is formed. On the n-type GaInAs layer 8 on both sides of the gate electrode 10, AuGe /
A 150 nm thick source electrode 11 and a drain electrode 12 made of Ni / Au are formed. Note that ion implantation is also performed on the n-type GaInAs layer 8, but this has nothing to do with the essence of the present invention.

This HEMT is applied to the high-concentration implantation region 13.
Since impurities having a higher concentration than the remaining region of the multi-layer growth layer 2 are ion-implanted, the resistivity of the high-concentration implantation region 13 decreases and the source resistance decreases. As a result, FIG.
The current path C1 is increased in addition to the current path C2 shown in FIG.
It will have two current paths. That is, as compared with the conventional HEMT shown in FIG. 3 (where the resistance R1 of the current path C1 is very large, only the current path C2 is provided substantially in the direction perpendicular to the substrate 1). -The parasitic resistance between the gate electrodes can be greatly reduced. Therefore,
The source resistance can be reduced, and the transconductance can be increased. In addition, high concentration implantation region 1
3, the electron concentration increases, so that the resistance R3 can be greatly reduced, and the transconductance can be further increased. In addition, the remaining region of the multi-layer growth layer 2, especially the region between the drain electrode 12 and the gate electrode 10, is usually
The impurity concentration is kept at the same level (conventional level). Therefore, it is possible to suppress an increase in gate leak current without increasing ionization collision, surface leak, or tunnel current component on the drain side. Therefore, the reverse breakdown voltage between the gate and the drain does not decrease. Rather, n-type AlI
The reverse breakdown voltage between the gate and the drain can be improved by reducing the thickness of the nAs layer (electron supply layer) 6 to lower the concentration. Indeed, the present inventors, the thickness of n-type AlInAs layer and d _D, when the impurity concentration of n _D, film thickness and impurity concentration of the n-type AlInAs layer product d _{D-n D} is d _D & When n _D ≦ 1 × 10 ¹² cm ⁻² is satisfied, the reverse breakdown voltage between the gate and the drain is 10 V
Was confirmed to exceed.

[0022]

As is clear from the above, the field effect transistor of the present invention has a multilayer growth layer having a heterojunction inside, a gate electrode provided on the multilayer growth layer, and a gate electrode formed on both sides of the gate electrode. A field-effect transistor having a source electrode and a drain electrode provided on a substrate at a distance from the gate electrode, respectively, wherein a region between the source electrode and the gate electrode in the multi-layer growth layer (high-concentration region) In the implantation region, the impurity is implanted at a higher concentration than in the remaining region of the multi-layer growth layer, so that the source resistance can be reduced while maintaining the gate-drain reverse withstand voltage at a high level. The conductance can be increased.

When a two-dimensional electron gas is formed near the hetero junction in the multilayer growth layer, a HEMT is constituted by the multilayer growth layer and each electrode.
In this HEMT, the concentration of the two-dimensional electron gas is locally increased in the high-concentration injection region as compared with the remaining region, so that
With the gate-drain reverse withstand voltage kept high,
Further, the source resistance can be reduced, and the transconductance can be increased.

Further, the multilayer growth layer includes an electron supply layer for supplying electrons to the two-dimensional electron gas, and the layer thickness d _D and impurity concentration n _{D of the} electron supply layer excluding the high-concentration injection region. When the relationship of d _D · n _D ≦ 1 × 10 ¹² cm ⁻² is satisfied in the region where the gate and the drain are reversed, the reverse breakdown voltage between the gate and the drain can be increased to 10 V (volt) or more.

[Brief description of the drawings]

FIG. 1 is a diagram showing a cross-sectional structure of a HEMT according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a process of manufacturing the HEMT.

FIG. 3 is a diagram showing a cross-sectional structure of a conventional HEMT.

[Explanation of symbols]

 Reference Signs List 1 semi-insulating InP substrate 2 multilayer growth layer 3 i-type AlInAs layer 4 i-type GaInAs layer 5 i-type AlInAs layer 6 n-type AlInAs layer 7 i-type AlInAs layer 8 n-type GaInAs layer 9 two-dimensional electron gas 10 gate electrode 11 source Electrode 12 Drain electrode 13 n-type high-concentration implantation region 20 photoresist

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/337-21/338 H01L 27/095 H01L 27/098 H01L 29/775-29/778 H01L 29 / 80-29/812

Claims (3)

(57) [Claims] 1. A multilayer growth layer having a heterojunction inside, a gate electrode provided on the multilayer growth layer, and source electrodes provided on both sides of the gate electrode so as to be separated from the gate electrode, respectively. And a drain electrode on the substrate, wherein the multi-layer growth layer extends from both sides of the gate electrode directly below the source electrode and the drain electrode, respectively.
An uppermost layer made of InAs, and a region between the source electrode and the gate electrode in the multilayer growth layer is ion-implanted with a higher concentration of impurities than the remaining region of the multilayer growth layer. A field effect transistor, wherein an impurity is not ion-implanted in a region of the multilayer growth layer immediately below the source electrode. 2. The field effect transistor according to claim 1, wherein a two-dimensional electron gas is formed near the hetero junction in the multilayer growth layer. 3. The multi-layer growth layer includes an electron supply layer for supplying electrons to the two-dimensional electron gas, and the layer thickness d _D and the impurity concentration n _{D of the} electron supply layer are different from each other when the high concentration impurity is an ion. in excluding implanted in that region region, the field effect transistor according to claim 2, characterized by satisfying the _{d D · n D ≦ 1 ×} 10 12 cm -2 the relationship.