JP2861590B2 - Tunnel transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor utilizing a tunnel phenomenon which can be highly integrated, operate at high speed, and have multiple functions.

[0002]

Utilizing the tunnel phenomenon at the p ⁺ -n ⁺ junction in the Prior Art Semiconductor surface normal SiMOSFET and Ga
A tunnel transistor has been proposed as a transistor having a different operation principle from As MESFET and having a function. This device is described, for example, in Japanese Patent Application No. 3-196321 entitled "Semiconductor Device" by the present applicant. This transistor can constitute a functional circuit with a small number of elements, and enables high integration.

FIG. 3 is a schematic sectional view of a conventional tunnel transistor. 1 is a substrate, 2 is an insulating region formed on the substrate 1, 3 is a degenerated first semiconductor having one conductivity type, 4 is a non-degenerated second semiconductor, and 5 is opposite to the first semiconductor 3. 6 is an insulating layer made of a material having a wider band gap than the second semiconductor 4, 7 is a gate electrode on the insulating film, and 8 is a first semiconductor 3 A source electrode 9 forming an ohmic junction and a drain electrode 9 forming an ohmic junction with the third semiconductor 5 are shown.

In the operation of this conventional tunnel transistor, a substrate 1 is a GaAs substrate, and an insulating region 2 is an i-Al
_0.5 Ga _0.5 As, the first semiconductor 3 has n ⁺ -GaAs,
The second semiconductor 4 is thin i-GaAs, the third semiconductor 5 is P ⁺ -GaAs, and the insulating layer 6 is i-Al _0.5 Ga _0.5 A.
The case where Al is used for the gate electrode 7 and Au is used for the source electrode 8 and the drain electrode 9 will be described as an example.

When the source electrode 8 is set to the ground potential, no voltage is applied to the gate electrode 7 and a positive voltage is applied to the drain electrode 9, the first semiconductor (n ⁺ -GaAs) 3 and the third
Very thin second semiconductor (p ⁺ -GaAs) 5
Via the semiconductor (i-GaAs) 4 of FIG. In this bias direction, the drain current flows more easily than in the reverse bias. However, if the voltage is set to a voltage or less (0.7 V or less in GaAs) at which the carrier diffusion current is not remarkable, almost no current flows. When a large positive voltage is applied to the gate electrode 7, the second semiconductor (i-GaAs)
s) A high concentration of electrons is induced on the surface of 4). As a result, the second semiconductor 4 is in a degenerated state in which the electron concentration is extremely high, and becomes equivalent to n ⁺ -GaAs. Therefore, the first semiconductor (n ⁺ -GaAs) 3 and the second semiconductor (i-GaAs) 4 are in a completely conductive state. on the other hand,
The second semiconductor (i-GaAs) 4 and the third semiconductor (p ⁺
-GaAs) 5, a junction similar to that of an Ezaki diode (tunnel diode) is formed. Therefore, a large tunnel current due to the tunnel effect flows between the drain and the source to which a forward bias is applied,
A differential negative resistance appears in the current-voltage characteristics. Since the magnitude of the tunnel current depends on the concentration of electrons induced in the second semiconductor, the differential negative resistance characteristic is controlled by the voltage applied to the gate electrode 7, and the operation of the transistor having the function Is obtained.

[0006]

Although this device enables high integration, when the structure of the present invention is realized by using a compound semiconductor material or the like as shown here, the forward direction between the source and the gate is reduced. There is a problem that a bias is generated and a large amount of gate leak current flows. In order to further promote low power consumption and integration, it is desired to suppress the gate leak current.

An object of the present invention is to provide a tunnel transistor capable of suppressing a gate leak current.

[0008]

SUMMARY OF THE INVENTION A tunnel transistor of the present invention has an insulating region on a substrate, and a part of the insulating region has a degenerated first semiconductor having one conductivity type and a second non-degenerated semiconductor. Having a structure in which the semiconductor of the present invention is connected to a degenerated third semiconductor having a conductivity type opposite to that of the first semiconductor,
At least an exposed surface of the second semiconductor has a wider band gap than that of the second semiconductor and has a fourth region containing ionized impurities.
And an electrode on the fourth semiconductor.
And the third semiconductor are provided with ohmic electrodes, respectively.

[0009]

In the tunnel transistor of the present invention, even when no bias voltage is applied between the gate and the source, electrons or holes are induced on the surface of the second semiconductor,
A tunnel current flows between the source and the drain. At this time,
Since the tunnel current can be controlled by applying a reverse bias voltage between the gate and the source, the leakage current of the gate is suppressed.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing embodiments.

(First Embodiment) FIG. 1 is a schematic sectional view of a first embodiment of the present invention. 1, the same reference numerals as those in FIG. 3 denote the same components as in FIG. 3, and perform the same functions.
Reference numeral 10 denotes a fourth semiconductor having a wider band gap than the second semiconductor and containing ionized impurities.

In this embodiment, the substrate 1 is a GaAs substrate, the insulating region 2 is i-Al _0.5 Ga _0.5 As, the first semiconductor 3
N ⁺ -GaAs, the second semiconductor 4 is thin i-GaAs
s, p ⁺ -GaAs as the third semiconductor 5, and the fourth semiconductor 1
0 for n-Al _0.3 Ga _0.7 As, gate electrode 7 for Al,
Au was used for the source electrode 8 and the drain electrode 9.

In the tunnel transistor of this embodiment, since the fourth semiconductor 10 is doped with an n-type ionized impurity, the heterojunction between the fourth semiconductor 10 and the second semiconductor 4 has a modulation-doped structure. Electrons are accumulated on the second semiconductor side having a low conduction band energy. Therefore, even when no gate voltage is applied, an equivalent thin p ⁺ -n ⁺ tunnel diode structure is formed between the source and the drain, and a tunnel current (drain current) flows between the source and the drain. Therefore, the structure of this embodiment does not require a large positive gate voltage for accumulating electrons in the second semiconductor 4. Now, when a negative voltage is applied to the gate, the electron concentration stored in the second semiconductor 4 decreases,
The tunnel current between the source and the drain is reduced. Therefore, a transistor operation can be realized similarly to the conventional tunnel transistor. As described above, in the tunnel transistor of this embodiment, a large forward bias does not need to be applied between the source and the gate for transistor operation, and almost no gate leakage current flows.

Next, a method of manufacturing the tunnel transistor of this embodiment will be described.

First, on the GaAs substrate 1, a thickness of 500 nm
I-Al _0.5 Ga _0.5 As layer, i-G having a thickness of 20 nm
aAs layer, n-Al _0.3 Ga _0.7 As with a thickness of 50 nm
(N = 1 × 10 ¹⁸ cm ⁻³ ) layer was formed by MBE (Molecule).
ar Beam Epitaxy).
After the formation of the Al gate electrode 7, a high-concentration Se
Is implanted, and degenerated n ⁺ GaAs (n = 〜2 × 1
0 ¹⁹ cm ^-3 ). Further, high-concentration Be is ion-implanted into the drain region, and degenerated p ⁺ -GaAs (p =
~ 5 × 10 ¹⁹ cm ^-3 ). Finally, source and drain electrodes 8 and 9 were formed by Au vapor deposition. As a result of comparing this device with a conventional device, the source-drain voltage was -1 V and the drain current density was 0.1 mA / c.
The gate leakage current density at the time of m ² was about 2 A / cm ² in the conventional device, but was 1 μA / cm ^{2 in} the device of the present embodiment, and it was found that the reduction was about six orders of magnitude. Was.

(Second Embodiment) FIG. 2 is a schematic sectional view showing a second embodiment of the present invention. In FIG. 2, the same reference numerals as those in FIGS. 1 and 3 denote the same components as those in FIGS. 1 and 3 and perform the same functions. 11 is the fourth semiconductor 10
And an insulating layer located between the gate electrode 7.

[0017] In tunnel transistor of this embodiment, using the i-Al _0.5 Ga _0.5 As the insulating layer 11, and the other using the same material as that of the first embodiment.

The operation principle is almost the same as that of the first embodiment, and the gate leakage current during the operation of the transistor can be suppressed. In this embodiment, an i-Al _0.5 Ga _0.5 As insulating layer 11 is provided between the fourth semiconductor 10 and the gate electrode 7.
Is inserted, the gate leakage current is further suppressed as compared with the first embodiment, and the applied voltage range of the gate voltage is widened.

Using the same manufacturing method and material as those of the first embodiment, n-Al
_0.3 Ga _0.7 As (n = 2 × 10 ¹⁸ cm ⁻³ , 20 nm)
As a result of manufacturing a tunnel transistor having a structure of / i-Al _0.5 Ga _0.5 As (30 nm), the applicable range of the gate voltage at which a gate current hardly flows increased by about 1 V.

In the above embodiments of the present invention, only the n-type and the p-type third semiconductors are shown as the first and fourth semiconductors. Can obtain the same operation. Further, the material to be used may be Ge / S other than GaAs / AlGaAs.
iGe, SiGe / Si, Si / GaP, Ge / GaAs
s, InGaAs / InAlAs, GaSb / AlGa
It is clear that the present invention can be applied to other semiconductor combinations such as Sb, InAs / AlGaSb.

[0021]

According to the tunnel transistor having the function of the present invention, an ultra-high integrated circuit with low power consumption can be realized.

[Brief description of the drawings]

FIG. 1 is a structural diagram showing a first embodiment of the present invention.

FIG. 2 is a structural diagram showing a second embodiment of the present invention.

FIG. 3 is a structural diagram of a conventional tunnel transistor.

[Explanation of symbols]

 Reference Signs List 1 substrate 2 insulating region 3 first semiconductor 4 second semiconductor 5 third semiconductor 6 insulating layer 7 gate electrode 8 source electrode 9 drain electrode 10 fourth semiconductor 11 insulating film

──────────────────────────────────────────────────続 き Continued on the front page (58) Investigated field (Int.Cl. ⁶ , DB name) H01L 21/337-21/338 H01L 27/095-27/098 H01L 29/775-29/778 H01L 29 / 80-29/812

Claims (2)

(57) [Claims] An insulating region is formed on a substrate, and a part of the insulating region has a degenerated first semiconductor having one conductivity type, a non-degenerated second semiconductor, and an opposite to the first semiconductor. A fourth semiconductor having a structure in which a degenerated third semiconductor having a conductivity type is connected to the fourth semiconductor, wherein at least an exposed surface of the second semiconductor has a wider band gap than the second semiconductor and contains an ionized impurity; A tunnel transistor having a semiconductor and an electrode on the fourth semiconductor, wherein the first semiconductor and the third semiconductor are provided with ohmic electrodes, respectively. 2. The transistor according to claim 1, wherein an insulating layer is inserted on an electrode side on the fourth semiconductor.