JPS58162070A - Field effect transistor - Google Patents
Field effect transistorInfo
- Publication number
- JPS58162070A JPS58162070A JP4496982A JP4496982A JPS58162070A JP S58162070 A JPS58162070 A JP S58162070A JP 4496982 A JP4496982 A JP 4496982A JP 4496982 A JP4496982 A JP 4496982A JP S58162070 A JPS58162070 A JP S58162070A
- Authority
- JP
- Japan
- Prior art keywords
- type
- effect transistor
- field effect
- layer
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 22
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 17
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 7
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 claims abstract 3
- 229910052751 metal Inorganic materials 0.000 abstract description 4
- 239000002184 metal Substances 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 2
- 229910052697 platinum Inorganic materials 0.000 abstract description 2
- 229910052721 tungsten Inorganic materials 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 235000009508 confectionery Nutrition 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/432—Heterojunction gate for field effect devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、電界効果トランジスタに関するものであり、
特にｐ型ガリウム砒素基板の表面にｎ型反転層を有する
電界効果トランジスタを提案するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a field effect transistor,
In particular, we propose a field effect transistor having an n-type inversion layer on the surface of a p-type gallium arsenide substrate.
従来、ｎ型ガリウム砒素の電子移動度がシリコンに比べ
て約６倍大きいという材料的特長に着眼し、数多くの電
界効果トランジスタの研究開発がなされてきた。ところ
が、そのほとんどは第１図に示すようなショットキー、
ゲート構造の電界効果トランジスタである。すなわち、
半絶縁性ガリウム砒素基板１１にｎ型活性層１２（チャ
ネル領域）及び高濃度！ｌＩ型層１３をイオン注入法を
用いて形成した後、ｎ型活性層１２上にショットキ接合
電極１４１だ高濃度ｎ型層１３の上にソース・ドレイン
電極１６を形成して、作製される電界効果トランジスタ
である。BACKGROUND ART In the past, research and development of a large number of field effect transistors has focused on the material feature of n-type gallium arsenide, which is that the electron mobility is about six times higher than that of silicon. However, most of them are Schottky, as shown in Figure 1.
This is a field effect transistor with a gate structure. That is,
N-type active layer 12 (channel region) and high concentration on semi-insulating gallium arsenide substrate 11! After forming the II type layer 13 using the ion implantation method, a Schottky junction electrode 141 is formed on the n-type active layer 12 and a source/drain electrode 16 is formed on the heavily doped n-type layer 13 to reduce the electric field created. It is an effect transistor.
このような従来の電界効果トランジスタは、ゲート電極
とソース領域は電気的に分離せねばならないためソース
抵抗が大きい。また、この電界効果トランジスタのピン
チオフ電圧はｎ型活性層の不純物濃度と厚さによって定
まるが、その制（財）には極めて高度な技術を必要とす
る。さらに、エンハンスメント型の特性を得ようとする
場合には、活性層の厚さは６０人程度の制御性が要求さ
れる。Such conventional field effect transistors have a large source resistance because the gate electrode and the source region must be electrically separated. Furthermore, the pinch-off voltage of this field effect transistor is determined by the impurity concentration and thickness of the n-type active layer, and controlling it requires extremely sophisticated technology. Furthermore, if enhancement-type characteristics are to be obtained, the thickness of the active layer must be controlled to a degree of about 60 degrees.
本発明は、このような大きいソース抵抗が得られ、エン
ハンスメント型電界効果トランジスタを得るための活性
層の制（財）の問題を解決できるガリウム砒素を用いた
電界効果トランジスタを提供するものである。The present invention provides a field effect transistor using gallium arsenide that can obtain such a large source resistance and solve the problem of controlling the active layer to obtain an enhancement type field effect transistor.
以下に、本発明の一実施例における電界効果トランジス
タについて述べる。まず、本発明の一実施例だおける電
界効果トランジスタの構造断面図を第２図として示す。A field effect transistor according to an embodiment of the present invention will be described below. First, FIG. 2 shows a cross-sectional view of the structure of a field effect transistor according to an embodiment of the present invention.
高濃度ｐ型基板２１（不純物濃は１０１８〜１０１９α
−６）上に分子線エピタキシャル（ＭＢＥ）法を用いて
、低濃度ｐ型ＧａＡｓ層２５をエピタキシャル成長する
。このｐ型ＧａＡｓ層２５の不純物濃度は１０〜１０
ｃＴｎ で厚さは１μｍである。次に連続してＭＢＥ
法によりｎ型ガリウム−７ルミ砒素層（ｎ−Ａｐ、ｘＧ
ａｌ 、Ａｓ）２２をエピタキシャル成長する。このｎ
型ガリウムｐアルミ砒素層２２の不純物濃度と厚さはそ
れぞれ１０〜５×１ｏ ｒＩｎ 、０．１μｍである。High concentration p-type substrate 21 (impurity concentration is 1018 to 1019α
-6) A low concentration p-type GaAs layer 25 is epitaxially grown thereon using the molecular beam epitaxial (MBE) method. The impurity concentration of this p-type GaAs layer 25 is 10 to 10
It is made of cTn and has a thickness of 1 μm. Then consecutive MBE
An n-type gallium-7 lumi arsenide layer (n-Ap, xG
al, As) 22 is epitaxially grown. This n
The impurity concentration and thickness of the gallium p-aluminum arsenide layer 22 are 10 to 5×1 orIn and 0.1 μm, respectively.
また、ｎ Ａ ｌ ｘＧ ａ １ｘ Ａ ｓにおけるＡ
ＱとＧａの混晶比！は０．２〜ｏ３である。次に、ゲー
ト電極となる金属として、例えばＷ、Ｐｔ、Ａ、Ｑ等を
蒸着し、通常のフォト・レジスト法を甲いてゲート部だ
けを残して電極金属２３及びｎ −ＡＱ 、Ｇａ １．
−ｘＡｓＡｓ層をエツチング形成する。この後、ゲート
電極ヲマスクにして、Ｓｔのイオン注入によって高濃度
ｎ型領域２４を形成する。この高濃度ｎ型領域２４の不
純物濃度は１０１８〜１０” ｃｍ−’で深さは０．２
〜０．６μｍ である。Also, A in n A l x G a 1x A s
Mixed crystal ratio of Q and Ga! is 0.2 to o3. Next, for example, W, Pt, A, Q, etc., are vapor-deposited as metals that will become the gate electrodes, and the electrode metal 23, n-AQ, Ga 1.
-xAsAs layer is etched. Thereafter, using the gate electrode as a mask, a heavily doped n-type region 24 is formed by ion implantation of St. The impurity concentration of this high concentration n-type region 24 is 1018 to 10"cm-' and the depth is 0.2".
~0.6 μm.
以上のような工程により、高濃度ｎ型飴域２４をソース
・ドレインとするエンハンスメント型のＧ ａ Ａ ｓ
電界効果トランジスタを実現することができる。以上の
製造工程および第２図の構造かられかるように、本発明
の電界効果トランジスタは通常のシリコンｎチャンネル
ＭＯ８ＦＥＴと類似している。Through the above steps, an enhancement type GaAs using the high concentration n-type candy region 24 as the source and drain is produced.
A field effect transistor can be realized. As can be seen from the above manufacturing process and the structure shown in FIG. 2, the field effect transistor of the present invention is similar to a conventional silicon n-channel MO8FET.
次に上記構成のゲート領域の各接合部におけるポテンシ
ャル分布を第３図に示す。ｎ−ＡＱ工Ｇａ１−ｘＡ３と
ｐ−ＧａＡｓ の接合部は各々の材料に対する電子親和
力の差によって第３図のようになり、ゲート電位が零（
Ｖｇ＝Ｏ） の時、電子に対する価電子帯ｖｃ、導電帯
Ｅｖ等のポテンシャルは第３図の実線のようになり、ｐ
−ＧａＡｓと ｎ−Ａｆｌ、Ｇａ１−ｘＡｓとの電子親
和力の差によって生ずるポテンシャルの谷の部分が７工
ルミ準位Ｅｆ より上にある。この時ｐ −Ｇ ａ Ａ
ｓ 側に溜る電子は少なく、正孔と再結合するためド
レイン・ソース間に電流は流れない。次に、ゲート電位
を正にバイアス（Ｖｇ）ｏ）すると価電子帯Ｅｖが破線
で示すように下がるとともに、ｐ−ＧａＡｓ 側に生ず
る電子の数が増加し、ドレイン・ソース間に電流が流れ
る。Next, FIG. 3 shows the potential distribution at each junction of the gate region having the above structure. The junction between n-AQ Ga1-xA3 and p-GaAs is as shown in Figure 3 due to the difference in electron affinity for each material, and the gate potential is zero (
Vg=O), the potentials of the valence band vc, conduction band Ev, etc. for electrons are as shown by the solid line in Figure 3, and p
The valley of the potential caused by the difference in electron affinity between -GaAs, n-Afl, and Ga1-xAs is above the 7-Eluminum level Ef. At this time p −G a A
Few electrons accumulate on the s side and recombine with holes, so no current flows between the drain and source. Next, when the gate potential is positively biased (Vg)o), the valence band Ev decreases as shown by the broken line, the number of electrons generated on the p-GaAs side increases, and a current flows between the drain and source.
以上に述べたように本発明の電界効果トランジスタの構
造を甲いると、ヱンノ１ンスメント型でかつソースおよ
びドレイン領域がゲート佃域に対してセルフ・アライン
構造で製作できるためソース抵抗を極めて小さくするこ
とができる。したがって、従来のＧ ａ Ａ ｔｒを用
いた電界効果トランジスタと比較して、本発明の電界効
果トランジスタは集積度が高くなるとともに、さらに高
周波動作が可能となる。As described above, the structure of the field-effect transistor of the present invention is of an awareness type, and the source and drain regions can be manufactured in a self-aligned structure with respect to the gate region, making the source resistance extremely small. be able to. Therefore, compared to the conventional field effect transistor using G a A tr, the field effect transistor of the present invention has a higher degree of integration and can operate at a higher frequency.
第１図は従来のＧ ａ Ａ ｓを馬いた電界効果トラン
ジスタの断面図、第２図は本発明の一実施例における電
界効果トランジスタの断面図、第３図は同電界効果トラ
ンジスタのゲート領域のポテンシャル状態を示す図であ
る。
２１・・・・・・高濃度ｐ型Ｇ ａ Ａ ｓ基板、２２
會・−・・Ｏｎ型ＡｇＧａ Ａｓ層、２３・・・・
・・ゲート電極、ｘ １−ｘ
２５・・・・・・低濃度ｐ型Ｇ ａ Ａ ｓ層。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
１２図
３
第３図FIG. 1 is a cross-sectional view of a conventional field-effect transistor using GaAs, FIG. 2 is a cross-sectional view of a field-effect transistor according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view of the gate region of the same field-effect transistor. It is a figure showing a potential state. 21...High concentration p-type GaAs substrate, 22
Meeting: On-type AgGaAs layer, 23...
...Gate electrode, x1-x25...Low concentration p-type GaAs layer. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 12 Figure 3 Figure 3
Claims (1)
れ、前記ｎ型領域の２つの間にまたがって、ｎ型ガリウ
ム・アルミニウム砒素層が形成されて、前記ｎ型ガリウ
ム・アルミニウム砒素層をゲート、前記２つのｎ型領域
をそれぞれソースおよびドレインとす、ることを特徴と
する電界効果トランジスタ。Two n-type regions are formed on the surface of the p-type gallium arsenide substrate, and an n-type gallium aluminum arsenide layer is formed spanning between the two of the n-type regions, and the n-type gallium aluminum arsenide layer is A field effect transistor characterized in that a gate and the two n-type regions serve as a source and a drain, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4496982A JPS58162070A (en) | 1982-03-19 | 1982-03-19 | Field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4496982A JPS58162070A (en) | 1982-03-19 | 1982-03-19 | Field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58162070A true JPS58162070A (en) | 1983-09-26 |
Family
ID=12706301
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4496982A Pending JPS58162070A (en) | 1982-03-19 | 1982-03-19 | Field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58162070A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60134479A (en) * | 1983-12-23 | 1985-07-17 | Hitachi Ltd | Semiconductor device |
| JPS61177782A (en) * | 1985-01-28 | 1986-08-09 | フィリップス エレクトロニクス ネムローゼ フェンノートシャップ | Semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5694780A (en) * | 1979-12-28 | 1981-07-31 | Fujitsu Ltd | Semiconductor device |
| JPS577165A (en) * | 1980-06-17 | 1982-01-14 | Fujitsu Ltd | Semiconductor device |
| JPS5773979A (en) * | 1980-10-27 | 1982-05-08 | Nec Corp | Field effect transistor |
-
1982
- 1982-03-19 JP JP4496982A patent/JPS58162070A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5694780A (en) * | 1979-12-28 | 1981-07-31 | Fujitsu Ltd | Semiconductor device |
| JPS577165A (en) * | 1980-06-17 | 1982-01-14 | Fujitsu Ltd | Semiconductor device |
| JPS5773979A (en) * | 1980-10-27 | 1982-05-08 | Nec Corp | Field effect transistor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60134479A (en) * | 1983-12-23 | 1985-07-17 | Hitachi Ltd | Semiconductor device |
| JPH0810762B2 (en) * | 1983-12-23 | 1996-01-31 | 株式会社日立製作所 | Semiconductor device |
| JPS61177782A (en) * | 1985-01-28 | 1986-08-09 | フィリップス エレクトロニクス ネムローゼ フェンノートシャップ | Semiconductor device |
| JPH07123164B2 (en) * | 1985-01-28 | 1995-12-25 | エヌ・ベー・フイリツプス・フルーイランペンフアブリケン | Semiconductor device |
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