JPH0249465A - Compound semiconductor device and manufacture thereof - Google Patents
Compound semiconductor device and manufacture thereofInfo
- Publication number
- JPH0249465A JPH0249465A JP1126438A JP12643889A JPH0249465A JP H0249465 A JPH0249465 A JP H0249465A JP 1126438 A JP1126438 A JP 1126438A JP 12643889 A JP12643889 A JP 12643889A JP H0249465 A JPH0249465 A JP H0249465A
- Authority
- JP
- Japan
- Prior art keywords
- buffer layer
- layer
- element isolation
- isolation band
- band
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- 150000001875 compounds Chemical class 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000002955 isolation Methods 0.000 claims description 126
- 239000000463 material Substances 0.000 claims description 11
- 238000003486 chemical etching Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 23
- 230000010354 integration Effects 0.000 abstract description 12
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 37
- -1 oxygen ions Chemical class 0.000 description 9
- 239000001301 oxygen Substances 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 8
- 238000001459 lithography Methods 0.000 description 7
- 238000000926 separation method Methods 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 5
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000700560 Molluscum contagiosum virus Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔目 次〕
概要
産業上の利用分野
従来の技術
発明が解決しようとする課題
課題を解決するための手段
作用
実施例
発明の効果
第３頁
第５頁
第６頁
第７頁
第８頁
第１１頁
第１１頁
第２４頁
〔概 要〕
ＧａＡｓ Ｉ Ｃなど化合物半導体集積回路の素子分離
帯の構造と形成方法に関し、
サイドゲート効果を解消させ、且つ、集積度を向上させ
ることを目的とし、
半絶縁性半導体基板にバッファ層（または、半絶縁性半
導体基板および第１バッファ層より高抵抗、または、半
導体素子の能動層とは異種導電型の第２バッファ層と第
１バッファ層と）を介して積層した能動層を有する化合
物半導体集積回路において、
印加電圧の同じ半導体素子相互の間には前記バッファ層
（または、第１バッファ層）まで達する第１の素子分離
帯を設け、且つ、印加電圧の異なる半導体素子相互の間
には前記半導体基板（または１、第２バッファ層）まで
達する第２の素子分離帯を設けた化合物半導体装置を特
徴とし、
その製造方法は、半絶縁性半導体基板に選択的にバッフ
ァＮ（または、第１バッファ層）まで達する第１の素子
分離帯と第２の素子分離帯の上部とを化学エツチングに
よって溝状に形成し、次いで、第２の素子分離帯の下部
をイオン注入によって不活性体が前記半導体基板（また
は、第２バッファ層）まで達する第２の素子分離帯を形
成する工程、または、半絶縁性半導体基板に選択的に第
２の素子分離帯の上部を化学エツチングによって溝状に
形成し、次いで、第２の素子分離帯の下部および第１の
素子分離帯をイオン注入によって不活性体が前記半導体
基板（または、第２バツフアＮ）まで達する第２の素子
分離帯およびバッファ層（または、第１バッファ層）ま
で達する第１の素子分離帯を形成する工程が含まれてな
ることを特徴とする。[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Actions Examples Effects of the Invention Page 3 Page 5 Page 6 Page 7, Page 8, Page 11, Page 11, Page 24 [Summary] Regarding the structure and formation method of element isolation bands in compound semiconductor integrated circuits such as GaAs IC, eliminating side gate effects and improving the degree of integration. A semi-insulating semiconductor substrate is provided with a buffer layer (or a semi-insulating semiconductor substrate and a second buffer layer having a higher resistance than the first buffer layer, or a second buffer layer and a second buffer layer having a conductivity type different from that of the active layer of the semiconductor element). In a compound semiconductor integrated circuit having active layers laminated via a buffer layer (1 buffer layer), a first element isolation band extending to the buffer layer (or the first buffer layer) is provided between the semiconductor elements to which the same voltage is applied. A compound semiconductor device is characterized in that a second element isolation band is provided between semiconductor elements having different applied voltages and that reaches the semiconductor substrate (or the first and second buffer layers), and the manufacturing method thereof is as follows: , selectively forming a first element isolation band reaching up to the buffer N (or the first buffer layer) and an upper part of the second element isolation band in the shape of a groove on the semi-insulating semiconductor substrate by chemical etching; A step of forming a second element isolation band in which the inert material reaches the semiconductor substrate (or the second buffer layer) by ion implantation into the lower part of the second element isolation band, or a step of selectively forming a second element isolation band in a semi-insulating semiconductor substrate. The upper part of the second element isolation band is formed into a groove shape by chemical etching, and then the inert material is formed in the semiconductor substrate (or The method is characterized in that it includes a step of forming a second element isolation band reaching up to the second buffer (N) and a first element isolation band reaching up to the buffer layer (or the first buffer layer).
本発明は化合物半導体装置とその製造方法に係り、特に
ＧａＡｓ Ｉ Ｃなど化合物半導体集積回路の素子分離
帯の構造とその形成方法に関する。The present invention relates to a compound semiconductor device and a method of manufacturing the same, and particularly to a structure of an isolation band of a compound semiconductor integrated circuit such as GaAs IC and a method of forming the same.
最近、超高速デバイスとして化合物半導体ＩＣ（集積回
路）が検討されているが、その素子分離は高集積化のた
めに特に重要な課題で、本発明はそのような化合物半導
体ＩＣの素子分離帯構造に関している。Recently, compound semiconductor ICs (integrated circuits) have been studied as ultra-high-speed devices, and element isolation is a particularly important issue for achieving high integration. It's about.
第１０図（ａ）、 （ｂ）は従来のＨＥＭＴＩ Ｃ（Ｈ
ＥＭＴ素子からなるＩＣ）の断面図を示しており、両図
に共通して記号１は半絶縁性ＧａＡｓ基板、２はｉ −
ＧａＡｓ層からなるバッファ層（Ｊｌ厚５０００人）、
３はＨ−ＡＩＧａＡｓ層からなる電子供給層（膜厚４０
０人）、４はｎ−ＧａＡｓ層からなるコンタクト層（膜
厚１０００人） 、 ５ （一部分）は二次元電子層
（２ＤＥＣ）、６はゲート電極、７，８はソース電極お
よびドレイン電極で、ＴＩ、Ｔ２．Ｔ３はＨＥＭＴ素子
を示している。なお、ここに、電子供給層３とコンタク
ト層４とは素子動作に直接関係する層であるから総称し
て能動層とも呼んでいる。Figures 10(a) and (b) show the conventional HEMTI C(H
This figure shows a cross-sectional view of an IC (IC) consisting of an EMT element, and in both figures, symbol 1 is a semi-insulating GaAs substrate, and 2 is an i-
Buffer layer consisting of GaAs layer (Jl thickness 5000 layers),
3 is an electron supply layer made of H-AIGaAs layer (thickness 40
0), 4 is a contact layer made of n-GaAs layer (thickness: 1000), 5 (part) is a two-dimensional electron layer (2DEC), 6 is a gate electrode, 7 and 8 are a source electrode and a drain electrode, TI, T2. T3 indicates a HEMT element. Note that since the electron supply layer 3 and the contact layer 4 are layers directly related to device operation, they are also collectively referred to as active layers.
且つ、第１０図（ａ）はバッファ層２まで達する素子分
離帯９が設けられた例で、第１０図（ｂ）はＧａＡｓ基
板ｌまで達する素子分離帯１０が設けられた例である。Further, FIG. 10(a) shows an example in which an element isolation band 9 reaching the buffer layer 2 is provided, and FIG. 10(b) shows an example in which an element isolation band 10 is provided reaching the GaAs substrate 1.
これらの素子分離帯はりソグラフィ技術を利用して選択
的に化学エツチングして溝状に空隙化する分離法、ある
いは、酸素イオン（０゛）を注入して不活性化（高抵抗
化）する分離法が採られている。Separation methods include selectively chemically etching these device isolation bands using lithography technology to create groove-like voids, or isolation methods in which oxygen ions (0゛) are implanted to inactivate (increase resistance). The law is being adopted.
ところが、第１０図（ａ）に示すバッファ層２まで達す
る素子分離帯９はコンタクト層４．電子供給層３、二次
元電子層５まで分離するため、一応の素子間分離の効果
があるものの、サイドゲート効果のためにデバイス特性
が安定しないと云う問題が起きる。サイドゲート効果と
は、ｎ型能動層を有する素子からなるＩＣにおいて、例
えば、第１０図（ａ）に示す素子Ｔ２がソースにＯ■の
電圧を印加して動作している時、隣接素子Ｔ１がソース
、または、ドレインに一３ｖの電圧を印加していたり、
あるいは、−３Ｖのゲート電圧を印加していたりすると
、素子Ｔ２のスレーショルド電圧ｖｔｈが変化する現象
のことである。即ち、隣接素子ＴＩがＴ２より低い電圧
で動作している時に素子Ｔ１はその影響を受けてｖｔｈ
特性が変動すると云うもので、これは品質上の大きな欠
陥になる。このサイドゲート効果は素子分離帯の深さお
よび幅に直接大きく関係するが、その原因は主に半絶縁
性ＧａＡｓ基板とバッファ層との界面にあることが知ら
れている （ＩＥＥＩＥ Ｅｌｅｃｔｒｏｎ Ｄｅｖｉ
ｃｅ Ｌｅｔｔｅｒｓ Ｖｏｌ、ＥＤＬ−８Ｎｏ、６
ｐ２８０（１９８７）参照）。However, the element isolation band 9 that reaches the buffer layer 2 shown in FIG. 10(a) has a contact layer 4. Since the electron supply layer 3 and the two-dimensional electron layer 5 are separated, there is a certain effect of isolation between elements, but there is a problem that the device characteristics are not stable due to the side gate effect. The side gate effect means that in an IC consisting of an element having an n-type active layer, for example, when the element T2 shown in FIG. is applying a voltage of -3V to the source or drain,
Alternatively, it is a phenomenon in which the threshold voltage vth of the element T2 changes when a gate voltage of -3V is applied. That is, when the adjacent element TI operates at a lower voltage than T2, the element T1 is affected by the voltage vth
This means that the characteristics fluctuate, which is a major quality defect. This side gate effect is directly related to the depth and width of the device isolation zone, but it is known that the cause is mainly at the interface between the semi-insulating GaAs substrate and the buffer layer (IEEE Electron Dev.
ce Letters Vol, EDL-8No, 6
p. 280 (1987)).
従って、素子分離帯の深さを深くして、半絶縁性ＧａＡ
ｓ基板まで達する素子分離帯を形成すれば、サイドゲー
ト効果はほぼ解消できる。第１０図（ロ）はそのＧａＡ
ｓ基板まで達する深い素子分離帯１０を設けた例を示し
ている。しかし、そのように、素子分離帯の深さを深く
すれば、その幅が拡大して、例えば、０．７μｍの深さ
にすると幅は２〜３μｍに拡がり、ＩＣの集積度を阻害
する問題が起こる。Therefore, by increasing the depth of the device isolation band, semi-insulating GaA
By forming an element isolation band that reaches the s-substrate, the side gate effect can be almost eliminated. Figure 10 (b) shows the GaA
An example is shown in which a deep element isolation band 10 reaching up to the s-substrate is provided. However, if the depth of the element isolation band is increased, its width will increase. For example, if the depth is 0.7 μm, the width will increase to 2 to 3 μm, which poses a problem that inhibits the degree of integration of ICs. happens.
本発明はこのような問題点を軽減させて、サイドゲート
効果を解消させ、且つ、集積度を向上させることを目的
とした化合物半導体装置とその製造方法を提案するもの
である。The present invention proposes a compound semiconductor device and a method for manufacturing the same, which aim to alleviate such problems, eliminate the side gate effect, and improve the degree of integration.
その課題は、第１図（ａ）に示す原理図のように、半絶
縁性半導体基板１１にその上部がチャネル層となるバッ
ファ層１２を介して積層した能動層１３を有する化合物
半導体ＩＣ（第１構造ＩＣ）において、印加電圧の同じ
半導体素子Ｔ２．Ｔ３相互間には前記バッファ層まで達
する第１の素子分離帯１９を設け、且つ、印加電圧の異
なる半導体素子ＴＩとＴ２．Ｔ３との間には前記半導体
基板まで達する第２の素子分離帯２０を設けた化合物半
導体装置の構造、
また、第１図（ｂ）に示す原理図のように、半絶縁性半
導体基板に半絶縁性半導体基板および第１バッファ層よ
り高抵抗、または、半導体素子の能動層とは異種導電型
の第２バッファ層１２″と、その上に形成され上部がチ
ャネル層となる第１バッファ層１２°とを介して積層し
た能動層１３を有する化合物半導体ＩＣ（第２構造ＩＣ
）において、印加電圧の同じ半導体素子相互の間には前
記第１バッファ層まで達する第１の素子分離帯１９を設
け、且つ、印加電圧の異なる半導体素子相互の間には前
記第２バッファ層まで達する第２の素子分離帯２５を設
けた化合物半導体装置の構造によって解決される。The problem is, as shown in the principle diagram shown in FIG. 1 structure IC), semiconductor elements T2 . A first element isolation band 19 reaching the buffer layer is provided between the semiconductor elements TI and T2.T3, and the semiconductor elements TI and T2. The structure of the compound semiconductor device includes a second element isolation band 20 that extends to the semiconductor substrate between the T3 and the semiconductor substrate. A second buffer layer 12'' having a higher resistance than the insulating semiconductor substrate and the first buffer layer, or having a different conductivity type from the active layer of the semiconductor element, and a first buffer layer 12 formed thereon, the upper part of which becomes a channel layer. A compound semiconductor IC (second structure IC) having an active layer 13 laminated through
), a first element isolation zone 19 is provided between semiconductor elements having the same applied voltage, reaching up to the first buffer layer, and a first element isolation zone 19 reaching up to the second buffer layer is provided between semiconductor elements having different applied voltages. This problem is solved by the structure of a compound semiconductor device that is provided with a second element isolation band 25 that extends to the second element isolation band 25.
尚、第１図において、同図（ａ）は第１構造ＩＣの断面
で同図（Ｃ）のＡＡ断面、同図（ｂ）は第２構造ＩＣの
断面で同図（Ｃ）のＡＡ断面、同図（Ｃ）は平面図であ
る。In Figure 1, (a) is a cross section of the first structure IC, which is the AA cross section in the figure (C), and (b) is a cross section of the second structure IC, which is the AA cross section in the figure (C). , the same figure (C) is a top view.
且つ、その製造方法としては、半絶縁性半導体基板に選
択的にバッファ層（または、第１バッファ層）まで達す
る第１の素子分離帯と第２の素子分離帯の上部とを化学
エツチングによって溝状に形成し、次いで、第２の素子
分離帯の下部をイオン注入によって不活性体が前記半導
体基板（または、第２バッファ層）まで達する第２の素
子分離帯を形成する工程、または、半絶縁性半導体基板
に選択的に第２の素子分離帯の上部を化学エツチングに
よって溝状に形成し、次いで、第２の素子分離帯の下部
および第１の素子分離帯をイオン注入によって不活性体
が前記半導体基板（または、第２バッファ層）まで達す
る第２の素子分離帯およびバッファ層（または、第１バ
ッファ層）まで達する第１の素子分離帯を形成する工程
が含まれることを特徴とする特
〔作 用〕
即ち、本発明は、印加電圧の同じ半導体素子相互の間に
はバッファ層（または、第１バッファ層）まで達する浅
い第１の素子分離帯を設け、印加電圧の鐸なる半導体素
子相互の間には半導体基板（または、半絶縁性半導体基
板および第１バッファ層より高抵抗、または、半導体素
子の能動層とは異種導電型の第２バッファ層）まで達す
る第２の素子分離帯を設ける。In addition, as a manufacturing method thereof, grooves are selectively formed in a semi-insulating semiconductor substrate by chemical etching in the upper part of the first element isolation band and the second element isolation band that reach the buffer layer (or the first buffer layer). and then forming a second element isolation band in which the inert material reaches the semiconductor substrate (or the second buffer layer) by ion implantation into the lower part of the second element isolation band, or The upper part of the second element isolation band is selectively formed into a groove shape on the insulating semiconductor substrate by chemical etching, and then the lower part of the second element isolation band and the first element isolation band are formed with an inert material by ion implantation. The method includes a step of forming a second device isolation band that reaches the semiconductor substrate (or the second buffer layer) and a first device isolation band that reaches the buffer layer (or the first buffer layer). Namely, in the present invention, a shallow first element isolation zone reaching up to the buffer layer (or the first buffer layer) is provided between semiconductor elements having the same applied voltage, and Between the semiconductor elements, there is a second element that reaches up to the semiconductor substrate (or a semi-insulating semiconductor substrate and a second buffer layer that has a higher resistance than the first buffer layer, or has a different conductivity type from the active layer of the semiconductor element). Provide a separation strip.
そうすれば、サイドゲート効果を解消でき、且つ、素子
分離帯を幅狭くできて、素子特性を維持し、集積度を向
上させることができる。By doing so, the side gate effect can be eliminated, and the device isolation band can be made narrower, device characteristics can be maintained, and the degree of integration can be improved.
〔実施例］ 以下、図面を参照して実施例によって詳細に説明する。〔Example] Hereinafter, embodiments will be described in detail with reference to the drawings.
第２図は本発明にかかる第１構造ＩＣの実施例Ｎ）の断
面図を示しており、ＴＩ、Ｔ２．Ｔ３はＨＥＭＴ素子、
２９は第１の素子分離帯、 ３０は第２の素子分離帯で
、その他の記号は第１０図と同一部位に同一記号が付け
である。このＨＥＭＴ素子のうち、Ｔ２はソース印加電
圧がＯ■であって、このソース電圧が素子Ｔ２に印加す
る電圧では最も低い電圧である。また、素子Ｔ３にもＴ
２と同じ電圧が印加する。一方、素子Ｔ１には一３■の
ソース電圧が印加されており、そのため、サイドゲート
効果によって素子Ｔ２．Ｔ３のｖｔｈが変化するから、
素子Ｔ１の周囲に設ける素子分離帯を半絶縁性ＧａＡｓ
基板１まで達する第２の素子分離帯３０とし、他の素子
Ｔ２．Ｔ３相互の周囲に設ける素子分離帯をバッファ層
２（その上部は二次電子ガスが発生するチャネルとなる
）まで達する第１の素子分離帯２９とする。且つ、第１
の素子分離帯２９および第２の素子分離帯３０の上部を
溝状に空隙化し、第２の素子分離帯３０の下部を不活性
体化した構成としている。そうすれば、第１の素子分離
帯２９は浅いために幅を狭くすることができ、更に、第
２の素子分離帯３０は不活性体の部分が素子分離帯の下
部のみになるために横方向への拡がりが少なくなって、
その幅も比較的に狭くできる。そのために、集積度を向
上することができ、且つ、サイドゲート効果を解消させ
ることができる。FIG. 2 shows a cross-sectional view of Example N) of the first structure IC according to the present invention, in which TI, T2. T3 is a HEMT element,
29 is a first element isolation band, 30 is a second element isolation band, and the other symbols are the same parts as in FIG. 10 with the same symbols. Among these HEMT elements, T2 has a source applied voltage of O■, and this source voltage is the lowest voltage applied to element T2. Also, T3 is also connected to element T3.
The same voltage as 2 is applied. On the other hand, a source voltage of 13cm is applied to the element T1, and therefore, due to the side gate effect, the element T2. Since the vth of T3 changes,
The device isolation band provided around the device T1 is made of semi-insulating GaAs.
The second element isolation band 30 reaches the substrate 1, and the other elements T2. The device isolation zone provided around each T3 is a first device isolation zone 29 that reaches up to the buffer layer 2 (the upper part of which becomes a channel in which secondary electron gas is generated). And the first
The upper portions of the element isolation band 29 and the second element isolation band 30 are formed into groove-like voids, and the lower part of the second element isolation band 30 is made into an inert material. By doing so, the width of the first device isolation band 29 can be narrowed because it is shallow, and furthermore, the width of the second device separation band 30 can be reduced because the inert portion is only the lower part of the device separation band. The spread in the direction is reduced,
Its width can also be made relatively narrow. Therefore, the degree of integration can be improved and the side gate effect can be eliminated.
次に、第３図（ａ）〜（ｂ）は実施例（Ｉ）の製造方法
の工程順断面図を示しており、順を追って説明すると、
第３図（ａ）に示すように、半絶縁性ＧａＡｓ基板１（
Ｃｒドープ）上にｉ −ＧａＡｓ層 （ノンドープ）か
らなるバッファ層２（膜厚５０００人）を成長し、次に
Ｓｉをドープしてｎ −ＡＩＧａＡｓ層からなる電子供
給層３（膜厚４００人）とｎ−ＧａＡｓ層からなるコン
タクト層４（膜厚１０００人）とをＭＢＥ法やＭＯＣＶ
Ｄ法によってエピタキシャル成長し、リソグラフィ技術
を用いて第１．第２の素子分離帯領域を化学エツチング
して、バッファ層２にまで達する溝２１を形成する。こ
の時、エツチング剤は弗酸＋過酸化水素の混合希釈液を
用いる。Next, FIGS. 3(a) to 3(b) show step-by-step cross-sectional views of the manufacturing method of Example (I), and will be explained step by step.
As shown in FIG. 3(a), a semi-insulating GaAs substrate 1 (
A buffer layer 2 (thickness: 5,000 layers) consisting of an i-GaAs layer (non-doped) is grown on the Cr-doped layer, and then an electron supply layer 3 (thickness: 400 layers) is doped with Si and made of an n-AIGaAs layer (thickness: 400 layers). and a contact layer 4 (thickness: 1000 mm) made of n-GaAs layer by MBE method or MOCV method.
Epitaxial growth is performed by the D method, and the first layer is grown using lithography technology. A trench 21 reaching the buffer layer 2 is formed by chemically etching the second isolation band region. At this time, a diluted mixed solution of hydrofluoric acid and hydrogen peroxide is used as the etching agent.
次いで、第３図（ｂ）に示すように、再びリソグラフィ
技術を用いて第２の素子分離帯領域のみを露出させたレ
ジスト膜マスク（図示せず）を形成し、露出させた第２
の素子分離帯にＧａＡｓ基板１に達する深さまで酸素イ
オンを注入して不活性体２２にする。イオン注入は加速
電圧１００〜２００ＫｅＶ、 ドーズ量１０１ｚ／ｃ
Ｊ程度の条件でおこなう。そうすれば、例えば、第１の
素子分離帯２９の幅を１μｍ程度、第２の素子分離帯３
０の幅を１．５μｍ程度にすることができる。以降は公
知の製法によって電掻を形成して第２図に示す構造に完
成させる。Next, as shown in FIG. 3(b), a resist film mask (not shown) exposing only the second element isolation zone region is formed again using lithography technology, and the exposed second
Oxygen ions are implanted into the device isolation zone to a depth that reaches the GaAs substrate 1 to form an inert material 22. Ion implantation is performed at an acceleration voltage of 100 to 200 KeV and a dose of 101z/c.
Perform under J conditions. Then, for example, the width of the first element isolation band 29 can be set to about 1 μm, and the width of the second element isolation band 3 can be set to about 1 μm.
The width of 0 can be set to about 1.5 μm. Thereafter, electric scrapers are formed by a known manufacturing method to complete the structure shown in FIG. 2.
次に、第４図は本発明にかかる第１構造ＩＣの実施例（
ｎ）の断面図を示しており、その記号は３９が第１の素
子分離帯、４０は第２の素子分離帯で、他の記号は第２
図と同一部位に同一記号が付けである。このＨＥＭＴ素
子も同様に、Ｔ２．Ｔ３には高い電圧が印加されて、素
子Ｔ１には低い電圧が印加されるため、素子Ｔ１の周囲
に設ける素子分離帯を半絶縁性ＧａＡｓ基板１まで達す
る第２の素子分離帯４０にし、他の素子Ｔ２．Ｔ３の周
囲に設ける素子分離帯をバッファ層２まで達する第１の
素子分離帯３９にしている。しかし、第２図に示す実施
例（Ｉ）と異なる点は、第２の素子分離帯４０の上部を
空隙にし、第２の素子分離帯４０の下部および第１の素
子分離帯３９を不活性体とした構成である。そうすれば
、同様に幅の狭い第１の素子分離帯を設け、更に、第２
の素子分離帯４０の幅も比較的に狭くできて、集積度を
向上させることができ、且つ、サイドゲート効果を解消
させることができる。Next, FIG. 4 shows an embodiment of the first structure IC according to the present invention (
n), in which the symbols 39 are the first isolation strip, 40 are the second isolation strip, and the other symbols are the second isolation strip.
The same parts as in the figure are given the same symbols. Similarly, this HEMT element also has T2. Since a high voltage is applied to T3 and a low voltage is applied to element T1, the element isolation band provided around element T1 is changed to the second element isolation band 40 that extends to the semi-insulating GaAs substrate 1, and Element T2. The element isolation band provided around T3 is a first element isolation band 39 that reaches up to the buffer layer 2. However, the difference from the embodiment (I) shown in FIG. It has a solid structure. In this way, the first device isolation band with a narrow width is similarly provided, and the second
The width of the device isolation band 40 can also be made relatively narrow, the degree of integration can be improved, and the side gate effect can be eliminated.
次に、第５図（ａ）〜（ｂ）は実施例（Ｉｆ）の製造方
法の工程順断面図を示しており、第５図（ａ）に示すよ
うに、半絶縁性ＧａＡｓ基板１上にｉ ＧａＡｓ層か
らなるバッファ層２（膜厚５０００人）とｎ −ＡＩＧ
ａＱｓ層からなる電子供給層３（膜厚４００人）とｎ−
ＧａＡｓ層からなるコンタクト層４ （膜厚１０００人
）とをエピタキシャル成長し、リソグラフィ技術を用い
て第２の素子分離帯領域を化学エツチングして、バッフ
ァ層２にまで達する溝２１を形成する。Next, FIGS. 5(a) to 5(b) show step-by-step cross-sectional views of the manufacturing method of Example (If). As shown in FIG. 5(a), the semi-insulating GaAs substrate 1 is Buffer layer 2 (thickness: 5000) consisting of i GaAs layer and n-AIG
Electron supply layer 3 (film thickness 400 layers) consisting of aQs layer and n-
A contact layer 4 (thickness: 1000 nm) made of a GaAs layer is epitaxially grown, and a trench 21 reaching the buffer layer 2 is formed by chemically etching the second isolation zone region using lithography technology.
次いで、第５図（ｂ）に示すように、再びリソグラフィ
技術を用いて第１．第２の素子分離帯領域を露出させた
レジスト膜マスク（図示せず）を形成し、露出させた第
１．第２の素子分離帯に酸素イオンを注入して不活性体
２２にする。その時、第２の素子分離帯では、ＧａＡｓ
基板１に達する深さまでイオン注入し、第１の素子分離
帯では、バッファ層２に達する深さまでイオン注入する
。そうすれば、第１の素子分離帯３９および第２の素子
分離帯４０の幅を実施例（１）と同様に狭くすることが
できる。Next, as shown in FIG. 5(b), the first. A resist film mask (not shown) is formed that exposes the second element isolation zone region, and the exposed first and second isolation zone regions are formed. Oxygen ions are implanted into the second isolation zone to form an inert body 22. At that time, in the second isolation band, GaAs
Ions are implanted to a depth that reaches the substrate 1, and in the first element isolation zone, ions are implanted to a depth that reaches the buffer layer 2. By doing so, the widths of the first element isolation band 39 and the second element isolation band 40 can be made narrow as in Example (1).
なお、第３図、第５図で説明した素子分離帯の形成方法
において、半絶縁性ＧａＡｓ基板１の第２の素子分離帯
部分に予め酸素イオンを注入して不活性体化しておき、
次に、バッファ層２．電子供給層３．コンタクト層４を
エピタキシャル成長すれば、より一層サイドゲート効果
を抑止できる。In addition, in the method for forming the device isolation band explained in FIGS. 3 and 5, oxygen ions are implanted in advance into the second device isolation band portion of the semi-insulating GaAs substrate 1 to make it inert.
Next, buffer layer 2. Electron supply layer 3. If the contact layer 4 is grown epitaxially, the side gate effect can be further suppressed.
次に、第６図は本発明にかかる第２構造ＩＣの実施例（
ＩＩＩ）の断面図を示しており、記号１は半絶縁性Ｇａ
Ａｓ基板、２パは高抵抗なｉ ＧａＡｓ層からなる第
２バッファ層（膜厚５００人）、２１はｊ −ＧａＡｓ
層からなる第１バッファ層（膜厚５０００人）。Next, FIG. 6 shows an embodiment of the second structure IC according to the present invention (
III), where symbol 1 is semi-insulating Ga
As substrate, 2p is a second buffer layer (thickness: 500) consisting of a high-resistance i-GaAs layer, and 21 is j-GaAs.
A first buffer layer (thickness: 5000 layers).
３はｎ−ＡｌＧａＡｓ層からなる電子供給層（膜厚４０
０人）、４はｎ−ＧａＡｓ層からなるコンタクト層（膜
厚１０００人）、２９が第１の素子分離帯、３５は第２
の素子分離帯で、Ｔｌ、Ｔ２．Ｔ３はＨＥＭＴ素子であ
る。この第２構造ＩＣが第１構造ＩＣと異なる構成はバ
ッファ層２の代わりに第２バッファ層２°゛（膜厚５０
０人）と第１バッファ層２’（膜厚５０００人）とを設
けたことにあり、この第２バッファ層２″′は半絶縁性
ＧａＡｓ基板１．第１バッファ層２′よりも高抵抗で、
第１バッファ層２゛と同じ１−ＧａＡｓ層からなるもの
の結晶欠陥の多い結晶層である。且つ、ＨＥＭＴ素子Ｔ
２．Ｔ３には高い電圧が印加されて、素子Ｔ１には低い
電圧が印加される構成であり、素子Ｔ１の周囲に設ける
素子分離帯を第２バッファ層２′°まで達する第２の素
子分離帯３５にし、他の素子Ｔ２．Ｔ３の周囲に設ける
素子分離帯を第１バッファ層２°まで達する第１の素子
分離帯２９としており、その素子分離帯の構造は第２図
に示す第１構造ＩＣと同様に第１の素子分離帯２９およ
び第２の素子分離帯３５の上部を溝状に空隙にし、第２
の素子分離帯３５の下部を不活性体化した構成である。3 is an electron supply layer made of n-AlGaAs layer (thickness 40
0), 4 is a contact layer made of an n-GaAs layer (thickness: 1000), 29 is the first isolation band, 35 is the second
Tl, T2 . T3 is a HEMT element. This second structure IC is different from the first structure IC in that it has a second buffer layer 2° (film thickness 50 mm) instead of the buffer layer 2.
This is because the second buffer layer 2'' has a semi-insulating GaAs substrate 1.0 and a first buffer layer 2' (thickness: 5,000 layers), which has a higher resistance than the semi-insulating GaAs substrate 1. in,
Although it is made of the same 1-GaAs layer as the first buffer layer 2', it is a crystal layer with many crystal defects. And HEMT element T
2. The configuration is such that a high voltage is applied to T3 and a low voltage is applied to element T1, and the element isolation band provided around element T1 is a second element isolation band 35 that reaches up to the second buffer layer 2'°. and other elements T2. The element isolation band provided around T3 is a first element isolation band 29 that reaches up to 2° of the first buffer layer, and the structure of the element isolation band is similar to that of the first structure IC shown in FIG. The upper portions of the separation band 29 and the second element separation band 35 are made into groove-like spaces, and the second
This is a structure in which the lower part of the element isolation band 35 is made inert.
そうすれば、第１の素子分離帯２９の幅を狭（すること
ができ、更に、第２の素子分離帯３５は不活性体の部分
が横方向への拡がりが少なくなって、高集積化させるこ
とができ、しかも、高抵抗な第２バッファ層２″が介在
するために、ＧａＡｓ基板とバッファ層との界面だけで
なく、バッファ層やＧａＡｓ基板が関与したサイドゲー
ト効果を殆ど完全に抑止することができる。In this way, the width of the first element isolation band 29 can be narrowed, and furthermore, the width of the second element isolation band 35 is reduced in the horizontal direction of the inactive material portion, resulting in higher integration. Moreover, since the high-resistance second buffer layer 2'' is present, not only the interface between the GaAs substrate and the buffer layer but also the side gate effect caused by the buffer layer and the GaAs substrate can be almost completely suppressed. can do.
次に、第７図（ａ）〜（ｂ）は実施例（ＩＩＩ）の製造
方法の工程順断面図を示しており、順を追って説明する
と、第７図（ａ）に示すように、半絶縁性ＧａＡｓ基板
１ （Ｃｒドープ）上に第２バッファ層２”（膜厚５
００人）と第１バッファ層２° （膜厚５０００人）と
電子供給層３（膜厚４００人）とコンタクト層４（膜厚
１０００人）とをエピタキシャル成長し、リソグラフィ
技術を用いて第１．第２の素子分離帯領域を化学エツチ
ングして、第１バッファ層２′にまで達する溝２１を形
成する。この際、第２バッファ層２”はＭＢＥ法により
基板温度を２００’Ｃとして成長し、第１バッファ層２
゛は基板温度を６８０″Ｃとして成長させるが、このよ
うに基板温度を低温にして成長するとトラップの多い単
結晶層が得られ、半絶縁性ＧａＡｓ基板よりも高抵抗な
第２バッファ層２′°が形成される（特願昭６３−１９
４９５６号参照）。Next, FIGS. 7(a) and 7(b) show cross-sectional views of the manufacturing method of Example (III) in the order of steps. A second buffer layer 2” (thickness 5”) is formed on an insulating GaAs substrate 1 (Cr doped).
00 layers), a first buffer layer 2° (thickness: 5000 layers), an electron supply layer 3 (thickness: 400 layers), and a contact layer 4 (thickness: 1000 layers) were epitaxially grown, and the first buffer layer 2° (thickness: 5000 layers) was grown using lithography technology. The second isolation band region is chemically etched to form trenches 21 that reach the first buffer layer 2'. At this time, the second buffer layer 2'' is grown by the MBE method at a substrate temperature of 200'C, and the first buffer layer 2'' is grown using the MBE method at a substrate temperature of 200'C.
'' is grown at a substrate temperature of 680''C, but when grown at a lower substrate temperature in this way, a single crystal layer with many traps is obtained, and the second buffer layer 2' has a higher resistance than the semi-insulating GaAs substrate. ° is formed (Japanese Patent Application No. 1983-1983)
4956).
次いで、第７図（ｂ）に示すように、再びリソグラフィ
技術を用いて第２の素子分離帯領域のみを露出させたレ
ジスト膜マスク（図示せず）を形成し、露出させた第２
の素子分離帯にＧａＡｓ基板１に達する深さまで酸素イ
オンを注入して不活性体２２にする。そうすれば、第１
の素子分離帯２９の幅を１μｍ程度、第２の素子分離帯
３５の幅を１．５μｍ程度にすることができる。以降は
公知の製法によって電極を形成して第６図に示す構造に
完成させる。Next, as shown in FIG. 7(b), a resist film mask (not shown) exposing only the second element isolation zone region is formed again using lithography technology, and the exposed second
Oxygen ions are implanted into the device isolation zone to a depth that reaches the GaAs substrate 1 to form an inert material 22. Then, the first
The width of the device isolation band 29 can be set to about 1 μm, and the width of the second device separation band 35 can be set to about 1.5 μm. Thereafter, electrodes are formed by a known manufacturing method to complete the structure shown in FIG.
次に、第８図は本発明にかかる第２構造ＩＣの実施例（
ＩＶ）の断面図を示しており、その記号は３９が第１の
素子分離帯、４５が第２の素子分離帯で、他の記号は第
６図と同一部位に同一記号が付けである。このＨＥＭＴ
素子も同様に、Ｔ２．Ｔ３には高い電圧が印加されて、
素子ＴＩには低い電圧が印加されるため、素子ＴＩの周
囲に設ける素子分離帯を第２バッファ層２″まで達する
第２の素子分離帯４５にし、他の素子Ｔ２．Ｔ３の周囲
に設ける素子分離帯を第１バッファ層２°まで達する第
１の素子分離帯３９にしている。第６図に示す実施例（
Ｉ）と異なる点は、第２の素子分離帯４５の上部を空隙
にし、第２の素子分離帯４５の下部および第１の素子分
離帯３９を不活性体とした構成で、その素子分離帯の構
造は第４図に示す第１構造ＩＣと同様である。且つ、高
抵抗な第２バッファ層２゛′が介在するために、サイド
ゲート効果の抑制は完全におこなわれる。Next, FIG. 8 shows an embodiment of the second structure IC according to the present invention (
IV), in which the symbols 39 are the first isolation strip, 45 the second isolation strip, and the other symbols are the same parts as in FIG. 6 with the same symbols. This HEMT
Similarly, the element also has T2. A high voltage is applied to T3,
Since a low voltage is applied to the element TI, the element isolation band provided around the element TI is changed to the second element isolation band 45 that reaches up to the second buffer layer 2'', and the element isolation band provided around the other elements T2 and T3 is changed. The isolation band is a first element isolation band 39 that reaches up to 2° of the first buffer layer.The embodiment shown in FIG.
The difference from I) is that the upper part of the second element isolation band 45 is made into a void, and the lower part of the second element isolation band 45 and the first element isolation band 39 are made into an inert body. The structure of is similar to the first structure IC shown in FIG. In addition, since the high-resistance second buffer layer 2' is present, the side gate effect is completely suppressed.
次に、第９図（ａ）〜（ｂ）は実施例（ＴＶ）の製造方
法の工程順断面図を示しており、第９図（ａ）に示すよ
うに、半絶縁性ＧａＡｓ基板１ （Ｃｒドープ）上に
第２バッファ層２″（膜厚５００人）と第１バッファ層
２゛ （膜厚５０００人）と電子供給層３（膜厚４００
人）とコンタクト層４ （膜厚１０００人）とをエピタ
キシャル成長し、リソグラフィ技術を用いて第２の素子
分離帯領域を化学エツチングして、第１バッファ層２°
にまで達する溝２１を形成する。この際、第２バッファ
層２１′はＭＢＥ法により基板温度を２００°Ｃとして
成長し、第１バッファ層２“は基板温度を６８０°Ｃと
して成長する。Next, FIGS. 9(a) and 9(b) show step-by-step cross-sectional views of the manufacturing method of the example (TV), and as shown in FIG. 9(a), the semi-insulating GaAs substrate 1 ( A second buffer layer 2'' (thickness: 500 mm), a first buffer layer 2'' (thickness: 5000 mm), and an electron supply layer 3 (thickness: 400 mm) are formed on the (Cr-doped)
A contact layer 4 (thickness: 1,000 mm) is epitaxially grown, a second isolation band region is chemically etched using lithography technology, and a first buffer layer 2
A groove 21 is formed that reaches up to . At this time, the second buffer layer 21' is grown by the MBE method at a substrate temperature of 200°C, and the first buffer layer 2'' is grown at a substrate temperature of 680°C.
次いで、第９図（ｂ）に示すように、再びリソグラフィ
技術を用いて第１．第２の素子分離帯領域を露出させた
レジスト膜マスク（図示せず）を形成し、露出させた第
１．第２の素子分離帯に酸素イオンを注入して不活性体
２２にする。その時、第２の素子分離帯では、第２バッ
ファ層２１゛に達する深さまでイオン注入し、第１の素
子分離帯では、第１バッファ層２“に達する深さまでイ
オン注入する。そうすれば、第１の素子分離帯３９およ
び第２の素子分離帯４５の幅を実施例（Ｉ［［）と同様
に狭くすることができる。Next, as shown in FIG. 9(b), the first. A resist film mask (not shown) is formed that exposes the second element isolation zone region, and the exposed first and second isolation zone regions are formed. Oxygen ions are implanted into the second isolation zone to form an inert body 22. At this time, in the second isolation zone, ions are implanted to a depth that reaches the second buffer layer 21'', and in the first isolation zone, ions are implanted to a depth that reaches the first buffer layer 2''. The widths of the first element isolation band 39 and the second element isolation band 45 can be made narrow as in the embodiment (I[[).
また、上記の第６図ないし第９図で説明した第２構造化
合物半導体ＩＣにおいては、ＭＢＥ法によって基板温度
２００’Ｃで成長した高抵抗なＧａＡｓ層を第２バッフ
ァ層としたが、同様に低い基板温度（例えば２００°Ｃ
）で成長した高抵抗なＡｌＧａＡｓ層、ＭＢＥ法やＭＯ
ＣＶＤ法で成長した他の方法で形成した高抵抗なＡｌＧ
ａＡｓ層やＧａＡｓ層、あるいは、ｎ−＾ｌＧａＡｓ層
からなる電子供給層３． ｎ−ＧａＡｓ層からなるコ
ンタクト層４から構成されたｎ−能動層とは反対導電型
のｐ −ＡｌＧａＡｓ層やｐ −ＧａＡｓ層などのサイ
ドゲート抑制効果のある層を第２バンフア層として設け
ても良い。Furthermore, in the second structural compound semiconductor IC described in FIGS. 6 to 9 above, a high-resistance GaAs layer grown at a substrate temperature of 200'C by the MBE method was used as the second buffer layer. Low substrate temperature (e.g. 200°C
) High resistance AlGaAs layer grown by MBE method or MO
High-resistance AlG grown by CVD and other methods
Electron supply layer 3 consisting of an aAs layer, a GaAs layer, or an n-^lGaAs layer. A layer having a side gate suppressing effect such as a p-AlGaAs layer or a p-GaAs layer having a conductivity type opposite to that of the n-active layer composed of the contact layer 4 made of an n-GaAs layer may be provided as the second buffer layer. good.
更に、上記に説明した実施例は酸素イオンを注入して不
活性体化したが、酸素イオン以外のプロトン、−・リウ
ム、硼素、燐などの基板を不活性体化することの可能な
他のイオンを注入してもよい。Furthermore, in the embodiment described above, oxygen ions were implanted to inactivate the substrate, but other materials other than oxygen ions, such as protons, -.lium, boron, and phosphorus, which can inactivate the substrate, Ions may also be implanted.
且つ、第２図〜第９図に示す実施例においては、バッフ
ァ層２または第１バッファ層２°を膜厚５０００人にし
ているが、この膜厚が４０００Å以下になれば第２図〜
第５図の実施例では基板・バッファ層界面の影響のため
、また、第６図〜第９図の実施例では高抵抗バッファ層
２″の影響のために素子特性が劣化し、例えば、第１バ
ッファ層を２０００人とすると、相互コンダクタンスＧ
ｍ、に値は約１０〜３０％程度低下する。そのため、バ
ッファ層は数千人程度に厚く形成することが重要である
。従って、本発明にかかる構造はこのバッファ層の膜厚
に原因するところが大きいものである。In addition, in the embodiments shown in FIGS. 2 to 9, the buffer layer 2 or the first buffer layer 2° is made to have a film thickness of 5000 Å, but if this film thickness becomes 4000 Å or less, the thickness shown in FIGS.
In the embodiment shown in FIG. 5, the device characteristics deteriorate due to the influence of the substrate/buffer layer interface, and in the embodiments shown in FIGS. If one buffer layer has 2000 people, the mutual conductance G
m, the value decreases by about 10 to 30%. Therefore, it is important to form the buffer layer as thick as several thousand layers. Therefore, the structure according to the present invention is largely due to the thickness of this buffer layer.
更に、上記の実施例は低電圧が印加されるＨＥＭＴ素子
の周囲に深い第２の素子分離帯を設けた例であるが、そ
の逆に、高電圧が印加されるＨＥＭＴ素子の周囲に深い
第２の素子分離帯を設けても同様の効果がある。その際
、数の少ない方の素子を深い第２の素子分離帯で包囲す
る方式を採ることが高集積化のために得策である。Furthermore, the above embodiment is an example in which a deep second isolation band is provided around the HEMT element to which a low voltage is applied, but conversely, a deep second isolation band is provided around the HEMT element to which a high voltage is applied. A similar effect can be obtained by providing two isolation bands. In this case, it is advisable to adopt a method in which the smaller number of elements is surrounded by a deep second element isolation zone for higher integration.
更に補足説明すれば、第２の素子分離帯は上記のように
異電圧が印加されるＨＥＭＴ素子の周囲を完全に包囲す
る構成にすることが最適であるが、設計上から止むを得
ぬ場合には部分的に途切れた第２の素子分離帯を設けて
もサイドゲート効果の抑制に相当の効果が得られる。As a supplementary explanation, it is optimal for the second element isolation band to completely surround the HEMT element to which different voltages are applied as described above, but if it is unavoidable from a design perspective. Even if a partially interrupted second element isolation band is provided, a considerable effect can be obtained in suppressing the side gate effect.
上記のように、本発明にかかる構造は化合物半導体ＩＣ
を一層高集積化し、且つ、ｖｔｈを一定化するなど素子
特性を安定にすることができる大きな効果のあるもので
ある。As described above, the structure according to the present invention is a compound semiconductor IC.
This has the great effect of making it possible to further increase the integration density and stabilize device characteristics such as keeping vth constant.
なお、上記実施例はＨＥＭＴ素子からなるＩＣで説明し
たが、ＭＥＳＦＥＴ （金属半導体電界効果トランジス
タ）素子などの他の化合物半導体素子からなるｔＣにも
適用できることは云うまでもない。It should be noted that although the above embodiment has been described using an IC made of a HEMT element, it goes without saying that it can also be applied to a tC made of other compound semiconductor elements such as a MESFET (metal semiconductor field effect transistor) element.
以上の説明から明らかなように、本発明によれば安定な
特性をもった化合物半導体ＩＣを高密度に形成すること
ができて、超高速ＩＣの今後の発展に太き（寄与するも
のである。As is clear from the above description, according to the present invention, compound semiconductor ICs with stable characteristics can be formed at high density, which will greatly contribute to the future development of ultra-high-speed ICs. .
第１図（ａ）〜（Ｃ）は原理図、
第２図は本発明にかかる第１構造ＩＣの実施例（Ｉ）の
断面図、
第３図（ａ）、 （ｂ）は実施例（Ｉ）の製造方法の工
程順断面図、
第４図は本発明にかかる第１構造ＩＣの実施例（ｎ）の
断面図、
第５図（ａ）、（ロ）は実施例（ｎ）の製造方法の工程
順断面図、
第６図は本発明にかかる第２構造ＩＣの実施例（ＩＩＩ
）の断面図、
第７図（ａ）、 （ｂ）は実施例（Ｉ［）の製造方法の
工程順断面図、
第８図は本発明にかかる第２構造ＩＣの実施例（ＩＶ）
の断面図、
第９図（ａ）、 （ｂ）は実施例（ＩＶ）の製造方法の
工程順断面図、
第１０図（ａ）、■）は従来の）ＩＥＭＴＩＣの断面図
である。
図において、
１は半絶縁性ＧａＡｓ基板、
２はｉ −ＧａＡｓ層からなるバッファ層、２°は第１
バッファ層、２゛１は第２バッファ層、３はｎ−＾ｌＧ
ａＡｓ層からなる電子供給層、４はｎ−ＧａＡｓ層から
なるコンタクト層、５は二次元電子層（２ＤＥＣ）、
６はゲート電極、
７．８はソース電極およびドレイン電極、Ｔ１．Ｔ２．
Ｔ３はＩ（ＥＭＴ素子、または、半導体素子、
９、１９．２９．３９は第１の素子分離帯、１０、２０
．２５．３０．３５．４０．４５は第２の素子分離帯、
１１は半絶縁性基板、
１２はバッファ層、
１２°は第１バッファ層、
１２”は第２バッファ層、
１３は能動層、
２１は溝、 ２２は不活性体を示している
。1(a) to (C) are the principle diagrams, FIG. 2 is a sectional view of the embodiment (I) of the first structure IC according to the present invention, and FIGS. 3(a) and (b) are the embodiment ( FIG. 4 is a cross-sectional view of Example (n) of the first structure IC according to the present invention; FIGS. 5(a) and (B) are cross-sectional views of Example (n) of the manufacturing method of I). FIG. 6 is a cross-sectional view of the manufacturing method in the order of steps, showing an embodiment (III) of the second structure IC according to the present invention.
), FIGS. 7(a) and (b) are cross-sectional views in the order of steps of the manufacturing method of Example (I[), and FIG. 8 is Example (IV) of the second structure IC according to the present invention.
FIGS. 9(a) and 9(b) are sectional views in the order of steps of the manufacturing method of Example (IV), and FIGS. 10(a) and 1) are sectional views of a conventional IEMTIC. In the figure, 1 is a semi-insulating GaAs substrate, 2 is a buffer layer made of an i-GaAs layer, and 2° is a first
Buffer layer, 2゛1 is the second buffer layer, 3 is n-^lG
An electron supply layer made of an aAs layer, 4 a contact layer made of an n-GaAs layer, 5 a two-dimensional electron layer (2DEC), 6 a gate electrode, 7.8 a source electrode and a drain electrode, T1. T2.
T3 is I (EMT element or semiconductor element, 9, 19.29.39 is the first element isolation band, 10, 20
．． 25.30.35.40.45 is the second element isolation band,
11 is a semi-insulating substrate, 12 is a buffer layer, 12° is a first buffer layer, 12'' is a second buffer layer, 13 is an active layer, 21 is a groove, and 22 is an inactive body.
Claims (4)
なるバッファ層を介して積層した能動層を有する化合物
半導体集積回路において、印加電圧の同じ半導体素子相
互の間には前記バッファ層まで達する第１の素子分離帯
を設け、且つ、印加電圧の異なる半導体素子相互の間に
は前記半導体基板まで達する第２の素子分離帯を設けた
ことを特徴とする化合物半導体装置。(1) In a compound semiconductor integrated circuit having an active layer laminated on a semi-insulating semiconductor substrate with a buffer layer whose upper part serves as a channel layer interposed therebetween, the voltage between semiconductor elements with the same applied voltage reaches up to the buffer layer. A compound semiconductor device characterized in that a first element isolation band is provided, and a second element isolation band that reaches the semiconductor substrate is provided between semiconductor elements having different applied voltages.
よび第１バッファ層より高抵抗、または、半導体素子の
能動層とは異種導電型の第２バッファ層と、その上に形
成され上部がチャネル層となる該第１バッファ層とを介
して積層した能動層を有する化合物半導体集積回路にお
いて、印加電圧がほぼ同じ半導体素子相互の間には前記
第１バッファ層まで達する第１の素子分離帯を設け、且
つ、印加電圧の異なる半導体素子相互の間には前記第２
バッファ層まで達する第２の素子分離帯を設けたことを
特徴とする化合物半導体装置。(2) A second buffer layer having a higher resistance than the semi-insulating semiconductor substrate and the first buffer layer, or having a different conductivity type than the active layer of the semiconductor element, and an upper layer formed on the semi-insulating semiconductor substrate. In a compound semiconductor integrated circuit having an active layer laminated through the first buffer layer, which serves as a channel layer, between the semiconductor elements to which the applied voltage is approximately the same, there is a first element isolation layer that reaches the first buffer layer. A band is provided, and the second band is provided between the semiconductor elements having different applied voltages.
A compound semiconductor device characterized in that a second element isolation band is provided that reaches a buffer layer.
ファ層と）を介して能動層を成長した半絶縁性半導体基
板に選択的に前記バッファ層（または、第１バッファ層
）まで達する第１の素子分離帯と第２の素子分離帯の上
部とを化学エッチングによつて溝状に形成し、次いで、
第２の素子分離帯の下部をイオン注入によつて不活性体
が前記半導体基板（または、第２バッファ層）まで達す
る第２の素子分離帯を形成する工程が含まれてなること
を特徴とする化合物半導体装置の製造方法。(3) A layer that selectively reaches the buffer layer (or the first buffer layer) on a semi-insulating semiconductor substrate on which an active layer is grown via the buffer layer (or the second buffer layer and the first buffer layer). The first element isolation band and the upper part of the second element isolation band are formed into a groove shape by chemical etching, and then,
The feature further includes the step of forming a second element isolation band in which the inert material reaches the semiconductor substrate (or the second buffer layer) by ion implantation into the lower part of the second element isolation band. A method for manufacturing a compound semiconductor device.
ファ層と）を介して能動層を成長した半絶縁性半導体基
板に選択的に第２の素子分離帯の上部を化学エッチング
によつて溝状に形成し、次いで、第２の素子分離帯の下
部および第１の素子分離帯をイオン注入によつて不活性
体が前記半導体基板（または、第２バッファ層）まで達
する第２の素子分離帯および前記バッファ層（または、
第１バッファ層）まで達する第１の素子分離帯を形成す
る工程が含まれてなることを特徴とする化合物半導体装
置の製造方法。(4) Selectively chemically etching the upper part of the second device isolation zone on the semi-insulating semiconductor substrate on which the active layer has been grown via the buffer layer (or the second buffer layer and the first buffer layer). a second element formed in a groove shape, and then ion-implanted into the lower part of the second element isolation band and the first element isolation band so that the inert material reaches the semiconductor substrate (or the second buffer layer); the separator and the buffer layer (or
1. A method for manufacturing a compound semiconductor device, comprising the step of forming a first element isolation band that reaches up to a first buffer layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1126438A JP2884596B2 (en) | 1988-05-24 | 1989-05-18 | Compound semiconductor device and method of manufacturing element separation band |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63-127870 | 1988-05-24 | ||
| JP12787088 | 1988-05-24 | ||
| JP1126438A JP2884596B2 (en) | 1988-05-24 | 1989-05-18 | Compound semiconductor device and method of manufacturing element separation band |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0249465A true JPH0249465A (en) | 1990-02-19 |
| JP2884596B2 JP2884596B2 (en) | 1999-04-19 |
Family
ID=26462621
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1126438A Expired - Fee Related JP2884596B2 (en) | 1988-05-24 | 1989-05-18 | Compound semiconductor device and method of manufacturing element separation band |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2884596B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0846181A (en) * | 1994-07-28 | 1996-02-16 | Nec Corp | Manufacture of semiconductor device |
| US5523593A (en) * | 1992-03-30 | 1996-06-04 | Hitachi, Ltd. | Compound semiconductor integrated circuit and optical regenerative repeater using the same |
| US5739559A (en) * | 1994-03-17 | 1998-04-14 | Hitachi, Ltd. | Compound semiconductor integrated circuit with a particular high resistance layer |
| US6218685B1 (en) | 1998-01-08 | 2001-04-17 | Matsushita Electronics Corporation | Semiconductor device and method for fabricating the same |
| JP2005175477A (en) * | 2003-12-05 | 2005-06-30 | Internatl Rectifier Corp | Structure and manufacturing method of group iii nitride monolithic power ic |
| JP2008235740A (en) * | 2007-03-23 | 2008-10-02 | Furukawa Electric Co Ltd:The | GaN-BASED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF |
| WO2015125471A1 (en) * | 2014-02-21 | 2015-08-27 | パナソニック株式会社 | Field-effect transistor |
-
1989
- 1989-05-18 JP JP1126438A patent/JP2884596B2/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5523593A (en) * | 1992-03-30 | 1996-06-04 | Hitachi, Ltd. | Compound semiconductor integrated circuit and optical regenerative repeater using the same |
| US5739559A (en) * | 1994-03-17 | 1998-04-14 | Hitachi, Ltd. | Compound semiconductor integrated circuit with a particular high resistance layer |
| JPH0846181A (en) * | 1994-07-28 | 1996-02-16 | Nec Corp | Manufacture of semiconductor device |
| US6218685B1 (en) | 1998-01-08 | 2001-04-17 | Matsushita Electronics Corporation | Semiconductor device and method for fabricating the same |
| JP2005175477A (en) * | 2003-12-05 | 2005-06-30 | Internatl Rectifier Corp | Structure and manufacturing method of group iii nitride monolithic power ic |
| US7892938B2 (en) | 2003-12-05 | 2011-02-22 | International Rectifier Corporation | Structure and method for III-nitride monolithic power IC |
| JP2008235740A (en) * | 2007-03-23 | 2008-10-02 | Furukawa Electric Co Ltd:The | GaN-BASED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF |
| WO2015125471A1 (en) * | 2014-02-21 | 2015-08-27 | パナソニック株式会社 | Field-effect transistor |
| JPWO2015125471A1 (en) * | 2014-02-21 | 2017-03-30 | パナソニック株式会社 | Field effect transistor |
| US10529841B2 (en) | 2014-02-21 | 2020-01-07 | Panasonic Corporation | Field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2884596B2 (en) | 1999-04-19 |
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