JPH06104290A - Manufacture of compound semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method for manufacturing a compound semiconductor device having a complementary transistor by which when forming a complementary circuit, leak current is remarkably reduced without damaging the crystallinity and the surface flatness of a semiconductor layer can be secured. CONSTITUTION:In this method, a process wherein an intrinsic carrier drifting layer 2 and an n-type carrier supplying layer 3 are formed in this order and a process wherein by driving a p-type impurity into a formation region of a p-type HEMT by ion implantation, the n-type carrier supplying layer 3 in the formation region X of the p-type HEMT is converted to a p-type carrier supplying layer 2 are included. A process wherein a gate electrode 14 is brought into Schottky contact with the surface of the p-type carrier supplying layer 7 and a source electrode 15 and a drain electrode 16 are ohmic-connected to both sides of the gate electrode 14 to form a p-type HEMT and a process wherein a gate electrode 11 is brought into Schottky contact with the surface of the n-type carrier supplying layer 3 which is not doped with p-type impurity and a source electrode 12, and a drain electrode 13 are ohmic-connected to both sides of the gate electrode 11 to form an n-type HEMT are also included in this method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a compound semiconductor device, and more particularly to a method for manufacturing a compound semiconductor device having complementary transistors.

In recent years, electronic devices are required to have low power consumption as the integration density increases. For this reason, in silicon semiconductors, a complementary (complementary) circuit that uses the n channel and the p channel complementarily to reduce the power consumption of the DC component is often used.

However, in a compound semiconductor material, which is one of high-speed devices, there are few examples in which an n-channel and a p-channel are formed with good controllability to realize a low power consumption type complementary circuit.

This is because the compound semiconductor does not have a high-quality oxide film such as silicon, and the gate electrode is formed by the Schottky junction.

[0005]

2. Description of the Related Art GaAs MESFETs (metal-semicond
In a compound semiconductor complementary circuit using a uctor FET), hole mobility is as low as that of silicon (up to 400 cm ² / V · sec).
), In combination with a FET having a high mobility electron as a channel, high speed cannot be expected.

Therefore, a heterostructure is often used.
For example, as shown in FIG. 6, i-GaAs is formed on a GaAs substrate 60.
Layer 61 and i-AlGaAs layer 62 are laminated, and n-type FE
Two n ⁺ conductive layers 63 are formed by ion implantation at intervals on the i-AlGaAs layer 62 in the T region, a source electrode 64 and a drain electrode 65 are formed on them, and a region between them is formed. A gate electrode 66 is formed on a certain i-AlGaAs layer 62 to form an n-type FET t ₁ . On the other hand, two p ⁺ conductive layers 67 are provided in the p-type FET region by the same method,
A source electrode 68 and a drain electrode 69 are formed on the i-AlGaAs layer 62 between them, and a gate electrode 70 is formed on the i-AlGaAs layer 62 between them, thereby forming a p-type FET t ₂ .

In this case, the i-GaAs layer 61 of the n-type FET t ₁ is
An n channel is formed at the interface between the i-AlGaAs layer 62 and the i-AlGaAs layer 62, and a p channel is formed at the interface between the i-GaAs layer 61 and the i-AlGaAs layer 62 of the p-type FET t ₂ , and these FETs form a complementary circuit. To be done.

According to this, since the difference between the threshold voltages of the p-type and n-type FETs is large and a large power supply voltage is required, a gate leak current occurs during reverse bias, and it is difficult to reduce power consumption.

On the other hand, a method of forming a complementary circuit by an n-channel HEMT having an electron supply layer and a p-channel HEMT having a hole supply layer can be considered. For example, in FIG.
As shown in (a), the i-
After stacking the GaAs layer 72 and the n-InGaP electron supply layer 73,
As shown in FIG. 7B, the i-Ga in the p-type HEMT region A is
The As layer 72 and the n-InGaP electron supply layer 73 are etched to form a recess 74. Then, as shown in FIG. 7C, a semiconductor is selectively grown in the recess 74 to form an i-GaAs layer 75 and
The p-InGaP hole supply layer 76 is sequentially stacked.

After this, as shown in FIG. 7 (d), p-InGa
The gate electrode 77 is in Schottky contact on the P layer 76, and the source electrode 7 is formed in the regions on both sides of the gate electrode 77.
By ohmic-connecting 8 and the drain electrode 79, a p-channel HEMT is completed.

Further, by forming a gate electrode 80, a source electrode 81 and a drain electrode 82 on the n-InGaP layer 73, an n-channel HEMT is completed.

[0012]

However, if the complementary circuit is formed by such a method, the i-GaAs layer 75 and the p-InGaP hole supply layer 76 laminated in the recess 74 and the surroundings thereof are formed. Since an interface state is formed at the interface between the i-GaAs layer 72 and the n-InGaAs electron supply layer 73, a large leak current flows. In addition, the peripheral portions of the i-GaAs layer 75 and the p-InGaP hole supply layer 76 grown in the recess 74 rise, and the irregularities hinder the formation of electrodes such as the gate electrode 77.

The present invention has been made in view of the above problems, and when forming a complementary circuit, the leakage current is significantly suppressed without impairing crystallinity, and the surface of the semiconductor layer is flat. It is an object of the present invention to provide a method for manufacturing a compound semiconductor device capable of ensuring the reliability.

[0014]

The above-mentioned problem is opposite to the step of sequentially laminating the intrinsic carrier transit layer 2 and the one conductivity type carrier supply layer 3 on the semiconductor substrate 1 as illustrated in FIG. The opposite conductivity type HEMT is formed by ion-implanting the opposite conductivity type impurity into the formation region X of the conductivity type HEMT.
Forming the opposite-conductivity-type carrier supply layer 7 in the formation region X, and making a gate electrode 14 on the opposite-conductivity-type carrier supply layer 7 in Schottky contact. A step of forming an opposite conductivity type HEMT by ohmic-connecting the source electrode 15 and the drain electrode 16 on both sides of 14; and a gate electrode on the one conductivity type carrier supply layer 3 into which the opposite conductivity type impurity is not ion-implanted.
11 is in Schottky contact, and the source electrode 12 and the drain electrode 13 are ohmic-connected on both sides of the gate electrode 11 to form one conductivity type HEMT. To do.

Alternatively, as illustrated in FIG. 3, when the opposite conductivity type impurities are ion-implanted, the acceleration voltage is increased to keep the upper layer portion of the opposite conductivity type carrier supply layer 7 at one conductivity type. This is achieved by a method of manufacturing a compound semiconductor device, which is characterized by being intrinsic.

Alternatively, as illustrated in FIG. 5, before the ion implantation of the opposite conductivity type impurity, the surface of the one conductivity type carrier supply layer 3 in the region where the ion implantation is performed is etched to deplete the surface. This is achieved by a method for manufacturing a compound semiconductor device, which comprises the step of:

Alternatively, as illustrated in FIG. 4, a step of sequentially laminating an intrinsic carrier transit layer 2, an n-type carrier supply layer 3, and an n-type cap layer 4 on a semiconductor substrate 1, and a p-type H layer.
Thinning the source region and the drain region of the n-type cap layer 3 in the EMT region X to form the recesses 33 and 34; and the n-type carrier supply layer 3 and the n-type carrier supply layer 3 in the p-type HEMT region X. By implanting p-type impurities into the n-type cap layer 4, the n-type carrier supply layer 3 and the n-type cap layer 4 in the p-type HEMT region X are implanted.
To form a p-type carrier supply layer 7 and a p-type cap layer 8 and increase the p-type impurity concentration under the recesses 33 and 34; and on the p-type carrier supply layer 7. When the gate electrode 14 is in Schottky contact, the gate electrode 14
Forming a p-type HEMT by ohmic-connecting the source electrode 15 and the drain electrode 16 to the p-type cap layer 8 on both sides of the gate electrode on the n-type carrier supply layer 3 into which the p-type impurity is not implanted. To form a n-type HEMT by ohmic-connecting the source electrode 12 and the drain electrode 13 to the n-type cap layer 4 on both sides of the gate electrode. Achieve by method.

[0018]

[Operation] According to the first aspect of the present invention, by implanting opposite conductivity type ions into a part of the one conductivity type carrier supply layer 3, the region is formed as the opposite conductivity type carrier supply layer 7. The opposite conductivity type HEMT is formed on the type carrier supply layer 7.

Therefore, it is not necessary to re-grow the semiconductor in order to form the opposite conductivity type carrier supply layer 7, and the interface level of the re-growth interface and the unevenness of the re-growth portion do not occur.

Further, one conductivity type HEMT and opposite conductivity type HE
For both MT, it is easy to adjust the threshold voltage by adjusting the impurity concentration, the difference between the threshold voltages can be reduced, and it is effective in suppressing the gate leak current during reverse bias.

Further, according to the second aspect of the invention, since the acceleration voltage at the time of ion implantation of impurities of opposite conductivity type is increased,
Opposite conductivity type carrier supply layer 7 in opposite conductivity HEMT region
Is held in a region of intrinsic or one conductivity type, and in the opposite conductivity HEMT an np junction gate, or ip (or i
n) Since it is a junction gate, it is effective in reducing the gate leakage current and the power consumption of the complementary circuit.

Further, according to the third aspect of the present invention, since the upper portion of the opposite conductivity type carrier supply layer 7 is etched and depleted, p under the gate electrode 14 of the opposite conductivity type HEMT is used.
Since the surface of the type carrier supply layer 7 is depleted, the threshold voltage can be reduced.

Further, according to the fourth embodiment, a p-type HEM is used.
P-type carrier supply layer 7 of T and drain / source electrode 1
The cap layer 8 interposed between the layers 5 and 16 is formed by an n-type HEMT.
The source / drain electrode 1 of the p-type HEMT that uses holes with low mobility as carriers because it is thinner than that of
The layers under 5 and 16 serve as p ⁺ regions in a self-aligned manner, which is effective in reducing the parasitic resistance of the source of the p-type HEMT.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. (A) Description of the First Embodiment of the Present Invention FIG. 1 is a cross-sectional view showing the steps of the first embodiment of the present invention.

In FIG. 1, reference numeral 1 is a semi-insulating GaAs substrate on which an i-GaAs carrier transit layer 2, an n-InGaP carrier supply layer 3 and an n-GaAs cap are formed by an epitaxial growth method such as MOCVD. Layers 4 are laminated in 300 Å each.

In this case, the n-InGaP carrier supply layer 3 and
The n-GaAs cap layer 4 is made n-type by Si doping, and its concentration is 1 × 10 ¹⁸ / cm ³ . In this state,
Photoresist 5 is applied, exposed and developed, and p
A window 6 is formed in the type HEMT formation region X to expose the n-GaAs cap layer 4.

After this, Be ions are ion-implanted through the window 6. In this case, the dose amount is 3 × 10 ¹² / cm ² , the acceleration voltage is 30 keV, the n-GaAs cap layer 4 and the n-InGaP are
The Be ion peak is set to exist at the interface of the carrier supply layer 3.

Next, after peeling off the photoresist 5,
When lamp annealing is performed at 700 ° C. for 30 seconds, 100% of Be ions are activated, and the n-InGaP carrier supply layer 3 and the n-GaAs cap layer 4 in that region are compensated to be p-type, and FIG. 1 (b) P-InGaP carrier supply layer 7 and p-GaAs
It becomes the cap layer 8.

Note that i-Ga under the n-InGaP carrier supply layer is
The n-channel of the As carrier transit layer is not deteriorated by the lamp annealing under the above conditions, the two-dimensional electron gas concentration is 1.0 × 10 ¹² / cm ² , and the mobility is 6000 cm ² / V · se.
c.

After this, as shown in FIG. 1 (c), n-GaAs
The gate regions of the cap layer 4 and the p-GaAs cap layer 8 are removed by etching to form recesses 9 and 10, and n-InGa
Part of the P carrier supply layer 3 and the p-InGaP carrier supply layer 7 is exposed.

Then, as shown in FIG. 1 (d), n-InGaP
A gate electrode 11 is formed on the carrier supply layer 3 in Schottky contact, and a source electrode 12 and a drain electrode 13 are ohmic-connected on the n-GaAs cap layer 4 on both sides of the gate electrode 11, thereby forming an n-type HEMT. It is formed. And
Two-dimensional electron gas is present at the interface of the carrier transit layer 2 with the n-InGaP carrier supply layer 3.

Further, the gate electrode 14 is formed on the p-InGaP carrier supply layer 7, and the p-GaAs cap layers 8 on both sides thereof are formed.
A source electrode 15 and a drain electrode 16 are formed on top of this, whereby a p-type HEMT is completed. Then, a two-dimensional hole gas is generated at the interface of the carrier transit layer 2 with the p-InGaP carrier supply layer 7, and the two-dimensional hole gas concentration is 1.2 × 10 ¹² / cm ² . Become.

In this case, the two drain electrodes 13 and 16
Are conducted to form a complementary circuit of an equivalent circuit as shown in FIG. 1 (e). According to the above steps, p-type H
Since the p-GaAs cap layer 8 and the p-InGaP carrier supply layer 7 forming the EMT are formed by ion implantation of Be, it is not necessary to re-grow the semiconductor, and the interface level and the re-growth interface are not required. There is no unevenness in the grown portion.

Further, for both the n-type HEMT and the p-type HEMT, it is easy to adjust the threshold voltage by adjusting the impurity concentration, and the difference between the threshold voltages can be reduced.
The gate leak current during reverse bias can be minimized. (B) Description of Second Embodiment of the Present Invention In the above-mentioned embodiment, the boundary between the p-type HEMT and the n-type HEMT is a pn junction, but an isolation region is provided at the boundary to separate the elements. The manufacturing process will be described as a second embodiment.

FIG. 2 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention. First, as shown in FIG. 2 (a), the first
The i-GaAs carrier transit layer 2, the n-InGaP carrier supply layer 3, and the n-GaAs cap layer 4 are epitaxially grown in this order on the semi-insulating GaAs substrate 1 by the same method as in the embodiment. In this case, the layer thickness and the impurity concentration are the same as those in the first embodiment.

Next, a photoresist R is applied, and this is exposed and developed to form a p-type HEMT region X and an n-type HEMT.
The window 17 is provided at the boundary of the region Y. Then, oxygen ions are accelerated through the window 17 at an acceleration voltage of 120 keV and a dose of 5 × 10 ¹²
Implantation is performed under the condition of / cm ² to form the isolation region 18, and then the photoresist R is peeled off.

Next, as shown in FIG. 2 (b), a photoresist 19 is applied again, and this is exposed and developed to form a p-type H
A window 20 is formed in the EMT region X, Be ions are implanted into the p-type HEMT region X under the same conditions as in the first embodiment, and then lamp annealing is performed at about 700 ° C. for 30 seconds to activate the Be ions. To do. As a result, the n-GaAs cap layer 4 is changed to p-Ga.
While changing to the As cap layer 8, the n-InGaP carrier supply layer 3 is changed to the p-InGaP carrier supply layer 7.

After this, in the same manner as in the first embodiment, n-Ga
As shown in FIG. 2 (c), the gate regions of the As cap layer 4 and the p-GaAs cap layer 8 are removed by etching to form recesses 9 and 10, and the exposed n-InGaP carrier supply layer 3 and
On the p-InGaP carrier supply layer 7, as shown in FIG. 2 (d), the gate electrodes 11 and 14 respectively made of aluminum are formed.
To form.

Also, n-GaAs separated by the gate region
In each of the two regions of the cap layer 4, 20 AuGe and 20 Au are provided.
Isolation area 1 by stacking 0Å and 3000Å each
8 is closer to the drain electrode 13 and the other is closer to the source electrode 12
Thus, the n-type HEMT is completed.

Further, Cr and Au are respectively added to 500 in two regions of the p-GaAs contact layer 8 separated into the gate region.
Å Stacking 2500 Å each, isolation area 18
The side closer to is the drain electrode 16 and the other is the source electrode 15, whereby the p-type HEMT is completed.

Here, regarding the device characteristics when the gate length is 1 μm, the threshold voltage Vth of the n-type HEMT is 0.1.
V, conductance g _m is 250 ms / mm, and
The p-channel HEMT has a threshold voltage Vth of −0.1 V and a conductance g _m of 60 ms / mm.

According to this embodiment, similarly to the first embodiment, the p-GaAs cap layer 8 and the p-In forming the p-type HEMT are formed.
Since the GaP carrier supply layer 7 is made p-type by Be ion implantation, no interface state of crystal growth occurs, and
No unevenness is generated in the grown portion.

In addition, when the drain electrodes 13 and 16 of the n-type HEMT and the p-type HEMT are formed of different materials, the provision of the isolation region allows a margin at the time of forming the drain electrode and reduces the yield. Is suppressed. (C) Description of Third Embodiment of the Present Invention In the first and second embodiments described above, the implantation depth of Be ions is
Although the peak is set at the interface between the carrier supply layer and the cap layer, it may be deeper, and an example thereof will be described below.

FIG. 3 is a sectional view showing the manufacturing process of the third embodiment of the present invention. First, as shown in FIG. 3 (a), the second
Similar to the embodiment, i-GaAs is placed on the semi-insulating GaAs substrate 1.
Carrier traveling layer 2, n-InGaP carrier supply layer 3 and n-Ga
After the As cap layer 4 is sequentially stacked, oxygen ions are implanted into the boundary between the p-type HEMT region X and the n-type HEMT region Y to form the isolation region 18.

After this, as shown in FIG. 3B, a photoresist 21 is applied, and the photoresist 22 is exposed and developed to form a window 22 in the gate region of the p-type HEMT region X, and the window 22 is formed. Be ions are implanted through. In this case, the dose amount is 3.5 × 10 ¹² / cm ² , the acceleration voltage is 40 keV, and the p-type impurity is present under the n-InGaP carrier supply layer 4. Next, photoresist 2
1 is peeled off.

After this, as shown in FIG. 3C, a photoresist 23 is applied again, and this is exposed and developed, and n
The type HEMT region Y is covered with a photoresist 23, and a window 24 is formed in a portion of the p type HEMT region X other than the gate region.

Then, under the same conditions as in the first and second embodiments, Be
When ions are implanted and annealed, p-type HEMT region X
N-GaAs cap layer 4 and n-InGa other than the gate region
The P carrier supply layer 3 is made p-type, and the p-GaAs cap layer 2 is formed.
5 and the p-type InGaP carrier supply layer 26 is formed.

In this case, in the p-type InGaP carrier supply layer 26, the upper layer portion of the gate region becomes the n-type or i-type non-p-type region 27. Next, in the same manner as in the second embodiment, the gate regions of the n-GaAs cap layer and the p-GaAs cap layer 26 are removed by etching, aluminum gate electrodes 11 and 14 are formed in those regions, and The source electrode 1 is formed on both sides by using the same material as the second embodiment.
2, 15 and drain electrodes 13, 16 are formed.

According to this embodiment, in addition to the operation as shown in the second embodiment, the p-type HEMT has an np junction gate or an ip junction gate, so that the gate leakage current is reduced and the complementary circuit is consumed. The power can be reduced. (D) Description of Fourth Embodiment of the Present Invention In the above-mentioned three embodiments, the n-type HEMT and the p-type HEM are used.
Although the T cap layer has the same thickness, the p channel HEMT cap layer may be thin, and an example thereof will be described below.

First, similarly to the second embodiment, the i-GaAs carrier transit layer 2 and n-InGa are formed on the semi-insulating GaAs substrate 1.
After the P carrier supply layer 3 and the n-GaAs cap layer 4 are laminated in this order, oxygen ions are implanted at the boundary between the p-type HEMT region X and the n-type HEMT region Y to isolate the isolation region 18.
To form.

After this, as shown in FIG. 4 (a), a photoresist 30 is applied, and this is exposed and developed to form a p-type H
A window 31 is formed in the source / drain region of the EMT region X, and then the upper portion of the n-GaAs carrier supply layer 3 exposed from the window 31 is thinned by the RIE method or the like to form the recesses 32 and 33.
To provide. Then, the photoresist 30 is peeled off.

Next, a photoresist 35 is applied and patterned to form a window 36 exposing the p-type HEMT region X. Then, as shown in FIG. 4 (b), the first
Be ions were ion-implanted under the same conditions as in the embodiment, and the n-GaAs cap layer 4 and the n-InGaP carrier supply layer 3 in the region X were p-typed to form the p-GaAs cap layer 8 and the p-InGaP carrier. The supply layer 7 is formed, and then annealing is performed. Then, the photoresist 35 is removed.

After that, in the same manner as in the second embodiment, n-Ga
The two gate regions of the As cap layer 4 and the p-GaAs cap layer 8 are etched to form recesses 9 and 10 (FIG. 4 (c)).
Then, gate electrodes 11 and 14 are respectively formed on the n-InGaP carrier supply layer 3 and the p-InGaP carrier supply layer 7 exposed from the recesses 9 and 10, and the n-GaAs cap layer 4 on both sides thereof is formed.
Source electrodes 12 and 15 and drain electrodes 13 and 16 are formed on the p-GaAs cap layer 8.

According to such a structure, the source / drain
Thinning the cap layer 4 in the region
Therefore, in addition to the operation shown in the second embodiment, p channel
Under the HEMT source / drain electrodes 15, 16
Layer is p self-aligned ⁺Area, p-type HEM
This is effective in reducing the parasitic resistance of the source of T. (E) Description of the fifth embodiment of the present invention FIG. 5 is a sectional view showing a manufacturing process of the fifth embodiment of the present invention.
is there.

First, similarly to the second embodiment shown in FIG. 2A, the i-GaAs carrier transit layer 2, n-InGaP carrier supply layer 3 and n- are formed on the semi-insulating GaAs substrate 1. After sequentially stacking the GaAs cap layer 4, the p-type HEMT region X and the n-type H are formed.
Oxygen ions are implanted into the boundary of the EMT region Y to form the isolation region 18.

Next, as shown in FIG. 5A, a photoresist 38 is applied and patterned to form a p-type HEM.
A window 39 exposing the n-GaAs cap layer 4 in the T region X is formed, and then the n-GaAs cap layer 4 and the n-InGaP carrier supply layer 3 are etched by the RIE method or the like, and n-
The InGaP carrier supply layer 3 is thinned until the upper portion is depleted. Then, the photoresist 38 is peeled off.

Thereafter, as shown in FIG. 5B, the photoresist 40 is used as a mask and the dose amount is 1.5 × 1.
0 ¹² / cm ² , accelerating voltage of 15 keV and Be ions of p-type H
After implanting in the EMT region X, anneal is performed at 700 ° C. for 30 minutes.

As a result, the n-InGaP carrier supply layer 4 becomes the p-InGaP carrier supply layer 7 by compensating for the impurities, as in the above embodiment, and the p-InGaP carrier supply layer 7 is formed.
The upper part of is depleted.

Next, as shown in FIG. 5 (c), an n-type HEM is used.
The n-GaAs cap layer 4 in the gate region of the T region Y is etched to form the recess 9. After that, the gate electrode 11 is formed in the gate region of the n-InGaP cap layer 4, and the source electrode 12 and the drain electrode 13 are formed on each of the n-GaAs cap layers 4 on both sides thereof. Furthermore, exposed
A gate electrode 14 is formed in the center of the p-InGaP carrier supply layer 7, and a source electrode 15 and a drain electrode 16 are formed on both sides of the gate electrode 14 at intervals.

The material of the gate electrodes 11 and 14, the source electrodes 12 and 15 and the drain electrodes 13 and 16 is the second
The same thing as the example is used. According to such an embodiment, since the surface of the p-InGaP carrier supply layer 7 under the gate electrode 14 of the p-type HEMT is depleted, the threshold voltage can be reduced. In addition, the source electrodes 1 on both sides thereof
5 and the drain electrode 16 are ohmic-connected,
There is no influence of conductivity due to depletion. (F) Description of Other Embodiments of the Present Invention As the device of the above-mentioned embodiment, a structure having the characteristics of both the third and fourth embodiments can be formed, and the carrier supply layer below the gate electrode is of n-type or In addition to making it i-type, thin the cap layer on both sides to p ⁺ up to the carrier running layer below it.
It may be a region.

Further, the material of HEMT is not limited to the above-mentioned one, but as a material of the carrier supply layer.
InAlAs or AlGaAs may be used, and GaAs or InGaAs may be used as the material for the cap layer and the carrier transit layer above and below it.

Further, in the above embodiment, Be ions were implanted to make n-InGaAs and n-GaAs p-type, but a p-type element such as carbon (C) may be used. Further, in the above-described embodiment, n-InGaAs and n-GaAs are made to be p-type, but conversely, p-InGaAs and p-GaAs may be made to be n-type to form a complementary circuit. .

[0063]

As described above, according to the present invention, by implanting opposite conductivity type ions into a part of one conductivity type carrier supply layer, the region is formed as the opposite conductivity type carrier supply layer. The opposite conductivity type HE to the conductivity type carrier supply layer
Since the MT is formed, it is not necessary to re-grow the semiconductor in order to form the opposite conductivity type carrier supply layer, and the interface level of the re-growth interface and the unevenness of the re-growth part may occur. Can be prevented.

Further, one conductivity type HEMT and opposite conductivity type HEMT
For both MTs, it is easy to adjust the threshold voltage by adjusting the impurity concentration, the difference between the threshold voltages can be reduced, and the gate leak current during reverse bias can be minimized.

Further, according to the second aspect of the invention, since the acceleration voltage at the time of ion implantation of impurities of opposite conductivity type is increased,
The upper part of the opposite conductivity type carrier supply layer of the opposite conductivity type HEMT region is held in the intrinsic or one conductivity type region, and in the opposite conductivity type HEMT, an np junction gate, or ip (or i).
n) Since it is a junction gate, the gate leakage current can be reduced and the power consumption of the complementary circuit can be reduced.

Further, according to the third aspect of the present invention, since the upper portion of the opposite conductivity type carrier supply layer is etched and depleted, the surface of the p type carrier supply layer below the gate electrode of the opposite conductivity type HEMT is formed. Since it is depleted, the threshold voltage can be reduced.

Further, according to the fourth embodiment, the p-type HEM
Since the cap layer interposed between the p-type carrier supply layer of T and the drain / source electrode is made thinner than that of the n-type HEMT, p having holes with low mobility as carriers is used.
The layer below the source / drain electrodes of the p-type HEMT becomes the p ⁺ region in a self-aligned manner, and the parasitic resistance of the source of the p-type HEMT can be reduced.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the manufacturing process of the third embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the manufacturing process of the fourth embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the fifth embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a first conventional example.

FIG. 7 is a cross-sectional view showing a second conventional example.

[Explanation of symbols]

 1 GaAs substrate (semiconductor substrate) 2 i-GaAs carrier transit layer 3 n-InGaP carrier supply layer 4 n-GaAs cap layer 5 photoresist 6 window 7 p-InGaP carrier supply layer 8 p-GaAs cap layer 9, 10 recess 11 , 14 gate electrode 12, 15 source electrode 13, 16 drain electrode 18 isolation region 25 p-InGaP carrier supply layer 26 p-GaAs cap layer 27 non-p-type region 33, 34 recess

Claims (4)

[Claims] 1. A step of sequentially laminating an intrinsic carrier transit layer (2) and a one conductivity type carrier supply layer (3) on a semiconductor substrate (1), and a step opposite to the opposite conductivity type HEMT formation region (X). The opposite conductivity type HEMT is obtained by ion-implanting conductivity type impurities.
Forming the one-conductivity type carrier supply layer (3) in the formation region (X) of the opposite conductivity type carrier supply layer (7), and forming a gate electrode (14) on the opposite conductivity type carrier supply layer (7). ) In Schottky contact with the source electrode (15) and the drain electrode (16) on both sides of the gate electrode (14) to form an opposite conductivity type HEMT, and the opposite conductivity type impurity is ion-implanted. The gate electrode (11) is in Schottky contact on the one-conductivity type carrier supply layer (3) which is not protected, and the source electrode (12) and the drain electrode (13) are ohmic-connected on both sides of the gate electrode (11). And a step of forming one conductivity type HEMT, and a method of manufacturing a compound semiconductor device. 2. When the impurity of the opposite conductivity type is ion-implanted, the acceleration voltage is increased so that the upper layer portion of the carrier supply layer (7) of the opposite conductivity type is maintained at one conductivity type or made intrinsic. The method for manufacturing a compound semiconductor device according to claim 1, wherein 3. Before the ion implantation of the opposite conductivity type impurity, a step of etching the surface of the one conductivity type carrier supply layer (3) in the region where the ion implantation is performed to deplete the surface. The method of manufacturing a compound semiconductor device according to claim 1, wherein 4. A step of sequentially laminating an intrinsic carrier transit layer (2), an n-type carrier supply layer (3) and an n-type cap layer (4) on a semiconductor substrate (1), and a p-type HEMT region ( Thinning the source region and the drain region of the n-type cap layer (3) in (X) to form recesses (33, 34); and the n-type carrier in the p-type HEMT region (X). By implanting p-type impurities into the supply layer (3) and the n-type cap layer (4), the n-type carrier supply layer (3) and the n-type carrier supply layer (3) in the p-type HEMT region (X).
The mold cap layer (4) is made p-type to form a p-type carrier supply layer (7) and a p-type cap layer (8), and
A step of increasing the p-type impurity concentration under the recesses (33, 34); and a gate electrode (14) on the p-type carrier supply layer (7).
In Schottky contact with p on both sides of the gate electrode (14)
Forming a p-type HEMT by ohmic-connecting the source electrode (15) and the drain electrode (16) to the mold cap layer (8), and on the n-type carrier supply layer (3) into which the p-type impurity is not implanted. And forming a n-type HEMT by ohmic-connecting the source electrode (12) and the drain electrode (13) to the n-type cap layer (4) on both sides of the gate electrode by Schottky contact. A method of manufacturing a compound semiconductor device, comprising: