JP2002009253A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method in which an HEMT and a protective diode with decreased leakage current are formed on the same substrate. SOLUTION: A semiconductor device and its manufacturing method, which include a first active element (HEMT) with a channel layer 4, a carrier supply layer 5b, a high resistance layer 5c, a cap layer 6 including a first conductivity type impurity, a source electrode 8, a drain electrode 9 and a gate electrode 10, and a second active element (a protective diode) with a first conductivity type base region 25 consisting of the same layer with the cap layer 6 and including a second conductivity type impurity, a second conductivity type emitter region 21 and a second conductivity type collector region 22 on a substrate 1, are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a heterojunction field effect transistor and a protection diode on the same substrate and a method of manufacturing the same, and more particularly, it is possible to reduce a leakage current of the protection diode. The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art Heterojunction field effect transistors (H
FET; heterojunction field
In effect transformer, current modulation is performed using a heterojunction formed between a carrier traveling layer (channel layer) and a carrier supply layer. HFETs currently being mass-produced use electrons as carriers, and have a high electron mobility transistor (HEMT;
high electron mobility tr
ansistor).

A HEMT is a conventional device, for example, a junction field effect transistor (JFET).
FET) and Schottky junction type field effect transistor (MESFET; metal semiconductor)
or FET). HEM
At T, electrons are accumulated in the channel layer by applying a positive voltage to the gate electrode. Therefore, HEM
T is the gate-source capacitance Cg with respect to the gate voltage Vg as compared with other devices such as JFET and MESFET.
It is characterized in that the linearity of s and the linearity of the transconductance Gm with respect to the gate voltage Vg are high.

On the same substrate as the HEMT as described above,
A protection diode is formed to protect the internal circuit of the integrated circuit from electrostatic destruction. FIG. 8 shows a cross-sectional view of a conventional HEMT and a protection diode formed on the same substrate. As shown in FIG. 8, the semi-insulating Ga
No impurity is added to the As substrate 1 (undop).
ed) A second barrier layer 3, a channel layer 4, and a first barrier layer 5 are sequentially stacked via a buffer layer 2 made of GaAs single crystal.

The second barrier layer 3 is made of a III-V compound semiconductor such as AlGaAs, for example, and has a structure in which a high resistance layer 3a, an electron supply layer 3b and a spacer layer 3c are sequentially laminated. As a material of the high-resistance layer 3a, for example, AlGaAs (undoped-
AlGaAs) is used. As a material of the electron supply layer 3b, for example, AlGaAs (n
-AlGaAs) is used. As a material of the spacer layer 3c, for example, undoped-AlGaAs is used.

As a material of the channel layer 4, a semiconductor having a band gap narrower than that of the second barrier layer 3 and the first barrier layer 5, for example, undoped InGa
As (undoped-InGaAs) is used.
The first barrier layer 5 is made of, for example, a compound semiconductor such as AlGaAs, and has a configuration in which a spacer layer 5a, an electron supply layer 5b, and a high resistance layer 5c are sequentially stacked. As the material of the spacer layer 5a, for example, undoped-AlGaAs is used similarly to the spacer layer 3c. As a material of the electron supply layer 5b, for example, n-AlGaAs is used similarly to the electron supply layer 3b. The material of the high resistance layer 5c is, for example, undoped as in the case of the high resistance layer 3a.
-AlGaAs is used.

[0007] Two cap layers 6 are formed on the first barrier layer 5 at appropriate intervals. As a material of the cap layer 6, for example, GaAs containing silicon as an n-type impurity is used. The cap layer 6 is covered with an insulating film 7 made of, for example, a silicon nitride film.
A source electrode 8 and a drain electrode 9 are formed in an opening provided in the insulating film 7. Also, the first barrier layer 5
A gate electrode 10 is formed thereon. Gate electrode 1
When a voltage is applied to 0, the source electrode 8 and the drain electrode 9
Is modulated.

Although the p-type low-resistance region 11 formed in the high-resistance layer 5c immediately below the gate electrode 10 is not always necessary,
By forming the p-type low resistance region 11, the built-in voltage can be increased as compared with the case where a Schottky junction is formed in the gate electrode portion. Therefore,
A large positive voltage can be applied to the gate electrode. The p-type low resistance region 11 is formed as a p-type impurity such as Z
n is a high concentration (1 × 10 ¹⁹ to 2 × 10 ¹⁹ atoms / c)
containing at m about ^3).

Although not shown, the p-type low resistance region 11
In some cases, a recess may be formed in the high resistance layer 5c below the gate electrode 10 and in the vicinity thereof without forming the first barrier layer 5 to partially reduce the thickness of the first barrier layer 5. In a HEMT having a structure having such a recess, carriers (electrons) in the channel layer 4 immediately below the gate electrode 10 are easily depleted.
By controlling the depth of the recess to be formed, the threshold voltage of the transistor is adjusted.

On the other hand, in the protection diode portion indicated by pnp in FIG.
And a p-type collector region 22 is formed. An emitter electrode 23 and a collector electrode 24 are formed on the upper portions thereof, respectively. In the protection diode, the HEMT cap layer 6 is used as an n-type base region. An element isolation region 12 containing a p-type impurity is formed between the HEMT and the protection diode.

[0011]

In the conventional semiconductor device described above, in order to obtain an ohmic contact with the source electrode 8 and the drain electrode 9 in the HEMT portion, the cap layer 6 needs to have, for example, at least 6 × 10 ¹⁸ atoms / cm ^3. Of n-type impurities. However, according to the above-described conventional structure, since the cap layer 6 is used as the n-type base region of the protection diode, the n-type base region has an excessive n-type impurity concentration. As a result, there is a problem that the leakage current of the protection diode is large, which hinders the reduction in power consumption of the semiconductor device.

The present invention has been made in view of the above problems, and accordingly, the present invention provides a semiconductor device having a HEMT and a protection diode with reduced leakage current on the same substrate, and a method of manufacturing the same. The purpose is to do.

[0013]

In order to achieve the above object, a semiconductor device according to the present invention comprises a first active element, a second active element, a first active element, and a second active element on a substrate. 2
A first active element, wherein the first active element comprises a channel layer formed on the substrate, and a carrier and a conductive layer formed on the channel layer. A carrier supply layer containing a first conductivity type impurity having the same type, a high resistance layer formed on the carrier supply layer, and a first resistance layer formed on the high resistance layer at a predetermined interval. Two cap layers containing a conductive impurity, a source electrode formed on one of the cap layers, a drain electrode formed on the other of the cap layers, and between the source electrode and the drain electrode. The second active element is formed of the same layer as the cap layer, and further includes a first conductivity type base region further containing a second conductivity type impurity. And the first guide And having a mold base a second conductivity type emitter region formed at predetermined intervals in a surface region and a second conductivity type collector region.

In the semiconductor device according to the present invention, preferably, the concentration of the second conductivity type impurity in the cap layer is within a range in which an ohmic contact is formed in the source electrode and the drain electrode. I do. In the semiconductor device of the present invention, preferably, the first active element includes:
A first layer formed between the substrate and the channel layer;
The semiconductor device further includes a second carrier supply layer containing a conductive impurity. The semiconductor device of the present invention is preferably characterized in that the channel layer is made of a semiconductor to which no impurity is added.

Preferably, in the semiconductor device according to the present invention, the carrier supply layer is made of a semiconductor having a wider band gap than a semiconductor forming the channel layer. The semiconductor device of the present invention is preferably arranged such that the second
Is characterized in that the carrier supply layer is made of a semiconductor having a wider band gap than a semiconductor constituting the channel layer. The semiconductor device of the present invention is preferably characterized in that the high-resistance layer has a wider band gap than a semiconductor forming the channel layer and is made of a semiconductor to which no impurity is added.

Preferably, the semiconductor device according to the present invention has a band gap between the channel layer and the carrier supply layer which is wider than that of the semiconductor forming the channel layer and has no impurity added thereto. And a spacer layer comprising: The semiconductor device of the present invention is preferably a semiconductor which has a wider band gap between the channel layer and the second carrier supply layer than a semiconductor forming the channel layer and has no impurity added thereto. And a second spacer layer comprising: Preferably, the semiconductor device of the present invention further includes a buffer layer made of a semiconductor to which no impurity is added, between the substrate and the channel layer.

In the semiconductor device according to the present invention, preferably, the element isolation region is a high resistance region in which impurities are diffused. Alternatively, the semiconductor device of the present invention is preferably characterized in that the element isolation region is a trench formed on the substrate. In the semiconductor device of the present invention, preferably, the substrate, the channel layer, the carrier supply layer, the high resistance layer, and the cap layer are formed of III.
-A group V compound semiconductor layer. The semiconductor device of the present invention is preferably configured such that the substrate, the channel layer, the carrier supply layer, the second carrier supply layer,
The high resistance layer and the cap layer are III-V compound semiconductor layers. The semiconductor device of the present invention is preferably characterized in that the carrier is an electron.

As a result, the impurity concentration of the base region of the second active element becomes lower than the impurity concentration of the cap layer of the first active element, and the leak current in the second active element is reduced. Therefore, power consumption of the semiconductor device can be reduced. Further, in the semiconductor device of the present invention, by using the second active element as a protection diode, a circuit including the first active element is prevented from being damaged by static electricity.

Further, in order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention, comprises the steps of: providing a first active element, a second active element, the first active element and the second active element on a substrate;
Forming a channel layer on the substrate, and forming a channel layer on the substrate, wherein the carrier and the carrier have the same conductivity type. Forming a carrier supply layer containing one conductivity type impurity, forming a high resistance layer on the carrier supply layer, and forming a semiconductor layer containing first conductivity type impurity on the high resistance layer Forming a first conductivity type base layer by diffusing a second conductivity type impurity into the semiconductor layer in the second active element formation region; forming the device isolation region; Removing a part of the semiconductor layer in a first active element formation region to form two cap layers made of the semiconductor layer;
Forming a second conductivity type emitter region and a second conductivity type collector region on the surface layer of the conductivity type base layer; and forming a gate electrode on the high resistance layer between the two cap layers. Forming a source electrode on the cap layer and forming a drain electrode on the other cap layer.

In the method of manufacturing a semiconductor device according to the present invention, preferably, the step of forming the first conductivity type base layer includes a step of ion-implanting a second conductivity type impurity. In the method of manufacturing a semiconductor device according to the present invention, preferably, the step of forming the channel layer, the carrier supply layer, the high resistance layer, and the semiconductor layer includes forming the channel by metal organic chemical vapor deposition (MOCVD). A step of epitaxially growing the layer, the carrier supply layer, the high resistance layer, and the semiconductor layer.

This makes it possible to form a heterojunction field effect transistor (first active element) and a protection diode (second active element) with reduced leakage current on the same substrate. According to the method of manufacturing a semiconductor device of the present invention, it is only necessary to add, for example, an ion implantation step to the conventional manufacturing method, and it is not necessary to significantly change the process.

[0022]

Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1A is a sectional view of a semiconductor device of this embodiment. As shown in FIG. 1A, the semiconductor device of the present embodiment has an n-type base layer 25 in the protection diode portion, and the n-type impurity concentration of the n-type base layer 25 is lower than that of the cap layer 6 in the HEMT portion. Is low. This reduces the leakage current of the protection diode formed on the same substrate as the HEMT.

Hereinafter, the structure of the semiconductor device of this embodiment shown in FIG. 1A will be described in detail. In the HEMT portion, a second barrier layer 3, a channel layer 4, and a first barrier layer are formed on a semi-insulating GaAs substrate 1 via a buffer layer 2 made of undoped GaAs single crystal. 5 are sequentially stacked.

The semi-insulating GaAs substrate 1 contains almost no impurities and is made of, for example, a single crystal having a resistivity of about 10 ⁶ to 10 ⁸ Ω · cm. The semi-insulating GaAs substrate 1 is a bulk crystal and contains many lattice defects such as point defects and dislocations.
Therefore, when an epitaxial layer is grown on the semi-insulating GaAs substrate 1, a high-quality crystal is not obtained. To prevent this, a buffer layer 2 is provided on a semi-insulating GaAs substrate 1.

The second barrier layer 3 is made of, for example, Al _x Ga _{1 -x} A
It is made of a III-V compound semiconductor such as an s mixed crystal and has a configuration in which a high resistance layer 3a, an electron supply layer 3b, and a spacer layer 3c are sequentially laminated. Al _x as the second barrier layer 3
In the case of using Ga _1-x As mixed crystal, the Al composition ratio x
Is 0.2 to 0.3.

The material of the high resistance layer 3a is, for example, AlGaAs (undoped-A
1GaAs) is used. The high resistance layer 3 a is provided mainly for the same purpose as the buffer layer 2. That is, by forming the high resistance layer 3a, a favorable crystal state can be obtained at the heterojunction interface.

The material of the electron supply layer 3b is, for example, n
-Type impurity-containing AlGaAs (n-AlGaAs)
Is used. The electron supply layer 3b is made of, for example, silicon as an n-type impurity at 1.0 × 10 ^{12 to} 2.0 × 10 ¹² atoms.
This is a layer to which about s / cm ² has been added, and electrons generated from the electron supply layer 3b move to the junction interface with the channel layer 4 to form a channel and serve as a current path.

As a material of the spacer layer 3c, for example, undoped-AlGaAs is used. The spacer layer 3c is provided for the purpose of making the space separation between the electron supply layer 3b and the channel layer 4 more strict. Electron supply layer 3b
Contains a high concentration of impurities, so that a part of the potential of the impurities affects adjacent layers. An extremely thin spacer layer 3c is formed between the electron supply layer 3b and the channel layer 4 in order to prevent the scattering of impurities due to the reduction in electron mobility.

As a material of the channel layer 4, a semiconductor having a band gap narrower than that of the second barrier layer 3 and the first barrier layer 5, for example, In _x G to which no impurity is added is used.
a _1-x As (undoped-InGaAs) mixed crystal is used. Usually, the InGaAs mixed crystal has a higher electron mobility than the AlGaAs mixed crystal, and high-speed electron transfer is possible by using InGaAs as the channel layer 4. When an In _x Ga _{1 -x} As mixed crystal is used as the channel layer 4, the composition ratio x of In is usually 0.1 to 0.2. The channel layer 4 is formed to be extremely thin, has no degree of freedom of electron movement in the direction perpendicular to the bonding surface, and exhibits the properties of a two-dimensional electron gas (2DEG).

The first barrier layer 5 is made of, for example, Al _x Ga _{1 -x} A
It is made of a III-V compound semiconductor such as s mixed crystal, and has a configuration in which a spacer layer 5a, an electron supply layer 5b, and a high resistance layer 5c are sequentially laminated. Al _x as the first barrier layer 5
In the case of using Ga _1-x As mixed crystal, the Al composition ratio x
Is 0.2 to 0.3. The material of the spacer layer 5a is, for example, undoped as in the case of the spacer layer 3c.
-AlGaAs is used. Like the spacer layer 3c, the potential of the high concentration impurity contained in the electron supply layer 5b infiltrates the channel layer 4 in the spacer layer 5a,
It is provided for the purpose of preventing scattering of electrons.

As a material of the electron supply layer 5b, for example, n-AlGaAs is used similarly to the electron supply layer 3b.
The electron supply layer 5b is a layer to which, for example, silicon is added at about 1.0 × 10 ^{12 to} 2.0 × 10 ¹² atoms / cm ² as an n-type impurity, and electrons generated from the electron supply layer 5b It moves to the junction interface to form a channel and becomes a current path.

As a material of the high resistance layer 5c, the high resistance layer 3
As in the case of a, for example, undoped-AlGaAs is used. With miniaturization of semiconductor devices, the distance between a gate, a source, and a drain has been reduced. As a result, there is a problem that the breakdown voltage between the gate and the source or between the gate and the drain is reduced. For the purpose of ensuring these breakdown voltages, a high resistance layer 5c is provided. Further, by forming the high resistance layer 5c, the electron supply layer 5b containing impurities at a high concentration is formed.
And the space separation from the upper cap layer 6 is more strictly performed.

On the first barrier layer 5, two cap layers 6 are formed at appropriate intervals. As a material of the cap layer 6, for example, GaAs containing silicon as an n-type impurity is used. For example, 6 ×
By including a high concentration of n-type impurity of 10 ¹⁸ atoms / cm ³ or more, an ohmic contact between the source electrode 8 and the drain electrode 9 can be obtained.

The cap layer 6 is covered with an insulating film 7 made of, for example, a silicon nitride film. A source electrode 8 and a drain electrode 9 are formed in an opening provided in the insulating film 7. The source electrode 8 and the drain electrode 9 have a configuration in which Ni is stacked on an Au—Ge alloy. Further, a gate electrode 10 is formed on the first barrier layer 5. The gate electrode 10 is made of Ti, Pt from the substrate side.
And Au are sequentially laminated. In the above-mentioned HEMT, the channel layer 4 serves as a current path between the source electrode 8 and the drain electrode 9. When a voltage is applied to the gate electrode 10, a current flowing between the source electrode 8 and the drain electrode 9 is modulated.

Although the p-type low-resistance region 11 formed in the high-resistance layer 5c immediately below the gate electrode 10 is not always necessary,
By forming the p-type low resistance region 11, the built-in voltage can be increased as compared with the case where a Schottky junction is formed in the gate electrode portion. Therefore,
A large positive voltage can be applied to the gate electrode. The p-type low resistance region 11 is formed as a p-type impurity such as Z
n is a high concentration (1 × 10 ¹⁹ to 2 × 10 ¹⁹ atoms / c)
containing at m about ^3).

On the other hand, a semi-insulating GaAs is provided in the protection diode portion indicated by pnp in FIG.
A buffer layer 2, a second barrier layer 3, a channel layer 4, and a first barrier layer 5 are sequentially laminated on an s substrate 1. Also,
Like the HEMT portion, the second barrier layer 3 is a high resistance layer 3a.
And an electron supply layer 3b and a spacer layer 3c which are sequentially stacked on the upper layer. The first barrier layer 5 has a spacer layer 5a, and an electron supply layer 5b and a high resistance layer 5c sequentially stacked thereover.

An n-type base region 25 having an n-type impurity concentration lower than that of the cap layer 6 of the HEMT is formed above the high resistance layer 5c. As the n-type base region 25,
For example, a region in which, for example, boron is diffused as a p-type impurity in a GaAs layer containing silicon as an n-type impurity is used. A p-type emitter region 21 and a p-type collector region 22 are formed on the surface layer of n-type base region 25.

The protection diode portion is also covered with the insulating film 7 like the HEMT portion. An opening is formed in the insulating film 7 above the p-type emitter region 21, and an emitter electrode 23 is formed in the opening. Similarly, an opening is formed in the insulating film 7 above the p-type collector region 22, and a collector electrode 24 is formed in the opening. An element isolation region 12 containing a p-type impurity is formed between the HEMT and the protection diode.

Next, a method of manufacturing the semiconductor device of the present embodiment will be described. First, as shown in FIG. 1A, on a semi-insulating GaAs substrate 1, undoped-AlG is deposited by, for example, metal organic chemical vapor deposition (MOCVD).
The buffer layer 2 is formed by epitaxially growing aAs, for example, to a thickness of 200 nm.

On the upper layer of the buffer layer 2, for example, MOCV
Undoped-AlGaAs is epitaxially grown to a thickness of, for example, 50 nm by Method D to form a high-resistance layer 3a. On top of this, n-Al is formed by MOCVD, for example.
GaAs is epitaxially grown, for example, to a thickness of 3 nm,
The electron supply layer 3b is formed. On top of that, for example, MOC
Undoped-AlGaAs is epitaxially grown to a thickness of, for example, 2 nm by a VD method to form a spacer layer 3c. Thereby, a second barrier layer 3 is formed.

On the spacer layer 3c of the second barrier layer 3, an undoped-InG layer is formed by MOCVD, for example.
aAs is epitaxially grown, for example, to a thickness of 15 nm,
The channel layer 4 is formed. On the upper layer of the channel layer 4, for example, an undoped-AlGaAs is epitaxially grown to a thickness of, for example, 2 nm by MOCVD to form a spacer layer 5a. On the upper layer, n-AlGaAs is epitaxially grown to a thickness of, for example, 6 nm by MOCVD, for example, to form an electron supply layer 5b. On top of that,
For example, undoped-AlGaAs by MOCVD method
For example, s is epitaxially grown to a thickness of 80 nm to form a high-resistance layer 5c. Thereby, a first barrier layer 5 is formed.

On the high resistance layer 5 c of the first barrier layer 5,
GaAs containing high concentration of silicon as n-type impurity
(N ⁺ -GaAs) is epitaxially grown to a thickness of about 50 nm by, for example, the MOCVD method to form the cap layer 6. The n-type impurity concentration of the cap layer 6 is, for example, 6 ×
It is 10 ¹⁸ atoms / cm ³ .

Next, as shown in FIG. 2C, a photoresist is applied on the cap layer 6, and the photoresist is exposed and developed by a photolithography process.
A photoresist 13 having an opening in a protection diode formation region is formed. Using the photoresist 13 as a mask, for example, boron is ion-implanted as a p-type impurity into the cap layer 6 in the protection diode formation region. Thus, the n-type impurity concentration of the cap layer 6 in the protection diode formation region is reduced to, for example, about 2 × 10 ¹⁸ atoms / cm ³ , and the n-type base region 25 is formed. Thereafter, the photoresist 13 is removed by, for example, plasma ashing.

Next, as shown in FIG. 2D, a photoresist is applied on the cap layer 6 or the n-type base region 25, and the photoresist is exposed and developed by a photolithography process to form an element isolation region. A photoresist 14 having an opening in a formation region of the photoresist 12 is formed. Using the photoresist 14 as a mask, for example, boron is ion-implanted as a p-type impurity into the cap layer 6 in the element isolation region.

This ion implantation is performed with a larger dose than the ion implantation for forming the n-type base region 25.
Alternatively, instead of boron ion implantation, a high-resistance region is formed by ion implantation of oxygen to form an element isolation region 12.
It can also be. Thereafter, the photoresist 14 is removed by, for example, plasma ashing.

Next, as shown in FIG.
Part of the cap layer 6 is removed by etching,
The high resistance layer 5c is exposed. To etch the cap layer 6, first, a photoresist (not shown) is applied on the cap layer 6, and the photoresist is exposed and developed by a photolithography process to form an opening in the gate electrode formation region and its vicinity. Is formed. Subsequently, the cap layer 6 is etched using the photoresist as a mask by immersion in an etching solution such as citric acid. Thereafter, the photoresist is removed by, for example, plasma ashing.

Next, as shown in FIG. 3F, an insulating film 7 is formed on the entire surface of the substrate by depositing, for example, a 300 nm silicon oxide film by, for example, a plasma CVD method. Next, as shown in FIG. 4G, an opening is formed in the insulating film 7 in the gate electrode formation region of the HEMT. At this time, openings are also formed in the insulating film 7 in the emitter electrode forming region and the collector electrode forming region of the protection diode.

In order to form these openings, first, a photoresist (not shown) is applied on the insulating film 7, and the photoresist is exposed and developed by a photolithography process to form openings in the opening forming region. Is formed. Subsequently, reactive ion etching (RIE; reactive ion etching) using a photoresist as a mask and using, for example, a CF ₄ -based gas.
g), the insulating film 7 is subjected to anisotropic etching. After that, the photoresist is removed.

Next, as shown in FIG.
The p-type impurity is diffused into the high-resistance layer 5c in the HEMT portion through the opening formed in the first region to form the p-type low-resistance region 11. At this time, the n-type base layer 25 of the protection diode
The p-type impurity is also diffused through the opening formed in the insulating film 7 to form the p-type emitter region 21 and the p-type collector region 22 also in the surface layer of.

The p-type low resistance region 11 and the p-type emitter region 2
In order to form the 1 and p-type collector regions 22, for example, Zn as a p-type impurity is vapor-phase diffused at about 600 ° C. For gas phase diffusion of Zn, for example, diethyl zinc (DE
Z: A gas containing Zn (C ₂ H ₅ ) ₂ ) and arsine (AsH ₃ ) is used. Diethyl zinc is an organic metal that is liquid at room temperature, and becomes a gas by bubbling high-purity hydrogen as a carrier gas. By heating the substrate in a gas atmosphere containing diethyl zinc and arsine, Zn is vapor-phase diffused into the substrate. Organic zinc other than diethyl zinc, such as dimethyl zinc (DMZ; Zn (CH ₃ ) ₂ ), can also be used as a Zn diffusion source.

Next, as shown in FIG. 5I, a laminated film 15 of Ti / Pt / Au is formed on the entire surface of the substrate. By performing the etching in the subsequent step, the multilayer film 15 becomes HEMT.
Gate electrode 10 and the emitter electrode 2 of the protection diode
3 and the collector electrode 24. As the laminated film 15, for example, a Ti layer having a thickness of 30 nm and a P layer having a thickness of 50 nm are used.
A t layer and a 120 nm thick Au layer are sequentially deposited by electron beam evaporation.

Next, as shown in FIG.
5 is etched using a photoresist (not shown) as a mask to form a gate electrode 10, an emitter electrode 23, and a collector electrode 24. This etching can be performed by, for example, ion milling using argon gas.

Next, as shown in FIG. 6K, the insulating film 7 in the source electrode formation region and the drain electrode formation region is selectively etched to form an opening. continue,
As shown in FIG. 6 (l), for example, an Au—Ge alloy and Ni are sequentially deposited on the entire surface including the inside of the opening to form the laminated film 1.
6 is formed. Thereafter, as shown in FIG. 1A, the stacked film 16 is etched to form the source electrode 9 and the drain electrode 10. Further, for example, a heat treatment at about 400 ° C. is performed to alloy the Au—Ge alloy and Ni. Through the above steps, the semiconductor device of the present embodiment shown in FIG. 1A is obtained.

The semiconductor device of the present embodiment described above has a HEM
Although a p-type low-resistance region 11 is provided immediately below the gate electrode 10 of T, the p-type low-resistance region 11 is not formed, and the gate electrode 10
Forming a recess in the lower part and the high resistance layer 5c near the lower part,
The thickness of the first barrier layer 5 may be partially reduced. In a HEMT having a structure having such a recess, carriers (electrons) in the channel layer 4 immediately below the gate electrode 10 are easily depleted. By controlling the depth of the recess to be formed, the threshold voltage of the transistor can be adjusted.

(Embodiment 2) FIG. 7 is a sectional view of a semiconductor device of this embodiment. As shown in FIG. 7, the semiconductor device of the present embodiment is similar to the semiconductor device of the first embodiment,
The protection diode portion (the portion indicated by pnp in FIG. 7) has an n-type base layer 25, and the n-type base layer 25 has an n-type impurity concentration lower than that of the cap layer 6 in the HEMT portion. This reduces the leakage current of the protection diode formed on the same substrate as the HEMT. The semiconductor device according to the present embodiment includes a trench 1 formed by mesa etching between a HEMT portion and a protection diode portion.
The trench 17 separates the elements.

The semiconductor device of the present embodiment is similar to the semiconductor device of the first embodiment in that the HE device on the semi-insulating GaAs substrate 1
The buffer layer 2, the second barrier layer 3, the channel layer 4, and the first barrier layer 5 have a structure in which the MT layer and the protection diode portion are commonly stacked. The second barrier layer 3 has a configuration in which three layers of a high resistance layer 3a, an electron supply layer 3b, and a spacer layer 3c are sequentially stacked. The first barrier layer 5 includes a spacer layer 5a, an electron supply layer 5b, and a high resistance layer 5c.
Are sequentially laminated.

A cap layer 6 containing an n-type impurity at a high concentration is formed on the high resistance layer 5c in the HEMT portion. A source electrode 8 and a drain electrode 9 are formed on the cap layer 6. A gate electrode 10 is formed on the high resistance layer 5c between the source electrode 8 and the drain electrode 9. A p-type low-resistance region 11 in which a p-type impurity is diffused is formed in the high-resistance layer 5c immediately below the gate electrode 10.

On the other hand, the high resistance layer 5c of the protection diode portion
On top, n having an n-type impurity concentration lower than that of the cap layer 6 is formed.
A mold base layer 25 is formed. The p-type emitter region 21 and the p-type collector region 2 are formed on the surface of the n-type base layer 25.
2 are formed. An emitter electrode 23 is formed above the p-type emitter region 21, and a collector electrode 24 is formed above the p-type collector region 22.

As shown in FIG. 7, a trench 17 is formed as an element isolation region in the second barrier layer 3, the channel layer 4, the first barrier layer 5, and the cap layer 6 between the HEMT portion and the protection diode portion. Have been. The upper part of the cap layer 6 in the HEMT portion and the n-type base layer 25 of the protection diode and the inside of the trench 17 are covered with an insulating film 7 made of, for example, a silicon nitride film.

In order to form the semiconductor device of the present embodiment, first, as in the first embodiment, as shown in FIG. 1B, a buffer layer 2 is formed on a semi-insulating GaAs substrate 1, The layer 3a, the electron supply layer 3b, the spacer layer 3c, the channel layer 4, the spacer layer 5a, the electron supply layer 5b, the high resistance layer 5c, and the cap layer 6 are laminated. Subsequently, FIG.
As shown in (c), ions of a p-type impurity are selectively implanted into the cap layer 6 in the protection diode portion to form an n-type base layer 25.

Next, the cap layer 6, high resistance layer 5c, electron supply layer 5b, between the HEMT portion and the protection diode portion,
A spacer layer 5a, a channel layer 4, a spacer layer 3c,
Mesa etching is performed on the electron supply layer 3b, the high resistance layer 3a, and the buffer layer 2. Thus, a trench 17 is formed. This mesa etching is performed to a depth at which at least a part of the buffer layer 2 is removed. As shown in FIG. 7, the bottom of the trench 17 may reach the semi-insulating GaAs substrate 1.

Thereafter, as in the first embodiment, a part of the cap layer 6 in the HEMT portion (the gate electrode formation region and its vicinity) is removed. Further, an insulating film 7 made of, for example, a silicon nitride film is formed above the cap layer 6 in the HEMT portion and the n-type base layer 25 of the protection diode and in the trench 17. Openings are formed in the insulating film 7 in the gate electrode formation region, the emitter electrode formation region, and the collector electrode formation region. A p-type impurity is diffused through these openings to form a p-type low resistance region 11, a p-type emitter region 21, and a p-type collector region 22. After that, the gate electrode 10, the emitter electrode 23 and the collector electrode 24 are formed, and then the source electrode 8 and the drain electrode 9 are formed. Through the above steps, the semiconductor device of the present embodiment is obtained.

According to the semiconductor device of the embodiment of the present invention, the n-type impurity concentration of the n-type base layer 25 of the protection diode is reduced as compared with the conventional structure, so that the leakage current of the protection diode is reduced. be able to. Embodiments of the semiconductor device and the method for manufacturing the same of the present invention are not limited to the above description. For example, the composition of the compound semiconductor constituting the HEMT, the thickness of each layer, and the like can be appropriately changed.

On the semi-insulating GaAs substrate 1, at least a channel layer 4, an electron supply layer 5b and a high resistance layer 5c as a first barrier layer, a cap layer 6, and a gate electrode 10
, Ie, the second barrier layer 3
The present invention can be applied to a case where is not formed. In addition, various changes can be made without departing from the gist of the present invention.

[0065]

According to the semiconductor device of the present invention, the HEMT is provided.
It is possible to reduce the leakage current of the protection diode formed on the same substrate. Further, according to the method of manufacturing a semiconductor device of the present invention, it is possible to form a protection diode with reduced leakage current on the same substrate as a HEMT.

[Brief description of the drawings]

FIG. 1A is a sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 1B shows Embodiment 1 of the present invention.
13 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to FIG.

FIGS. 2C and 2D are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIGS. 3E and 3F are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 4G and FIG. 4H are cross-sectional views showing the manufacturing steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIGS. 5 (i) and 5 (j) are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to Embodiment 1 of the present invention.

FIGS. 6 (k) and 6 (l) are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 8 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semi-insulating GaAs substrate, 2 ... Buffer layer, 3 ... Second barrier layer, 3a ... High resistance layer, 3b ... Electron supply layer, 3c
... spacer layer, 4 ... channel layer, 5 ... first barrier layer,
5a: spacer layer, 5b: electron supply layer, 5c: high resistance layer, 6: cap layer, 7: insulating film, 8: source electrode, 9
... Drain electrode, 10 ... Gate electrode, 11 ... P-type low resistance area, 12 ... Element isolation area, 13, 14 ... Photoresist, 15, 16 ... Laminated film, 17 ... Trench (element isolation area), 21 ... P-type Emitter region, 22 ... p-type collector region, 23 ... emitter electrode, 24 ... collector electrode, 25 ...
n-type base layer.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/812 H01L 29/90 S // H01L 29/866 F term (Reference) 5F102 GA14 GB01 GC01 GD01 GD04 GJ05 GK05 GL04 GM06 GN05 GQ03 GR04 GR07 GS02 GS04 GT03 GV07 HC01 HC07 HC11

Claims (18)

[Claims] 1. A semiconductor device having a first active element, a second active element, and an element isolation region separating the first active element and the second active element on a substrate. A first active element, a channel layer formed on the substrate, a carrier supply layer formed on the channel layer and containing a first conductivity type impurity having the same conductivity type as a carrier; A high-resistance layer formed on the carrier supply layer; and a first high-resistance layer formed on the high-resistance layer at a predetermined interval.
Two cap layers containing a conductive impurity, a source electrode formed on one of the cap layers, a drain electrode formed on the other of the cap layers, and between the source electrode and the drain electrode. The second active element is made of the same layer as the cap layer, and the first conductive type base region further contains a second conductive type impurity. And a second conductivity type emitter region and a second conductivity type collector region formed at predetermined intervals in a surface layer of the first conductivity type base region. 2. The semiconductor device according to claim 1, wherein the concentration of the second conductivity type impurity in the cap layer is within a range where an ohmic contact is formed in the source electrode and the drain electrode. 3. The semiconductor according to claim 1, wherein said first active element further includes a second carrier supply layer containing a first conductivity type impurity formed between said substrate and said channel layer. apparatus. 4. The semiconductor device according to claim 1, wherein said channel layer is made of a semiconductor to which no impurity is added. 5. The semiconductor device according to claim 1, wherein said carrier supply layer is made of a semiconductor having a wider band gap than a semiconductor constituting said channel layer. 6. The semiconductor device according to claim 3, wherein said second carrier supply layer is made of a semiconductor having a wider band gap than a semiconductor forming said channel layer. 7. The semiconductor device according to claim 1, wherein said high-resistance layer has a wider band gap than a semiconductor forming said channel layer, and is made of a semiconductor to which impurities are not added. 8. The semiconductor device according to claim 1, further comprising a spacer layer between the channel layer and the carrier supply layer, the spacer layer having a wider band gap than a semiconductor forming the channel layer and made of a semiconductor to which impurities are not added. 2. The semiconductor device according to 1. 9. A second spacer made of a semiconductor having a wider band gap than a semiconductor forming the channel layer between the channel layer and the second carrier supply layer and having no impurity added thereto. 4. The semiconductor device according to claim 3, further comprising a layer. 10. A layer between the substrate and the channel layer,
2. The semiconductor device according to claim 1, further comprising a buffer layer made of a semiconductor to which no impurities are added. 11. The semiconductor device according to claim 1, wherein said element isolation region is a high resistance region in which impurities are diffused. 12. The semiconductor device according to claim 1, wherein said element isolation region is a trench formed on said substrate. 13. The semiconductor device according to claim 13, wherein said substrate, said channel layer, said carrier supply layer, said high resistance layer and said cap layer are formed of III.
The semiconductor device according to claim 1, wherein the semiconductor device is a group V compound semiconductor layer. 14. The semiconductor device according to claim 3, wherein said substrate, said channel layer, said carrier supply layer, said second carrier supply layer, said high resistance layer and said cap layer are III-V compound semiconductor layers. . 15. The semiconductor device according to claim 1, wherein said carriers are electrons. 16. Manufacturing of a semiconductor device in which a first active element, a second active element, and an element isolation region separating the first active element and the second active element are formed on a substrate. Forming a channel layer on the substrate; forming a carrier supply layer containing a first conductivity type impurity having the same conductivity type as a carrier on the channel layer; Forming a high resistance layer on the supply layer; forming a semiconductor layer containing a first conductivity type impurity on the high resistance layer; and forming the semiconductor layer in the second active element formation region on the high resistance layer. Diffusing a second conductivity type impurity to form a first conductivity type base layer; forming the device isolation region; removing a part of the semiconductor layer in the first active device formation region; Two cap layers made of the semiconductor layer Forming; forming a second conductivity type emitter region and a second conductivity type collector region on a surface layer of the first conductivity type base layer; and forming a gate on the high resistance layer between the two cap layers. A method of manufacturing a semiconductor device, comprising: forming an electrode; and forming a source electrode on one of the cap layers and forming a drain electrode on the other of the cap layers. 17. The method according to claim 16, wherein the step of forming the first conductivity type base layer includes a step of ion-implanting a second conductivity type impurity. 18. The channel layer, the carrier supply layer,
The step of forming the high resistance layer and the semiconductor layer is performed by a metal organic chemical vapor deposition (MOCVD) method.
ganic chemical vapor depo
17. The method of manufacturing a semiconductor device according to claim 16, further comprising the step of epitaxially growing the channel layer, the carrier supply layer, the high resistance layer, and the semiconductor layer by means of a position.