JPH06151473A - Compound semiconductor element and its manufacture - Google Patents

Abstract

PURPOSE:To provide such a compound semiconductor element, and its manufacturing method, that the change or fluctuation of its characteristics which usually occurs due to deep levels or surface levels can be suppressed. CONSTITUTION:In the element, a substrate voided region 34 is provided by removing a GaAs substrate from a region including at least the region 32 immediately below an active layer 30 grown to a crystal of 1,000Angstrom in thickness. The region 34 is provided with a semi-insulating layer 38 and a rear electrode 40 is provided below the layer 38.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device having an active layer on a semi-insulating compound semiconductor layer and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, when manufacturing a compound semiconductor device such as a gallium arsenide field effect transistor (GaAsFET), an active layer is generally formed on a compound semiconductor substrate.

A conventional example of GaAs will now be described with reference to the drawings.
A method of manufacturing the FET will be described. (A) of FIG.
FIG. 3D is a process diagram of a conventional GaAs FET manufacturing method. Each drawing is a cross-sectional view of a semiconductor device in a main process step.

First, a high-purity GaAs layer as a buffer layer 12 which is an undoped layer in which impurities are not doped is formed on the GaAs substrate 10 at several 1000 A ° (several 100 n).
m) (however, A ° represents angstrom) to several μm
Grow to a thickness of. This buffer layer 12 is made of GaAs
It is provided to prevent defects such as dislocations existing in the substrate 10 from diffusing into the active layer 14 described later.

Next, an N-type GaAs layer 14 is grown as an active layer 14 on the buffer layer 12, and then an element isolation ion implantation section 16 is provided ((A) of FIG. 10).

After that, the gate electrode 18 is formed on the active layer 14,
A drain electrode 20 and a source electrode 22 are provided to form a transistor structure (FIG. 10B). An actual semiconductor element has an interlayer insulating film and a wiring metal as a multilayer wiring structure, and a surface protective film is provided on the surface of the element (not shown).

Next, the substrate 10 is polished from the back surface (the surface on the back side of the substrate on which the transistor structure is formed) of the substrate to a thickness of 100 to 300 μm (FIG. 10C).

After polishing, the back surface electrode 24 is formed on the back surface of the substrate 10a.
To form. By forming the back surface electrode 24, the potential on the back surface side of the substrate of the semiconductor element can be fixed ((D) in FIG. 10).

The conductivity type of the GaAs substrate may be any of N type, P type and semi-insulating property, but the semi-insulating conductivity type substrate is applied to an integrated circuit including a transistor. Widely used in. This is because the semi-insulating substrate has a high resistivity of about 10 ⁷ to 10 ⁸ Ω · cm. Therefore, the use of the semi-insulating substrate increases the breakdown voltage between the active layer of the semiconductor element and the substrate. In addition, it is possible to exhibit excellent element isolation characteristics and further suppress the parasitic capacitance to the ground such as wiring.

Conventionally, in order to make a semi-insulating substrate have a high resistivity, it is usual that a shallow donor or shallow acceptor with a level of residual impurities in the substrate is replaced with a deep donor or a deep donor due to a crystal defect or intentionally added impurities. By compensating with the acceptor, the Fermi level is fixed at the center of the band gap.

For example, in an undoped semi-insulating GaAs substrate that has been bulk-grown by using the liquid sealing pulling method, a shallow acceptor due to residual impurities such as carbon (C) is generated by E.
Compensation is performed at a deep level near the center of the band gap called L2. Further, in the semi-insulating substrate to which chromium (Cr) is added, the shallow donor due to the residual silicon is compensated by chromium which is a deep acceptor.

Therefore, in the semi-insulating substrate, deep levels with various energy levels exist in various concentrations.

Usually, a conventional compound semiconductor device has a semi-insulating substrate in a region immediately below an active layer. In this substrate, deep levels with various energy levels are present at various concentrations depending on the type of substrate, pre-crystal growth treatment, or treatment conditions after crystal growth and post-growth. In addition, at the interface between the semi-insulating substrate formed by bulk growth and the growth layer formed by crystal growth on the semi-insulating substrate, the type of substrate,
The interface states of various energy levels exist in various concentrations depending on the crystal plate growth pretreatment or the crystal growth conditions. When these levels act as traps for electrons and holes, carriers are trapped in these levels. The number of captured carriers changes depending on the voltage applied to the device and the carrier concentration. In addition, there is a unique time constant in the process of carrier capture or emission at each level.

As a result, the device characteristics may be changed or fluctuated due to the deep level or the interface level. For example, in the case of an FET element using a semi-insulating substrate,
Change in threshold current due to deep levels or interface states,
The transient response of the drain current and drain conductance, the variation of the dependency of the drain current and drain conductance on the frequency of the signal applied to the element, or the variation or variation of the element characteristics such as the side gate effect may occur.

Therefore, when the compound semiconductor element is formed using the semi-insulating substrate, it is desirable that the above-mentioned change or fluctuation of the element characteristic does not occur.

[0016]

However, when bulk-growing a semi-insulating substrate, it is extremely difficult to control the energy level and concentration of deep levels while maintaining high resistivity. It is also extremely difficult to control the energy levels and concentrations of deep levels and interface levels of the semi-insulating substrate after the device having the semi-insulating substrate is constructed. Therefore, the above-mentioned change or fluctuation of the element characteristic occurs.

Therefore, an object of the present invention is to provide a compound semiconductor device capable of suppressing a change or variation in device characteristics due to a deep level or an interface level in a semi-insulating substrate and a method for manufacturing the same. is there.

[0018]

In order to achieve this object, according to the compound semiconductor device and the method for manufacturing the same of the present invention, in a compound semiconductor device having a crystal-grown active layer, at least immediately below the active layer. Is a substrate-free region, and the substrate-free region is provided with a semi-insulating layer formed using a compound semiconductor grown by crystal growth, and a back electrode is provided under the semi-insulating layer. To do.

Further, in manufacturing a compound semiconductor device, a step of crystal-growing a semi-insulating layer on a substrate, a step of forming an active layer on the upper side of the semi-insulating layer, and a step of forming an active layer at least directly under the active layer. The method is characterized by including a step of removing the substrate to expose the semi-insulating layer and a step of forming a back electrode under the semi-insulating layer.

In manufacturing the compound semiconductor device, a step of crystal-growing a non-doped buffer layer on the substrate, a step of forming an active layer on the buffer layer,
A step of exposing the buffer layer by removing the substrate in a region at least immediately below the active layer; a step of implanting ions into the buffer layer to form a semi-insulating layer; and a back electrode under the semi-insulating layer. And a step of forming.

Preferably, in the method of manufacturing a compound semiconductor device, the crystal growth step of the semi-insulating layer includes a step of sequentially forming a lower semi-insulating layer, an etching stopper layer and an upper semi-insulating layer. And good.

Preferably, in the method of manufacturing a compound semiconductor device, the crystal growth step of the buffer layer may include a step of sequentially forming a lower semi-insulating layer, an etching stopper layer and an upper semi-insulating layer. .

[0023]

According to the compound semiconductor device and the method for manufacturing the same of the present invention, since the substrate formed by bulk growth is removed at least in the region immediately below the active layer, the interface state can be eliminated. Furthermore, since the substrate is removed, it is possible to eliminate changes or fluctuations in semiconductor element characteristics due to deep levels in the substrate, regardless of the type of substrate or the like. Since the semi-insulating layer is formed by crystal growth, the influence of deep levels on the semiconductor device characteristics can be empirically predicted by controlling the crystal growth conditions and ion implantation conditions, regardless of the type of substrate. It can be suppressed within the range of obtaining.

[0024]

Embodiments of the compound semiconductor device and the method of manufacturing the same according to the present invention will be described below with reference to the drawings. It should be noted that the drawings referred to below only schematically show the sizes, shapes, and arrangement relationships of the respective constituent components to the extent that the present invention can be understood. Therefore, it is obvious that the present invention is not limited to the illustrated example.

First Embodiment The first embodiment of the present invention will be described below. FIG. 1 is a sectional view for explaining an embodiment of the present invention. The figure shows
The hatching and the like showing the cross section are partially omitted.

As shown in FIG. 1, the compound semiconductor device of this embodiment comprises an active layer 30 which is crystal-grown to a thickness of 1000 A °. And at least this active layer 30
The GaAs substrate in the region 32 immediately below is removed to form a substrate-free region 34. In the substrate-free region 34, an undoped GaAs buffer layer 36, a semi-insulating layer 38,
A back surface electrode 40 on the lower surface of the semi-insulating layer 38 is provided. The semi-insulating layer 38 is formed using a crystal-grown compound semiconductor. On the other hand, the board-free area 34
Substrate portions 42 formed by bulk growth are left in the regions on both sides of. In addition, isolation regions 46 are provided by implanting ions around the active layer 30. Further, outside the isolation region 46, n which is not an active layer is formed.
-A GaAs layer 48 is formed.

In the above-described embodiment, the semi-insulating layer 38 is provided only in the substrate-free region 34, but in the compound semiconductor device of the present invention, the semi-insulating layer 38 is wider including the substrate-free region 34. It may be provided over the area. Further, in the above-described embodiment, the semi-insulating layer 38 is formed below the active layer 30 via the buffer layer 36. However, in the present invention, the semi-insulating layer 38 is formed above the semi-insulating layer 38 except for the buffer 36. You may provide an active layer directly in.

Second Embodiment Next, a second embodiment of the present invention will be described. Figure 2 (A)
(B) is a first-half process drawing explaining the second embodiment,
3A to 3B are process diagrams of the latter half of FIG. 2B. Each figure schematically shows in cross section the state of the structure obtained in the main process steps. In the figure, hatching and the like showing the cross section are partially omitted.

First, the semi-insulating layer 38 is crystal-grown on the substrate 42. In the second embodiment, on the GaAs substrate 42,
Vanadium (V) -doped GaAs semi-insulating layer 3
8 is epitaxially grown to a thickness of 10 μm by MOCVD. The resistivity of this semi-insulating layer 38 is 10 at room temperature.
It is about ⁸ Ω · cm, which is the same level as the resistivity of a normal semi-insulating substrate. However, the resistivity of the semi-insulating layer 38 can be changed by changing the donor concentration and the acceptor concentration depending on the supply amount of vanadium during crystal growth ((A) in FIG. 2).

Next, the active layer 30 is formed on the upper side of the semi-insulating layer 38.
To form. In the second embodiment, a high-purity undoped GaAs layer 36 is grown to a thickness of 1 μm as a buffer layer 36 on the semi-insulating layer 38, and a high-purity n layer is formed on the active layer 30 as a channel layer of the FET. -Grow the GaAs layer 30 to a thickness of 1000 A °. After that, a separation region 46 for element isolation is formed by implanting oxygen ions by a method similar to the conventional method, and then an FET electrode (gate, drain and source electrode) 44 is formed (FIG. 2).
(B)).

Next, the substrate in the region 32 immediately below the active layer 30 is removed to expose the lower surface of the semi-insulating layer 38. In the second embodiment, mechanical polishing is performed from the back surface side of the substrate 42 to remove the residual 42a having a thickness of several μm. After that, all the remaining substrate 42a including the polishing damage layer including the microcracks generated by the polishing and the substrate 4
A part of the semi-insulating layer 38 grown on 2 is removed by etching to expose the lower surface of the semi-insulating layer 38 to obtain the structure shown in FIG.

Next, the back surface electrode 40 is formed on the exposed lower surface of the semi-insulating layer 38 by an electron beam method or an electroplating method.
Is formed to fix the back surface potential of the element ((B) of FIG. 3).

The compound semiconductor device of this embodiment is manufactured through the above steps.

In the second embodiment, the active layer 30 is grown on the upper side of the semi-insulating layer 38 via the buffer layer 36, but in the present invention, the active layer is grown directly on the semi-insulating layer. May be.

Third Embodiment Next, a third embodiment of the present invention will be described. FIG. 4 (A)
5A to 5B are process diagrams of the first half for explaining the third embodiment, and FIGS. 5A to 5C are process diagrams of the second half following FIG. 4B. Each drawing is a cross-sectional view at the main stage.
In the figure, hatching and the like showing the cross section are partially omitted.

First, the non-doped buffer layer 36 is crystal-grown on the substrate 42. In the third embodiment, a high-purity undoped GaAs layer 36 is directly grown as a buffer layer 36 on the GaAs substrate 42 to a thickness of 10 μm (FIG. 4).
(A)).

Next, the active layer 30 is formed on the buffer layer 36. In the third embodiment, a high-purity n-GaAs is formed on the buffer layer 36 as the active layer 30 which is the channel layer of the FET.
Layer 30 is formed by crystal growth to a thickness of 1000 A °. After that, a separation region 46 for element separation is formed by implanting oxygen ions by a method similar to the conventional method, and then,
The FET electrode 44 is formed ((B) of FIG. 4).

Next, at least the portion of the substrate 42 in the region 32 immediately below the active layer 30 is removed to expose the lower surface of the buffer layer 36. In the third embodiment, mechanical polishing is performed from the back surface side of the substrate 42 to remove the remaining substrate 42a having a thickness of several μm. After that, all the remaining substrate 42a including a polishing damage layer including microcracks generated by polishing and a part of the buffer layer 36 grown on the substrate 42 are removed by etching to expose the buffer layer 36 (FIG. 5 (A)).

Next, the buffer layer 36 is ion-implanted to form a semi-insulating layer 38. In the third embodiment,
From the lower side of the exposed buffer layer 36, for example, hydrogen ions or oxygen ions are implanted to form the semi-insulating layer 38 (FIG. 5B).

Next, the back surface electrode 40 is formed under the semi-insulating layer 38 by using the electron beam method or the electroplating method to fix the back surface potential of the element (FIG. 5C).

The compound semiconductor device of this example is manufactured through the above steps.

Fourth Embodiment Next, a fourth embodiment of the present invention will be described. FIG. 6A
7A to 7C are process diagrams of the first half for explaining the fourth embodiment, and FIGS. 7A to 7B are process diagrams of the second half following FIG. 6C. Each drawing is a cross-sectional view at the main stage.
In the figure, hatching and the like showing the cross section are partially omitted.

First, a semi-insulating layer having an etching stopper layer 50 sandwiched between lower and upper semi-insulating layers 38a and 38b is formed on a substrate. The lower and upper semi-insulating layers 38a and 38b collectively form the semi-insulating layer 38. In the fourth embodiment, a lower semi-insulating layer 38 of GaAs doped with vanadium (V) is formed on a GaAs substrate 42.
A is epitaxially grown to a thickness of several 100 A ° by MOCVD. Next, an AlGaAs layer 50 is formed as an etching stop layer 50 on the lower semi-insulating layer 38a.
Grow to a thickness of 0 A °. Further, an upper semi-insulating layer 38b of vanadium-doped GaAs is grown thereon. ((A) of FIG. 6).

Next, the active layer 30 is formed on the upper side of the upper semi-insulating layer 38b. Therefore, in the fourth embodiment, first, a high-purity undoped GaAs buffer layer 36 is grown to a thickness of 1 μm on the upper semi-insulating layer 38b, and FE is formed thereon.
High-purity n-Ga as the active layer 30 to be the channel layer of T
Crystallize the As layer to a thickness of 1000 A °. After that, a separation region 46 for element separation is formed by implanting oxygen ions by a method similar to the conventional method, and then the FET electrode 44 is formed ((B) of FIG. 6).

Next, the portion of the substrate 42 at least immediately below the active layer 30 is removed to expose the semi-insulating layer 38. In the fourth embodiment, mechanical polishing is performed from the back surface side of the substrate 42 to remove the remaining substrate 42a having a thickness of 100 to 200 μm. Next, the substrate portion 42 obtained by polishing
A mask pattern 54 is formed in a region of the back surface of a at least in a region excluding a region immediately below the active layer by using a normal photolithography technique. Therefore, the opening 52 is formed to expose the region of the substrate portion 42a corresponding to immediately below the active layer ((C) of FIG. 6). In performing this photolithography, using a double-sided mask aligner, the region immediately below the active layer on the front side of the polished substrate and the region of the opening 54 of the mask pattern 52 on the rear side of the residual substrate 42a are aligned (alignment). can do.

Next, reactive ion etching (RI) is performed from the rear surface side of the residual substrate 42a through the mask pattern 52.
Perform E). The etching gas is boron trichloride (BC
l ₃ ), chlorine (Cl ₃ ), and sulfur hexafluoride (SF ₆ ).
The mixed gas of is used. The dry etching is stopped at the etching stop layer 50 to remove the substrate portion corresponding to the opening 54 and the lower semi-insulating layer 38a. Subsequently, with respect to the damage layer (not shown) by dry etching in the etching stop layer 50 and the upper semi-insulating layer 38b,
The upper half-insulating layer 38b is exposed by performing etching to a depth of several tens to several 100 A ° in total for both layers. This 2
By passing through the stepwise etching process, the substrate and other parts are removed so as to make the thickness of the remaining laminated body uniform, thereby obtaining a structure as shown in FIG. 7 (A).

Next, after removing the mask pattern 52,
A back surface electrode 40 is formed mainly under the exposed upper semi-insulating layer 38b by an electron beam method or an electroplating method to fix the back surface potential of the element (FIG. 7B).

A compound semiconductor device is manufactured through the above steps.

Fifth Embodiment Next, a fifth embodiment of the present invention will be described. FIG. 8A
9C are process drawings for explaining the fifth embodiment, and FIG.
8A to 8C are process diagrams of the latter half following FIG. 8C. Each drawing is a cross-sectional view at the main stage. In the figure, hatching and the like showing the cross section are partially omitted.

First, the buffer layer 36 is formed on the substrate 42 with the etching stopper layer sandwiched between the lower and upper buffer layers 36a and 36b. The lower and upper buffer layers 36a and 36b as a whole form the buffer layer 36. In the fifth embodiment, high-purity undoped GaAs is directly formed as the lower buffer layer 36a on the GaAs substrate 42.
The layer is grown epitaxially by MOCVD to a thickness of a few 100 A °. Next, an AlGaAs layer 50 is formed as an etching stop layer 50 on the lower buffer layer 36a.
Grow to a thickness of A °. Further thereon, a high-purity undoped GaAs layer is formed as an upper buffer layer 36b by MOCV.
It is grown by the D method ((A) of FIG. 8).

Next, the active layer 30 is formed on the upper buffer layer 36b. In the fifth embodiment, the upper buffer layer 3
On 6b, a high-purity n-GaAs layer is crystal-grown to a thickness of 1000 A ° as an active layer 30 which becomes a channel layer of the FET. After that, a separation region 46 for element separation is formed by implanting oxygen ions by a method similar to the conventional method, and then the FET electrode 44 is formed (FIG. 8B).

Next, the buffer layer 36 is exposed by removing at least the portion of the substrate 42 immediately below the active layer 30. In the fifth embodiment, mechanical polishing is performed from the back surface side of the substrate 42 to remove the remaining substrate 42a having a thickness of 100 to 200 μm. Next, the residual substrate 42 obtained by polishing
A mask pattern 52 is formed in a region of the back surface of a at least in a region excluding the region immediately below the active layer by using a normal photolithography technique. Therefore, the opening 54 that exposes the region of the residual substrate 42a corresponding to the portion directly below the active layer is formed.
Are formed ((C) of FIG. 8). In performing this photolithography, a double-sided mask aligner is used and a region immediately below the active layer on the surface side of the polished substrate and the remaining substrate 42 are used.
a It is possible to perform alignment with the region of the opening 54 of the mask pattern 52 on the back surface side.

Next, reactive ion etching (RI) is performed from the rear surface side of the residual substrate 42a through the mask pattern 54.
Perform E). The etching gas is boron trichloride (BC
l ₃ ), chlorine (Cl ₃ ), and sulfur hexafluoride (SF ₆ ).
The mixed gas of is used. This dry etching is stopped at the etching stop layer 50 to remove the substrate portion corresponding to the opening 54 and the lower buffer layer 36a. Then, with respect to the damage layer (not shown) due to the dry etching in the etching stopper layer 50 and the upper buffer layer 36b,
The upper buffer layer 36b is exposed by etching both layers to a depth of several tens to several hundreds of degrees. This 2
By passing through the stepwise etching process, the substrate and other parts are removed so as to make the thickness of the remaining laminated body uniform, so that a structure as shown in FIG. 9A is obtained.

Next, the upper buffer layer 36b is ion-implanted to form the semi-insulating layer 38. In the fifth embodiment, the semi-insulating layer 3 is formed by implanting hydrogen ions or oxygen ions into the exposed upper buffer layer 36b.
8 is formed ((B) of FIG. 9). When the entire back surface is irradiated with ions, the ions are implanted not only in the exposed buffer layer 36b portion but also in the substrate portion 43 not removed. However, since the substrate 43 is much thicker than the semi-insulating layer 38 to be formed, the semi-insulating layer and the ion implantation layer in the substrate portion 43 are electrically continuous. It never happens. Further, there is no adverse effect on the device characteristics of the substrate other than the region immediately below the active layer.

Next, the exposed semi-insulating layer 38 is mainly used.
A backside electrode 40 is formed underneath by using an electron beam method or an electroplating method to fix the backside potential of the element (FIG. 9C).

The compound semiconductor device of this example is manufactured through the above steps.

In each of the above-described embodiments, the present invention has been described by using the specific material and the specific conditions, but the present invention can be modified and modified in many ways. For example, in the above-described embodiment, G is used as the substrate.
Although the aAs substrate is used, it is not necessary to limit the substrate to the compound semiconductor in the present invention. Further, in the above-described Examples 3 and 4, dry etching was performed on the polished substrate, but this etching step uses, for example, wet etching using a mixed solution of ammonia, hydrogen peroxide solution, and water. Is also good. Further, although the buffer layer is formed between the substrate and the etching stopper layer in the fourth and fifth embodiments, the etching stopper layer may be formed directly on the substrate in the present invention. Further, in the case of removing only a partial region of the substrate, for example, when manufacturing a MMIC (monolithic microwave IC), a via hole forming process used when partially forming holes penetrating the substrate is applied. You can also

[0058]

According to the compound semiconductor device of the present invention and the method of manufacturing the same, since the substrate formed by bulk growth is removed in the region immediately below the active layer, the interface state can be eliminated. Furthermore, since the substrate is removed, it is possible to eliminate changes or fluctuations in semiconductor element characteristics due to deep levels in the substrate, regardless of the type of substrate or the like. Since the semi-insulating layer is formed by crystal growth, the influence of deep levels on the semiconductor device characteristics can be empirically predicted by controlling the crystal growth conditions and ion implantation conditions, regardless of the type of substrate. It can be suppressed within the range of obtaining.

Further, for example, when the etching stop film is formed, it is possible to perform etching with a more uniform depth when removing the substrate. Therefore, the loading effect can be suppressed even when the substrate is removed only in a part of the region.

Further, for example, if the substrate other than the region where the substrate is not provided is left, the strength of the entire device is increased as compared with the case where the entire substrate is removed, and the handling at the time of manufacturing the device becomes easy.

[Brief description of drawings]

FIG. 1 is a sectional structural view for explaining a first embodiment of the present invention.

2 (A) and 2 (B) are process diagrams of the first half used to describe a second embodiment of the present invention.

3 (A) to 3 (B) are process diagrams of the latter half of the description for explaining the second embodiment of the present invention.

FIG. 4A to FIG. 4B are process diagrams of the first half provided for explaining the third embodiment of the present invention.

5 (A) to (C) are process diagrams of the latter half for explaining the third embodiment of the present invention.

6 (A) to (C) are process diagrams of the first half provided for explaining the fourth embodiment of the present invention.

7 (A) to 7 (B) are process diagrams of the latter half of the description provided for the fourth embodiment of the present invention.

FIG. 8A to FIG. 8C are process diagrams of the first half provided for explaining the fifth embodiment of the present invention.

9 (A) to 9 (C) are process diagrams of the latter half for explaining the fifth embodiment of the present invention.

10A to 10D are process diagrams provided for explaining a conventional semiconductor element and a method for manufacturing the same.

[Explanation of symbols]

10: GaAs substrate 12: buffer layer 14: active layer 16: element isolation ion implantation part 18: gate electrode 20: drain electrode 22: source electrode 24: back electrode 30: active layer 32: region immediately below active layer 34: substrate Free region 36: Buffer layer 36a: Lower buffer layer 36b: Upper buffer layer 38: Semi-insulating layer 38a: Lower semi-insulating layer 38b: Upper semi-insulating layer 40: Back electrode 42: Substrate 42a: Remaining substrate 43: Substrate part 44: FET electrode 46: Separation region 48: n-GaA
s layer 50: etching stop layer 52: mask pattern 54: opening

Claims (5)

[Claims] 1. A compound semiconductor device comprising a crystal-grown active layer, wherein at least a region immediately below the active layer is a substrate-free region, and the crystal-grown compound semiconductor is used in the substrate-free region. A compound semiconductor device comprising a formed semi-insulating layer, wherein a back electrode is provided under the semi-insulating layer. 2. A step of crystal-growing a semi-insulating layer on a substrate, a step of forming an active layer on the upper side of the semi-insulating layer, and a step of removing a substrate portion at least immediately below the active layer. A method of manufacturing a compound semiconductor device, comprising: exposing the semi-insulating layer; and forming a back electrode under the semi-insulating layer. 3. A step of crystal-growing a non-doped buffer layer on a substrate, a step of forming an active layer on the buffer layer, and a step of removing the substrate portion in a region immediately below the active layer to remove the buffer layer. And a step of forming a semi-insulating layer by implanting ions into the buffer layer, and a step of forming a back electrode under the semi-insulating layer. Manufacturing method of semiconductor device. 4. The method for manufacturing a compound semiconductor device according to claim 2, wherein in the crystal growth step of the semi-insulating layer, a lower semi-insulating layer, an etching stopper layer and an upper semi-insulating layer are sequentially formed. The manufacturing method of the compound semiconductor element characterized by including the process of performing. 5. The method of manufacturing a compound semiconductor device according to claim 3, wherein the crystal growth step of the buffer layer includes a step of sequentially forming a lower buffer layer, an etching stopper layer and an upper buffer layer. A method of manufacturing a compound semiconductor device having the characteristics.