KR100312368B1 - Compound semiconductor integrated circuit and optical regenerator using the same - Google Patents

Abstract

The present invention relates to a compound semiconductor integrated circuit having a field effect transistor having an extremely high speed and a light regenerative repeater using the same. In order to solve the problem of a reduction in side etching and a short circuit between low frequency vibration noise and wiring, Frequency oscillation of the compound semiconductor integrated circuit can be reduced by providing the semiconductor layer or the electrode layer isolated on the surface of the semiconductor between the semiconductor substrate and the element isolation trench having the depth reaching the heterojunction interface on at least the semi-insulating substrate or the buffer layer . Further, by setting the thickness of the buffer layer having the heterojunction to be 150 nm or more, the low frequency vibration can be reduced. An element-to-element isolation of 2 mu m or less in width reaching the buffer layer constituting the heterojunction on the surface of the element region is formed so as to surround the element region and the element peripheral region or the element region in the recess, Is formed at an angle of 10 to 60 degrees with respect to the semiconductor layer surface, it is possible to prevent short-circuiting of the wiring. By combining all of these structures, it is possible to obtain a compound semiconductor integrated circuit having a small side gate effect, a low frequency oscillation, and a short circuit of wiring, and the slab-based integrated circuit using the same can operate normally at a very high speed.

Description

Compound semiconductor integrated circuit and optical reproduction repeater using the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor integrated circuit having a field effect transistor (FET) having a very high speed and a light regenerative repeater using the same, and more particularly to a compound semiconductor junction circuit having a device isolation structure suited for enhancing its high properties.

In recent years, the distance between devices forming integrated circuits has been reduced with respect to high integration of semiconductor integrated circuits. There has been a problem called a side gate effect. The side gate effect is a phenomenon in which a current value flowing through a field effect transistor (FET) is reduced or a threshold voltage is changed by electrical interaction between elements.

In addition, when completing an amplifying circuit having a high gain by an FET using a compound semiconductor, it is important to suppress the side gate effect and suppress the phenomenon called low frequency oscillation. This phenomenon of low frequency oscillation is a phenomenon in which the current flowing to the FET in the integrated circuit normally self-oscillates even when there is no input signal, and the low frequency is called "low frequency oscillation" as very low at room temperature to several Hz.

A conventional compound semiconductor integrated circuit using FFT is described in, for example, Japanese Patent Application Laid-Open No. 2-49465. The compound semiconductor integrated circuit is provided with an element isolation band 39 extending from the recognized FETs T1, T2 and T3 to the semi-insulating GaAs substrate 31 as shown in FIG. 3, The effect was improving. 32, an undoped GaAs buffer layer; 33, an n-type AlGaAs electron supply layer; 34, an n-type GaAs contact layer; 35 is a negative electrode, 37 is a gate electrode, and 38 is an element separator not reaching the substrate 31.

Another conventional example is described in Japanese Patent Application Laid-Open No. 3-87044, for example. As shown in FIG. 4, the compound semiconductor integrated circuit includes a hetero junction buffer layer 42 made of AlGaAs having a thickness of 1000 angstroms at the bottom of the GaAs FET and inter-element isolation trenches 46 extending to the hetero junction interface 44 between adjacent FETs ), Thereby improving the electrical isolation of the FET, particularly the side gate effect. In FIG. 4, reference numeral 41 denotes a semi-insulating GaAs substrate. Reference numeral 43 denotes a GaAs layer. Reference numeral 45 denotes an ohmic electrode. Reference numerals 47 and 48 denote ohmic electrodes. The inter-element separation grooves 46 may be filled with an insulating material to form an inter-element separation body. In this case, the leakage current between the devices needs to pass through the heterojunction interface 44, but is blocked by the energy barrier of the heterojunction interface 44, It does not flow.

However, in the above-mentioned prior art, the suppressing effect on the low-frequency vibration is incomplete, and there is a problem that the integrated circuit according to the prior art operates abnormally. For example, when a limit amplifier with a gain of 50 dB is used, a low-frequency vibration noise having a magnitude that saturates the output amplitude is amplified due to amplification of the low-frequency vibration generated in the integrated circuit.

Further, in the prior art, since the element isolation trenches are formed by the dry etching method, the side walls of the element isolation trenches are formed almost perpendicular to the surface of the semiconductor integrated circuit. Therefore, even if the inter-element isolation trenches are covered with insulating material, the flatness of the surface of the insulating material in the vicinity of the sidewall of the trench becomes insufficient (a step is generated), and the thickness of the wiring metal deposited on the surface of the insulating material is not constant. As a result, in the etching process of the wiring metal for forming the wiring, there is also a problem that an etching residue is generated in the groove and the wiring is connected to each other. As a method for solving this problem, a method of forming inter-element isolation trenches by a wet etching method instead of a dry etching method is conceivable. That is, according to the wet etching method, the sidewall of the portion to be removed by etching of the etched body can be processed as an inclined surface, and the inclined surface can be processed in a tilted state toward the center of the etching- Is known. Therefore, when the inter-element isolation trenches having such a shape are formed by using an insulator, the surface of the insulator near the side wall of the trench becomes flat, and the thickness of the wiring metal deposited on the surface of the insulator becomes constant. As a result, the problem of short-circuiting of the wiring can be solved. However, when the groove is formed by the wet etching method, there arises a new problem that the degree of integration is lowered by an area necessary for the inclined surface of the side wall.

An object of the present invention is to provide a device isolation structure capable of reducing low-frequency vibration, and to provide a compound semiconductor integrated circuit optimal for ultra-high-speed operation and a light regenerative repeater using the integrated circuit.

Another object of the present invention is to solve the problem of short-circuiting of wiring in the element isolation structure of a semiconductor integrated circuit without reducing the degree of integration as much as the case of using the wet etching method.

In order to achieve the above object, first, a semiconductor layer isolated from the surface of a semiconductor between adjacent field effect transistors is formed by selective growth, and at least an element isolation groove having a depth reaching a heterojunction interface on a semi-insulating substrate or a buffer layer is formed.

That is, in a compound semiconductor integrated circuit formed by a plurality of field effect transistors formed on a semi-insulating substrate by epitaxial growth, an isolated semiconductor layer selectively grown on the semiconductor surface between adjacent field effect transistors is provided, Isolation trenches having a depth reaching at least the semi-insulating substrate are provided between the transistors.

In a compound semiconductor integrated circuit comprising a plurality of field effect transistors having a heterojunction buffer layer, an isolated semiconductor layer selectively grown on the semiconductor surface between adjacent field effect transistors is provided, and at least a heterojunction interface between adjacent field effect transistors Is formed in the device isolation trench. In this case, suppression of the side gate effect is further improved.

Insulators such as SiO ₂ may be buried in the element isolation trenches as needed to form inter-element isolation bodies. In this case, wirings can be formed thereon. The position of the element isolation trench is usually within 10 占 퐉 (it may contact the element). If the distance between the element isolation trenches and the element is as large as 10 mu m or more, the distance between elements becomes large, which is not preferable. Further, the width of the device bevel groove is not particularly limited as long as it is possible to manufacture, but it is allowed to enter between the isolated semiconductor layer and the device. It is preferable that the width of the trench is 2 mu m or less in order to facilitate wiring when the element isolation trenches are covered with an insulating material and a wiring layer is present on the surface.

The isolated semiconductor layer may be n-type or p-type if it is electrically conductive, specifically, it may be an impurity concentration of 10 ¹⁷ / cm 3 or more.

The isolated semiconductor layer may be replaced with an isolated ohmic electrode. The thickness of the isolated semiconductor layer becomes thinner as the impurity concentration becomes higher. For example, when the impurity concentration is 10 ¹⁸ / cm 3, the thickness of the isolated semiconductor layer is 100 nm or more. The thickness may be determined by a simple experiment as necessary. The width and the length of the isolated semiconductor layer are not particularly limited, so the manufacturing technology is preferable. The distance between the isolated semiconductor layers is preferably shorter than the width of the isolated semiconductor layer. If the interval is too large, the uniformity of the film thickness of the isolated semiconductor layer lowers. The isolated semiconductor layer may be provided on any layer below the device constituent layer.

We performed an analysis on the mechanism of high frequency oscillation and obtained the following results. First, when a negative (direct current) voltage is applied to the element on the substrate surface with respect to the substrate back electrode, the current flowing between the substrate electrode and the element starts to oscillate at a low frequency of 0.4 Hz to 5 Hz. The magnitude of the current is about several nA when a semi-insulating GaAs substrate having a thickness of 600 mu m is used, and the vibration amplitude is very small, i.e., less than 1 nA. This phenomenon is understood to be due to the fact that the semi-insulating GaAs substrate has a negative resistance due to a deep level, and the high-field domain runs from the device toward the substrate electrode.

However, when there is a FET adjacent to the element, in a conventional element isolation technique, the high-field domain running between the element and the substrate electrode fluctuates the electric potential in the lower portion of the FET to greatly affect the drain current of the FET. For example, the amplitude of the oscillation that appears in the drain current of the FET having a gate width of 50 mu m recognized at a distance of 40 mu m reaches 100 mu m or more, and this large current oscillation seriously impedes circuit operation.

In other words, by suppressing the phenomenon that the minute current between the device and the substrate is vibrated, the oscillation of the drain current of the FET can be avoided and the low frequency vibration when the integrated circuit is used can be suppressed.

FIG. 5 is a graph showing the effect of the present invention. The vertical axis shows the amplitude of the current when the -10 V voltage was applied between the substrate back electrode and the substrate surface element, and the horizontal axis shows the depth of the element isolation trench. In the horizontal axis, the device isolation trench reaches the semi-insulating substrate with a depth of 0.4 mu m. In the conventional structure in which the isolated semiconductor layer is not formed, element isolation grooves are provided between the FETs, and even if the depths of the isolation grooves are made deep, the effect of improving the low frequency oscillation is not exhibited. However, in the structure in which the semiconductor layer isolated from the periphery of the device is disposed, the vibration amplitude is reduced to 0.2 nA or less and the low frequency vibration can be remarkably improved when the depth is more than 0.4 탆 or more than the depth reaching the semi-insulating substrate. . In the present invention, since the oscillation of the minute current between the element and the substrate is suppressed in this way, the drain current of the adjacent FET does not vibrate, and no vibration noise appears in the circuit operation.

However, even when the thickness of the buffer layer is more than 100 nm, preferably not less than 130 nm, and more preferably not less than 150 nm, the compound semiconductor integrated circuit comprising several field effect transistors having a heterojunction buffer layer can improve the side gate internal pressure, Vibration can be reduced. The side gate internal pressure is further improved by providing at least the element isolation trench having the length reaching the buffer layer or the heterojunction interface. Further, by providing the above-mentioned isolated semiconductor layer, the device isolation effect is further improved and the reduction of low frequency vibration becomes remarkable.

Recently, we have fabricated GaAsFETs using a 100 nm Al _x Ga _{1 -x} As layer (buffer layer), which is a conventional structure, and examined the low-frequency vibrations. As a result, it is clear that there is a region where conventional low- . The oscillation withstand pressure of the low-frequency vibration will be described with reference to FIG. The characteristic line 151 is a case where the thickness of the undoped Al _x Ga _{1 -x} As layer 103 (FIG. 14) is 100 nm. In this case, the oscillation withstand voltage was -5 V to -9 V at the depth d (14 degrees) from the surface of the semiconductor device to the undoped Al _x Ga _{1 -x} As layer 103, but when the depth d was 300 nm, Exceeded -2 OV. That is, when the thickness of the undoped Al _x Ga _{1 -x} As layer 103 is 100 nm, it is necessary to set the depth d to 300 nm or more in order to improve the oscillation withstand pressure of the low frequency vibration.

However, when the depth d is set to 300 nm or more, a problem arises when forming the element isolation trench reaching the undoped Al _x Ga _{1 -x} As layer 103 (FIG. 14). That's two things: (1) When a groove is formed by wet etching, the active layer is etched by etching in the transverse direction, resulting in defects. (2) When grooves are formed by dry etching, the grooves are deep and vertical, making it difficult to planarize. To solve these two problems, a groove having a depth d of less than 300 nm is required. The buffer layer may be a single layer or multiple layers, and in the case of multiple layers, the total thickness of the buffer layer may be the above value.

An undoped GaAs layer 102, an undoped Al _x Ga _{1 -x} As layer 103 having a total thickness of 150 nm or more, a p-type GaAs layer 103 having a total thickness of 150 nm or more, A plurality of field effect transistors are formed on the surface of the crystal having a structure in which the n-type GaAs active layer 105 and the n-type GaAs active layer 105 are sequentially stacked, and grooves 131 having a depth of less than 300 nm are provided between the field effect transistors Respectively.

The range of x was 0.1? x? 0.45.

In FIG. 14, reference numeral 111 denotes a gate electrode, reference numeral 112 denotes a source electrode, and reference numeral 113 denotes a drain electrode.

The oscillation withstand voltage of the low frequency wave vibration is improved by forming the Al _x Ga _{1 -x} As layer 103 (FIG. 14) over 100 nm in total, preferably 130 nm or more, and more preferably 150 nm.

In addition, by forming a trench reaching the buffer layer AlGa _1-x As layer 103 (FIG. 19) between the field effect transistors, the side gate internal pressure is improved. The Al _x Ga _{1 -x} As layer 103 is formed on the surface of the semiconductor device by forming an Al _x Ga _{1 -x} As layer having a thickness of more than 100 nm, preferably not less than 130 nm, more preferably not less than 150 nm, The depth of the inter-element isolation trenches 134 reaching the Al _x Ga _{1 -x} As layer 103 can be made shallow.

Next, the purpose of obtaining a device isolation structure of a semiconductor integrated circuit having good integration and no short-circuiting of the wiring is to form a groove (not shown) on the side of at least the gate pad (indicated by reference numerals 27 and 29 in FIG. and a device isolation region having a width of 2 탆 or less reaching a semi-insulating semiconductor constituting a heterojunction on the surface of the device region is formed so as to surround the device region and the periphery of the groove, And a side wall of the groove through which the wiring formed on the insulating material is passed is formed so that the surface of the element region is directed in the depth direction toward the center of the groove So as to form an inclined sloped surface.

Therefore, (1) the element isolation region is formed so as to surround the element region and the groove, and the sidewall of the groove in the gate width direction is inclined from the surface of the element region toward the center of the groove in the depth direction (2) a groove is formed so as to surround the periphery of the device region, and an inter-device isolator is formed in the groove so as to surround the periphery of the device region, the groove is covered with an insulating material, The sidewall of the groove to be passed may be inclined from the surface of the element region toward the center of the groove in the depth direction. Incidentally, the angle (e.g., ? In FIG. 28 and 30) between the inclined surface and the semiconductor layer surface of the element region is 10 to 60 degrees. If the angle is more than 60 degrees, the inclined surface becomes close to perpendicular to the semiconductor layer, and the effect of the present invention becomes insufficient. In addition, by combining the above structure in which the groove and the element separator are combined with the structure in which the isolated semiconductor layer is provided and the structure in which the buffer layer has a thickness of more than 100 nm, excellent results can be obtained with both advantages of each structure .

First, the operation of the case (1) will be described. The groove in the case (1) serves to define the element region. Further, the sidewall formed of the inclined surface serves to prevent breakage of the gate pad.

The inter-element isolation body having a width of 2 mu m or less is for preventing short-circuit of the wiring. This is evident from the fact that the step Z is sufficiently small at a width of 2 mu m as the relationship between the step Z and the element isolation width X as shown in Fig. Further, since the element region is surrounded by the element-to-element separator, the leakage current can be more completely prevented. Also, because of this, the distance between adjacent elements can be shortened, and therefore the degree of integration can be maintained.

Next, the operation of the case (2) will be described. Since the groove is formed on the upper part of the element-to-element separator, the element separates between the grooves and the element. Therefore, it is clear that the prevention of the short circuit of the wiring is improved in the portion of the groove which is effective for short-circuit prevention. Further, since the depth of the element-to-element separator can be shortened by the groove, the effect of short-circuit prevention is also improved in this portion. This is clear in FIG. That is, in FIG. 31, it is clear that when the depth Y of the inter-element separator is short, the step Z is small. Further, since the element region is surrounded by the element-to-element isolation body, the leakage current can be more completely prevented. Further, because of this, the distance between the adjacent elements can be shortened, so that it is possible to compensate for the decrease in the degree of integration due to provision of the grooves, and the degree of integration can be maintained.

In the semiconductor integrated circuit of the present invention, the wiring layer and the surface protection layer may be conventionally used.

In the compound semiconductor integrated circuit having the heterojunction buffer layer and the device isolation trench reaching the heterojunction interface, the energy difference between the Fermi level and the conduction band, and the energy difference between the Fermi level and the valence band, Is larger than the heterojunction semiconductor layer (the side opposite to the substrate).

By using the compound semiconductor integrated circuit of the present invention described above, it is possible to obtain a high performance optical regenerator that operates normally at, for example, 10 gigabits per second.

Next, Embodiment 1 of the present invention will be described with reference to Figs. 1, 2, and 6. FIG. 1 is a plan view of a device isolation structure, FIG. 2 is a cross-sectional structure diagram of a FET and a device isolation structure called a HIGFET (Heterostructure Insulated-Gate FET), and FIG.

First, the manufacturing process thereof will be described. 6 shows a state in which the undoped GaAs buffer layer 2, the p-type GaAs layer 3 and the n-type GaAs active layer 4 are formed on the semi-insulating GaAs substrate 1 by MBE (molecular beam epitaxy) , And the undoped AlGaAs layer 5 are successively grown successively. The substrate temperature during growth was preferably about 510 ° C. As shown in Table 1, the thickness and the impurity concentration of each layer were measured by using an undoped LEC substrate (substrate grown by Liquid Encapsulated Czochralski method) or a Cr-doped LEC substrate for the semi-insulating GaAs substrate 1 do. The composition ratio of the undoped AlGaAs layer 5 is usually Al _0.3 Ga _0.7 .

Table 1

Next, in Fig. 6 (b), the region of the FET is covered with the SiO ₂ film, and the semiconductor surface in the other region is etched by using the wet etching liquid. The etching depth is 200 nm. Next, after the SiO ₂ film is removed, a WSi _x (tungsten silicide) film having a thickness of 600 nm is deposited by a sputtering method, and photolithography and dry etching are performed to form the heat resistant gate electrode 7. Here, it was appropriate that the composition ratio _x of Si was 0.45. In order to reduce the resistance between the source gates, Si may be implanted after the heat resistant gate electrode 7 is formed. In this case, the ion implantation conditions are an acceleration energy of 40 keV and a dose of 1 × 10 ¹⁴ / cm ² .

Next, in FIG. 6 (c), a silicon oxide film 62 having a thickness of 100 nm is deposited on the entire surface by plasma CVD, and the source and drain electrode portions of the FET are formed by photolithography and reactive ion etching And the SiON film of the portion forming the isolated semiconductor layer are etched to pierce the window. As the etching gas, CF ₄ and O ₂ gas are generally used. Thereafter, the semiconductor surface is etched to a depth of 70 nm by a reactive ion etching method, and the portion of the undoped AlGaAs layer 5 in contact with the source and drain electrodes of the FET is removed. At this time, SiCl ₄ is used as the etching gas.

Next, in FIG. 6 (d), by using MOCVD (Organic Metal Pyrolysis) method using the SiON film 62 with the window as a mask, a high concentration n-type selective growth layer 60 and a high concentration n- (61) are simultaneously grown. The growth temperature is usually 700 ° C, and trimethylgallium and arsine are used as the source gas. The layers 60 and 61 are made of GaAs having a thickness of 320 nm doped with Si or Se at a concentration of 4 x 10 ¹⁸ / cm ³ . As shown in FIG. 1, the high-concentration n-type isolated semiconductor layer 61 has a square shape with a side of 7 占 퐉 and is arranged at the same interval with an interval of 3 占 퐉.

6 (e), the SiON film 62, the p-type GaAs layer 3 and the undoped GaAs buffer layer 2 are etched by photolithography and reactive ion etching to form the semi-insulating substrate 1, The element isolation trench 9 is formed to have a depth reaching the depth of the element isolation trench 9. The groove 9 has a width of 1 탆 and a depth of 0.5 탆 and reaches the semi-insulating GaAs substrate 1. The shape of the groove 9 is such that it surrounds the periphery of each FET as shown in FIG. The high concentration n-type isolated semiconductor layer 61 is arranged to surround the groove 9.

Particularly, in the processing of the groove 9, a reactive ion etching method called ECR (Electron Cyclotron Resonance) is used to perform processing under the conditions of SiCl ₄ , microwave discharge power density 1.54 kW / m ² , and pressure 44 mPa as an etching gas Even if grooves having a depth of 0.5 탆 are formed, the weighting on the side can be suppressed to 0.2 탆 or less, and the shape of the grooves 9 can be improved.

Thereafter, the ohmic electrode 8 is formed on the n-type selective growth layer 60 of high concentration by the lift-off method, and element isolation structures such as the first and second diagrams and the field effect transistor are completed. Thereafter, wiring is performed on the ohmic electrode 8 and the heat resistant gate electrode 7 to complete an integrated circuit. Further, all the potential of the layer 61 was floated without conducting wiring in the heavily doped n-type isolated semiconductor layer 61.

The effect of this embodiment will be described with reference to FIG. FIG. 7 is a graph showing drain currents of adjacent FETs. The substrate back electrode is 0 V, the source potential of one FET is -8 V, the source potential of the noticed FET is -1 V, and the interval between the FETs is 40 μm. The conventional device isolation structure oscillates at an amplitude of 100 mu A or more, whereas the drain current of the device isolation structure of the first embodiment has a constant value, thereby completely preventing the low frequency oscillation phenomenon.

As described above, according to the first embodiment, it is possible to suppress the micro-current oscillation between the FET and the substrate and to prevent the low-frequency oscillation of the drain current of the adjacent FET.

According to the first embodiment, since the pattern density of the high concentration n-type selective growth layer 60 and the high concentration n-type isolated semiconductor layer 61 is high and almost uniform in the chip, the selective saturation There is an effect that the in-plane distribution of the thickness is made uniform.

In the first embodiment, the FETs are HIGFETs, but MESFETs (Metal-Semiconductor Field Effect Transistors) or HEMTs (High-Electron Mobility Transistors) may also be used.

Example 2

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 8 is a cross-sectional view of the HIGFET and device isolation structure. The difference from Embodiment 1 is that an undoped GaAs buffer layer 82, an undoped AlGaAs buffer layer 83 and an undoped GaAs buffer layer 84 are provided in place of the undoped GaAs buffer layer 2, To the depth reaching the undoped AlGaAs buffer layer (83). The film thickness of the undoped GaAs buffer layer 82 was 100 nm, the thickness of the undoped AlGaAs buffer layer 83 was 300 nm, the composition ratio was Al _0.3 Ga _0.7 As, and the film thickness of the undoped GaAs buffer layer 84 was 300 nm.

(20) represents a heterojunction interface.

According to the present embodiment, the low frequency oscillation phenomenon of the HIGFET can be suppressed, and the interval between the FETs can be reduced to about 1.5 mu m to improve the side gate internal pressure. As a result, the band gap due to the wiring capacitance and the wiring inductance between the FETs is improved, and the high-temperature characteristics of the integrated circuit can be improved. In addition, there is also an effect of reducing the chip area and reducing the production cost.

Example 3

Next, a third embodiment of the present invention will be described with reference to FIG. 9, FIG. 10, and FIG. FIG. 9 is a circuit diagram of the basic amplifier 70, FIG. 10 is a block diagram of the limit amplifier, and FIG. 11 is a configuration diagram of the optical regenerator.

The third embodiment is an example in which the element isolation structure described in the first or second embodiment is specifically applied to an integrated circuit and a light regenerative repeater. First, the FET of the circuit diagram shown in FIG. 9 is formed by using the element isolation structure shown in FIGS. 1 and 2 or the element isolation structure shown in FIG. 8, and a basic amplifier 70 of one stage is formed. FETs that are short-circuited with a source and a drain are usually used for the diode, and the device isolation structure of the present invention is also used for the isolation structure. A HIGFET with a gate length of 0.3 μm was used for the FET. Next, as shown in FIG. 10, four basic amplifiers 70 are combined to form a limit amplifier integrated circuit. The light amplifier is used as the timing extracting circuit of FIG. 11 to constitute a light regenerator for optical communication.

According to the third embodiment, it is possible to realize a high-gain, ultra-high-speed limit amplifier that does not cause noise due to low-frequency vibration and realize a light regenerating repeater that operates normally at an ultra-high speed, for example, 10 gigabits per second.

In the third embodiment, the basic amplifier circuit of FIG. 9 may be applied to the preamplifier, the gain variable amplifier, the main amplifier, and the discriminator in the eleventh aspect. In this case, the noise due to the low-frequency vibration in each integrated circuit can be suppressed, and the reception sensitivity of the optical regenerative repeater can be further improved.

Example 4

Next, a fourth embodiment of the present invention will be described with reference to FIG. The difference from Embodiment 1 is that only one row of highly isolated n-type isolated semiconductor layers 61 is arranged around the element isolation trenches 9.

According to the fourth embodiment, it is possible to register and operate the layer 61, the groove 9 and the FET as one set of data in the mask drawing of the integrated circuit, thereby improving the efficiency of the mask arrangement work . In addition, since the amount of numerical data transferred at the time of manufacturing the mask is greatly reduced, the cost required for the computer processing at the time of mask production can be reduced.

Example 5

Next, a fifth embodiment of the present invention will be described with reference to FIG. The difference from the first embodiment is that an ohmic electrode 98 isolated in place of the high concentration n-type isolated semiconductor layer 61 is used. The electrodes 98 do not provide wiring, and their potentials are all float.

According to the fifth embodiment, the electrode 99, which is an isolated pattern, can be formed by a process independent of the high concentration n-type selective growth layer 60. For example, the process of forming the layer 60 can be performed by ion implantation It is possible to make changes such as changing the number of processes, and the degree of freedom of the process can be improved.

As is clear from Examples 1 to 5, the present invention can suppress the low-frequency oscillation phenomenon in the field effect transistor and its integrated circuit, and in the case where the element isolation trench reaching the heterojunction interface is provided, The suppression of the gate effect is further improved, and an integrated circuit and a photo-regenerative repeater using the compound semiconductor field-effect transistor optimized for ultra-high-speed operation can be provided.

Example 6

The procedure of the sixth embodiment of the semiconductor device of the present invention will be described with reference to FIGS. 15 to 18. FIG.

FIG. 15 is a process chart (1) for manufacturing a semiconductor device according to Embodiment 6 of the present invention. FIG. An undoped GaAs layer 102 (300 nm), an undoped Al _x Ca _1-x As layer (50 nm), and an undoped GaAs layer 102 are formed on a semi-insulating GaAs substrate 101 grown by the LEC method by the MBE method (Molecular Beam Epitaxy method) A layer obtained by laminating an undoped GaAs layer (50 nm), an undoped Al _x Ga _{1 -x} As layer (50 nm), an undoped GaAs layer (50 nm) and an undoped Al _x Ga _{1 -x} As layer 103, undoped Al _x Ga _1-x as of the total layer thickness of 150nm), p-type GaAs layer (104) (150nm: be as an impurity and a ^{6.0 × 10 16 cm -3),} n -type GaAs active An undoped AlGaAs layer 106 (10 nm) and an undoped GaAs layer 107 (5 nm) were grown on the GaN layer 105 (15 nm: containing Si as impurity at 5.3 × 10 ¹⁸ cm ^-3 ). Here, the undoped Al _x Ga _{1 -x} As layers 103 and 106 had an Al composition ratio x of 0.3.

FIG. 16 is a process drawing (2) for manufacturing a semiconductor device according to the sixth embodiment of the present invention. A groove 131 having a depth of 100 nm was formed by a wet etching method, and a gate electrode 111 was formed by photolithography. WSix (tungsten suicide) was used as the gate electrode metal, and the thickness thereof was set to 600 nm.

FIG. 17 is a process chart (3) for manufacturing a semiconductor device according to the sixth embodiment of the present invention. FIG. After the ion implantation (ion type: Si, dose: 5 × 10 ¹³ cm ^-2 ) of the source and drain regions was performed, the ohmic electrode layer forming grooves 132 and 133 having a depth of 50 nm were successively subjected to dry etching . Here, SiCl ₄ was used as the etching gas.

FIG. 18 is a process diagram (4) for manufacturing a semiconductor difference in Example 6 of the present invention. FIG. Subsequently, the n-type GaAs layers 141 and 142 (320 nn: including Si of 4.0 x 10 ¹⁸ cm ^-3 as an impurity) were selectively grown by the MOCVD method. Subsequently, a source electrode 112 and a drain electrode 113 were formed by a lift-off method, and alloyed at 400 ° C to form an FET using an ohmic electrode. The metal used as the source electrode 112 and the drain electrode 113 and their thicknesses are AuGe: 60 nm, W: 10 nm, Ni: 10 nm, Au: 120 nm. Finally, an ohmic electrode 114 was formed on the back surface of the substrate to fix the potential of the electrode 114. [

By using the semiconductor device of the sixth embodiment, the oscillation withstand voltage of the low frequency oscillation can be made to be at least -20 V or less irrespective of the thickness d in FIG. 14 as indicated by the characteristic line 152 in FIG.

Example 7

19 is a cross-sectional view of the semiconductor device according to the seventh embodiment. The seventh embodiment can be formed in the same manner as the sixth embodiment. The difference from the embodiment 6 of the embodiment 7 is that (1) the layer 103 is an undoped Al _x Ga _{1 -x} As single layer with a thickness of 300 nm and (2) the ion implantation (ion type: Si , Dose amount: 5 × 10 ¹³ cm ^-2 ), and a groove 134 having a depth of 100 nm is formed between the field effect transistors by a dry etching method. SiCl ₄ was used as the etching gas in forming the groove 134. The width of the groove 134 is 1 占 퐉.

It is sufficient if the groove 134 reaches at least the AlO _x Ga _{1 -x} As layer 103. The groove 134 may be formed after the source electrode 112 and the drain electrode 113 are formed.

Since the groove 134 reaches the undoped Al _x Ga _{1 -x} As layer 103 in the seventh embodiment as compared with the sixth embodiment, the side gate internal pressure can be improved.

Example 8

20 is a plan view of the semiconductor device according to the eighth embodiment. The eighth embodiment can be formed in the same manner as the seventh embodiment. The eighth embodiment differs from the seventh embodiment in that grooves 134 having a depth of 100 nm are formed by a dry etching method so as to surround the field effect transistors.

Since the groove 134 is formed so as to surround the field effect transistor in the eighth embodiment as compared with the seventh embodiment, there is an effect that the side gate internal pressure can be improved.

Example 9

21 is a cross-sectional view of the semiconductor device according to the ninth embodiment; The ninth embodiment can be formed in the same manner as that of the eighth embodiment. The ninth embodiment differs from the ninth embodiment in that (1) the thickness of the p-type GaAs layer 104 is 50 nm, the Be concentration as an impurity is 1.8 × 10 ¹⁷ cm ^-3 , and (2) And the step of forming the groove 134 by the method is omitted. In Example 9, the thickness of the p-type GaAs layer 104 is 1/3 of that in Example 6, and the Be concentration as an impurity is 3 times as high as in Example 6. [ Therefore, the threshold voltage of the FET in the ninth embodiment coincides with the threshold voltage of the FET in the sixth embodiment.

The thickness of the p-type GaAs layer 104 is reduced by 50 nm in the ninth embodiment as compared with the eighth embodiment. Thereby, the time for crystal growth and the raw material of GaAs can be saved, which is effective in reducing the cost.

The depth of the groove 131 by the wet etching method was set to 100 nm in the same manner as in the sixth embodiment. Since the groove 131 reaches the undoped Al _x Ga _{1 -x} As layer 103, the step of forming the groove 134 by the dry etching method can be omitted. By omitting the step of forming the grooves 134, the process sequence can be simplified and the production cost can be reduced.

In the sixth to ninth embodiments, the layer 103 is made of undoped Al _x Ga _1-x As, but it is also possible to use an Al _x Ga _{1 -x} As layer in which oxygen is doped at 1 to 3 × 10 ¹⁸ cm ^-3 Maybe. In this case, the side gate internal pressure can be improved.

In Examples 6 to 9, semiconductor crystals having the above structures were used. When the total thickness of the undoped Al _x Ga _{1 -x} As layer 103 is 150 nm or more, the thickness of the other semiconductor layers, the presence or absence of impurities, And the concentration may be changed. For example, even if the p-type GaAs layer 104 is an undoped GaAs layer, the effect of the present invention does not change.

Compound semiconductors in which the thickness of the buffer layer described in Examples 6 to 9 is set to 100 nm can improve the oscillation withstand voltage of the low-frequency oscillation of the current flowing through the drain current of the FET, thereby making it possible to produce an integrated circuit with high reliability. In addition, since the element isolation trench can be made shallow, the groove formation time can be shortened and the production cost can be reduced.

Example 10

A semiconductor integrated circuit using the FET of the tenth embodiment of the present invention will be described with reference to FIGS. 23 to 28. FIG.

An undoped GaAs layer 202 (1500 Å in thickness), an undoped AlGaAs layer 203 (1000 Å in thickness), an undoped GaAs layer 204 (thickness (thickness)) are formed on the semi-insulating GaAs substrate 201 manufactured by the LEC method by MBE And an n-type GaAs layer 205 (having a thickness of 1000 ANGSTROM and containing Si of 2.5 x 10 < ¹⁷ > cm < ³ > as an impurity) were successively grown at a substrate temperature of 580 DEG C. [ Here, the Al composition ratio of the undoped AlGaAs layer 204 was set to 0.3 (FIG. 23). Further, the GaAs layers 202 and 204 may be replaced with a p-type GaAs layer in any one or both of the undoped layers.

Subsequently, a silicon dioxide film 206 having a thickness of 300 ANGSTROM and a silicon film 207 having a thickness of 1000 ANGSTROM are deposited to form a resist 208 by a photolithography technique. Using the resist 208 as a mask, 206 and the silicon film 207 were removed. Thereafter, a groove 231 having a depth of 1500 ANGSTROM was formed by surrounding the region to be a device region of the field effect transistor by a wet etching method. The groove 231 penetrates the n-type GaAs layer 205 and reaches the undoped GaAs layer 204. The etching solution used for wet etching was a mixed solution of fluorohydrogen: hydrogen peroxide: water = 4: 1: 20. The inclination of the sidewall of the groove was about 40 degrees (angle ? Of the groove side of the n-type GaAs layer 205) (Fig. 24).

Next, the resist 208 was removed and the silicon film 207 was removed using CF ₄ . Next, a resist (not shown) is applied to form an open hole pattern having a width of 1 mu m surrounding the element region in the groove 231, and the undoped GaAs layer 204 is formed by RIE (Reactive Ion Etching) And a groove 232 having a width of 1 mu m reaching the undoped GaAs layer 202 through the undoped AlGaAs layer 203 were formed. Here, SiCl ₄ was used as the etching gas. Since the groove 232 reaches the undoped AlGaAs layer 203, isolation between elements can be ensured. The side walls of this groove 232 are formed substantially perpendicular to the surface of the semiconductor device.

Then, the source electrode 221 and the drain electrode 222 were formed by a lift-off method, and alloyed at 400 캜 to form an ohmic electrode. The electrodes used as the electrodes 221 and 222 and the thickness thereof were AuGe: 600 Å, W: 100 Å, Ni: 100 Å, Au: 1200 Å. Further, the Schottky barrier gate electrode 223 was formed to form the FET. The metal used as the gate electrode and the thickness thereof were set to Ti: 500 Å, Pt: 500 Å, and Au: 2000 Å (FIG. 25)

Subsequently, an insulator 241 was formed and the surface of the semiconductor device was made flat. The insulator 241 was formed by plasma deposition of a silicon dioxide film having a thickness of 2000 ANGSTROM, application of an organic insulating film having a thickness of about 2000 ANGSTROM, and plasma deposition of a silicon dioxide film having a thickness of 3000 ANGSTROM. Thereafter, inter-element wiring 242 was executed (FIG. 26).

There was no etching residue of the wiring material in this wiring formation step, and a semiconductor integrated circuit free from wiring shortage could be manufactured.

26 shows a plan view of FIG. 26, FIG. 28 shows a sectional view taken along line A-A of FIG.

In FIG. 28, (251) and (252) represent hetero interfaces.

Example 11

A semiconductor integrated circuit using the FET of the eleventh embodiment of the present invention will be described with reference to FIG. 29 and FIG. 30. FIG. FIG. 29 is a plan view, and FIG. 30 is a sectional view taken along line B-B of FIG. 29. The semiconductor integrated circuit of the tenth embodiment is different from the semiconductor integrated circuit of the tenth embodiment in that the side surfaces 226 and 227 of the element region are in contact with the side walls of the groove 232 having a width of 1 mu m. That is, the grooves corresponding to the grooves 231 in Embodiment 10 are formed only at two places of the grooves 231 'and 231' '. Since the grooves 232 are manufactured by dry etching, It is possible to fabricate a semiconductor integrated circuit that is perpendicular to the surface of the region but has a narrow width of the groove 232 of 1 mu m so that no wiring short circuit occurs.

It is not necessary to provide the groove 231 " as long as the mask misalignment is permissible. The groove 231 " may be a groove 232 film like the side faces 226 and 227. That is, It is not necessary to arrange the mask in the gate width direction twice as long as the mask 231 'and the groove 232 are manufactured.

As is clear from Examples 10 and 11, grooves are provided at least on the side of the gate pad, and an inter-element separator having a width of 2 m or less is formed so as to include an element region at a predetermined position, It is possible to provide a semiconductor integrated circuit free from the short-circuiting of the wiring without lowering the wiring density.

FIG. 1 is a plan view of an element isolation structure according to Embodiment 1 of the present invention. FIG.

FIG. 2 is a cross-sectional view of a field effect transistor and device isolation structure of Example 1 of the present invention. FIG.

FIG. 3 is a cross-sectional view showing an example of a conventional element isolation structure. FIG.

FIG. 4 is a cross-sectional view showing another example of a conventional element isolation structure. FIG.

FIG. 5 is a graph showing the effect of the present invention. FIG.

6 is a cross-sectional structural view illustrating a manufacturing process of a field-effect transistor and a device isolation structure according to Embodiment 1 of the present invention.

FIG. 7 is a graph showing the effect of the embodiment 1 of the present invention. FIG.

FIG. 8 is a sectional view of a field effect transistor and a device isolation structure according to Example 2 of the present invention; FIG.

FIG. 9 is a circuit diagram of a basic amplifier according to Embodiment 3 of the present invention; FIG.

10 is a block diagram of a limit amplifier according to Embodiment 3 of the present invention.

FIG. 11 is a structural view of a light regenerative repeater according to Embodiment 3 of the present invention. FIG.

12 is a plan view of a device isolation structure according to a fourth embodiment of the present invention;

FIG. 13 is a plan view of a device isolation structure according to a fifth embodiment of the present invention; FIG.

FIG. 14 is a cross-sectional structural view illustrating the principle of another element isolation structure of the present invention; FIG.

FIGS. 15 to 18 are cross-sectional views showing a process for manufacturing a semiconductor device according to the sixth embodiment of the present invention. FIG.

FIG. 19 is a cross-sectional view of a semiconductor device according to Embodiment 7 of the present invention. FIG.

FIG. 20 is a plan view of the semiconductor device according to the eighth embodiment of the present invention; FIG.

21 is a cross-sectional view of a semiconductor device according to Embodiment 9 of the present invention.

FIG. 22 is a graph for explaining the low frequency vibration preventing effect of the present invention. FIG.

23 to 26 are cross-sectional views showing a manufacturing process of a semiconductor integrated circuit using the FET according to the tenth embodiment of the present invention.

FIG. 27 is a plan view of the semiconductor integrated circuit shown in FIG. 26; FIG.

28 is a cross-sectional view of the drawing of FIG. 27 and the vertical direction (line A-A);

FIG. 29 is a plan view of a semiconductor integrated circuit using the FET of Embodiment 11 of the present invention. FIG.

30 is a cross-sectional view of a semiconductor integrated circuit using the FET of Embodiment 11 of the present invention.

FIG. 31 is a graph showing the relationship between the step and the width of the element-to-element separator.

Claims (23)

A semi-insulating substrate; A plurality of field effect transistors formed on the substrate; And an element isolation trench formed between adjacent ones of the field effect transistors, Wherein a plurality of isolated conductive layers are formed in contact with the semiconductor surface between adjacent ones of the field effect transistors. The method according to claim 1, Wherein the plurality of isolated conductive layers are a plurality of isolated semiconductor layers. 3. The method of claim 2, Wherein the element isolation groove has a depth reaching the semi-insulating substrate. The method of claim 3, Wherein the device isolation grooves surround each of the field effect transistors, and the plurality of isolated semiconductor layers are disposed outside the device isolation trenches. 5. The method of claim 4, The isolated semiconductor layers are arranged at regular intervals, The spacing being less than the width of the isolated semiconductor layer, Wherein the width is a size measured along a direction perpendicular to the direction in which the isolated semiconductor layer is arranged at an interval therebetween. 3. The method of claim 2, Wherein the compound semiconductor integrated circuit has a buffer layer, a semiconductor layer is disposed on a buffer layer side opposite to the substrate to form a heterojunction at an interface between the buffer layer and the semiconductor layer, The energy difference between the Fermi level and the lowest level of the conduction band and the energy difference between the Fermi level and the highest level of the valence band are larger in the buffer layer than in the semiconductor layer which is heterojunction with the buffer layer, Wherein the element isolation trench has a depth reaching at least the interface of the heterojunction. The method according to claim 6, Wherein the device isolation grooves surround each of the field effect transistors, and the plurality of isolated semiconductor layers are disposed outside the device isolation trenches. 8. The method of claim 7, The isolated semiconductor layers are arranged at regular intervals, The spacing being less than the width of the isolated semiconductor layer, Wherein the width is a size measured along a direction perpendicular to the direction in which the isolated semiconductor layer is arranged at an interval therebetween. The method according to claim 1, Wherein the isolated conductive layer is an ohmic electrode floating electrically and not electrically connected to the field effect transistor. The method according to claim 1, Wherein the element isolation trench is filled with an insulating material. The method according to claim 6, Wherein the thickness of the buffer layer is 100 nm or more. The method according to claim 6, Wherein the buffer layer has a thickness of at least 130 nm. The method according to claim 6, Wherein the thickness of the buffer layer is at least 150 nm. 14. The method of claim 13, And the distance from the top surface of the semiconductor layer to the buffer layer is less than 300 nm. The method according to claim 6, Wherein the element isolation trench has a width of at least 2 占 퐉 and is filled with an insulating material and a side surface thereof is perpendicular to a surface of the element region of the field effect transistor and forms a groove on at least the gate pad side of the element region, Each of the device isolation trenches has a structure selected from the group consisting of a structure surrounding the device region and the trench and a structure surrounding the device region in the trench, Wherein the angle formed between the first electrode and the second electrode is in a range of 10 DEG to 60 DEG with respect to the second electrode. Board; A first semi-insulating semiconductor layer formed on the substrate; A sphere region of the field effect transistor formed on the first semiconductor layer; And an inter-element isolator formed between the element regions and reaching the first semiconductor layer at the surface of the element region, The semiconductor layer being disposed on the first semiconductor layer on the side opposite to the substrate to form a heterojunction at an interface that the semiconductor layer shares with the first semiconductor layer, The energy difference between the Fermi level of the heterojunction and the lowermost level of the conduction band and the energy difference between the Fermi level of the heterojunction and the highest level of the valence band is higher than the semiconductor layer which is heterojunction with the first semiconductor layer, Larger from the floor, Wherein the inter-element separator is made of an insulating material, and a side wall thereof is perpendicular to the element region surface, The side walls of the grooves in the gate width direction are inclined surfaces inclined toward the center of the grooves in the depth direction on the surface of the device region, Wherein the inter-element separator is formed so as to surround the periphery of the sofa region and the groove, and the width thereof is 2 占 퐉 or less. 17. The method of claim 16, A second semiconductor layer formed between the substrate and the first semiconductor layer, and a third semiconductor layer formed between the first semiconductor layer and the element region, And the third semiconductor layer is the semiconductor layer disposed on the first semiconductor layer. 18. The method of claim 17, Wherein the substrate is a semi-insulating GaAs substrate, the first semiconductor layer is an AlGaAs layer, the second semiconductor layer is a GaAs layer, the third semiconductor layer is a semi-insulating GaAs layer, Lt; RTI ID = 0.0 > IC < / RTI > 17. The method of claim 16, And the two sidewalls in the gate length direction of the element region are in contact with the element-to-element separator. Board; A first semi-insulating semiconductor layer formed on the substrate; An element region of the field effect transistor formed on the first semiconductor layer; And an inter-element isolator formed between the element regions and reaching the first semiconductor layer at the surface of the element region, The semiconductor layer being disposed on the first semiconductor layer on the side opposite to the substrate to form a heterojunction at an interface that the semiconductor layer shares with the first semiconductor layer, The energy difference between the Fermi level of the heterojunction and the lowest level of the conduction band and the energy difference between the Fermi level of the heterojunction and the highest level of the valence band is higher than that of the semiconductor layer which is heterojunction with the first semiconductor layer Larger in the semiconductor layer, Wherein the inter-element isolator is made of an insulating material and its side wall is perpendicular to the surface of the element region, the groove is formed so as to surround the periphery of the element region, The inter-element isolator is formed so as to surround the element region in the groove, The groove is filled with an insulating material, a wiring is formed in the insulating material, Wherein a sidewall of the groove through which the wiring passes is an inclined surface inclined from the surface of the element region toward a center portion of the groove in a depth direction. 21. The method of claim 20, Wherein the width of the element-to-element separator is 2 占 퐉 or less. 22. The method of claim 21, A second semiconductor layer formed between the substrate and the first semiconductor layer, and a third semiconductor layer formed between the first semiconductor layer and the element region, And the third semiconductor layer is the semiconductor layer disposed on the first semiconductor layer. 23. The method of claim 22, Wherein the substrate is a semi-insulating GaAs substrate, the first semiconductor layer is an AlGaAs layer, the second semiconductor layer is a GaAs layer, the third semiconductor layer is a semi-insulating GaAs layer, GaAs region.