JPH05275474A - Compound semiconductor integrated circuit and optical regenerative repeater - Google Patents

Abstract

PURPOSE:To enable very high speed operation, by forming adjacent field effect transistors(FET's), and further forming an element isolation trenches whose depth reaches a semiinsulative substrate. CONSTITUTION:By photolithography and reactive etching, an SiON film 62, a P-type GaAs layer 3 and an undoped GaAs buffer layer 2 are etched, thereby forming element isolation trenches 9 whose depth reaches a semiinsulative GaAs substrate 1. The trenches 9 are arranged so as to surround each FET. Thereby oscillation of fine currents between the FET's and the substrate can be restrained, low frequency oscillation of drain currents of adjacent FET's is prevented, and very high speed operation is enabled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor integrated circuit using a field effect transistor (FET) having an ultrahigh speed, and in particular, a compound semiconductor integrated circuit having an element isolation structure suitable for enhancing the high speed. Regarding

[0002]

2. Description of the Related Art A compound semiconductor integrated circuit using a conventional FET is discussed in, for example, Japanese Patent Laid-Open No. 2-49465. As shown in FIG. 3, the compound semiconductor integrated circuit is provided with an element isolation band 39 which reaches the semi-insulating GaAs substrate 31 between adjacent FETs (T1, T2, T3), and electrically isolates the FETs, particularly the side. The gate effect was improved. In FIG. 3, T1, T2 and T3 are HEMs.
A type FET called T, 32 is an undoped GaAs buffer layer, 33 is an n-type AlGaAs electron supply layer, 34 is an n-type GaAs contact layer, 35 is an ohmic electrode, 3
Reference numeral 7 is a gate electrode, and 38 is an element isolation band that does not reach the substrate 31.

Another conventional example is discussed in, for example, Japanese Patent Laid-Open No. 3-87044. As shown in FIG. 4, the compound semiconductor integrated circuit is provided with a heterojunction buffer layer 42 made of AlGaAs having a thickness of 1000 Å below a GaAsFET and an element isolation groove 46 reaching a heterojunction interface 44 between adjacent FETs. This has improved the electrical isolation of the FET, especially the side gate effect. In FIG. 4, 41 is a semi-insulating GaAs substrate, 43
Is a GaAs layer, 45 is an ohmic electrode, 47 and 48 are ohmic electrodes, and 49 is a gate electrode.

[0004]

When an amplifier circuit having a high gain is constructed by an FET using a compound semiconductor,
It is important to suppress the phenomenon called low frequency vibration together with the suppression of the side gate effect. This phenomenon of low frequency oscillation is a phenomenon in which the current flowing through the FET in the integrated circuit steadily self-oscillates even when there is no input signal.
Because its frequency is very low, around a few Hz at room temperature "
This is called "low frequency vibration." In the above-mentioned prior art, the effect of suppressing low frequency vibration is incomplete, and there is a problem that the integrated circuit according to the prior art operates abnormally. For example, a limit amplifier with a gain of 50 dB is used. When it was made, the low-frequency vibration generated in the integrated circuit was amplified, and there were many defects in which low-frequency vibration noise of a size that saturates the output amplitude was generated.

It is an object of the present invention to propose an element isolation structure capable of reducing low frequency vibrations, and to provide a compound semiconductor integrated circuit most suitable for ultra-high speed operation and an optical regenerator using the integrated circuit.

[0006]

In order to achieve the above object, first, an isolated semiconductor layer is formed on a semiconductor surface between adjacent field effect transistors by selective growth, and a device having a depth reaching a semi-insulating substrate. A separation groove was formed.

[0007]

[Function] We analyzed the mechanism of low-frequency vibration and obtained the following results. First, when a negative (direct current) voltage is applied to the element on the front surface of the substrate with respect to the electrode on the back surface of the substrate, when a certain voltage is reached, the current flowing between the substrate electrode and the element is at a low frequency of 0.4 Hz to 5 Hz. It begins to vibrate. When a semi-insulating GaAs substrate having a thickness of 600 μm is used, the magnitude of the current is about several nA, and the vibration amplitude is very small, 1 nA or less. This phenomenon is semi-insulating
It is understood that the aAs substrate has a negative resistance due to a deep level, and a high electric field domain travels from the element toward the substrate electrode.

However, when an FET is adjacent to the element, in the conventional element isolation technique, the high electric field domain running between the element and the substrate electrode changes the potential under the channel of the FET, and the drain current of the FET is changed. Have a great effect on. For example, the oscillation amplitude appearing in the drain current of an FET having a gate width of 50 μm adjacent to each other over a distance of 40 μm is 100 μA or more, and this large current oscillation seriously hinders the circuit operation.

In other words, by suppressing the phenomenon in which the minute current between the element and the substrate vibrates, it is possible to avoid the vibration of the drain current of the FET and suppress the low frequency vibration in the integrated circuit.

FIG. 5 is a graph showing the effect of the present invention. The vertical axis indicates -1 between the substrate backside electrode and the substrate surface element.
The oscillation amplitude of the current when 0 V was applied, and the horizontal axis represents the depth of the element isolation groove. The element isolation groove has a depth of 0.
The semi-insulating substrate is reached at 4 μm. In the conventional structure in which the isolated semiconductor layer is not formed, even if the element isolation groove is provided between the FETs and the depth of the isolation groove is increased, the effect of improving the low frequency vibration is not observed. However, in the structure in which the isolated semiconductor layer is arranged around the element, when the depth is 0.4 μm or more, that is, the depth reaching the semi-insulating substrate, the vibration amplitude is 0.2 n.
It can be seen that the frequency is reduced to A or less and the low frequency vibration can be remarkably improved. In the present invention, since the vibration of the minute current between the element and the substrate is suppressed in this way, the drain current of the adjacent FET also does not vibrate, and the vibration noise does not appear in the circuit operation.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A first embodiment of the present invention will be described below with reference to FIGS. 1 is a plan view of an element isolation structure, FIG. 2 is a cross-sectional structure diagram of a type of FET called HIGFET (Heterostructure Insulated-Gate FET) and the element isolation structure,
6A to 6C are sectional structural views showing the manufacturing process.

First, the manufacturing process will be described. Figure 6 (a)
In FIG. 3, an undoped GaAs buffer layer 2, a p-type GaAs layer 3, an n-type GaAs active layer 4, and an undoped AlGaAs layer 5 are successively grown on a semi-insulating GaAs substrate 1 by MBE (Molecular Beam Epitaxial) method. The substrate temperature during growth was preferably about 510 ° C. Here, the thickness and impurity concentration of each layer are as shown in Table 1.
As the semi-insulating GaAs substrate 1, an undoped LEC substrate or a Cr-doped LEC substrate is usually used. Undoped A
The composition ratio of the 1GaAs layer 5 is usually selected from Al0.3 Ga0.7 As.

[0013]

[Table 1] ─────────────────────────────────── Layer name Growth film thickness (nm) Impurity concentration ( 1 / cm3) Impurity ─────────────────────────────────── Undoped AlGaAs layer 5 24 − − n-type GaAs Active layer 4 15 3.6E18 Si p-type GaAs layer 3 300 3.0E16 Be undoped GaAs buffer layer 2 300 −− ───────────────────────── ─────────── Next, in FIG.
The surface of the semiconductor is covered with an O 2 film and the surface of the semiconductor other than the above is etched using a wet etchant. The etching depth is 200 nm. Next, after removing the SiO2 film,
600nm thick WSix (tungsten silicide)
The film is deposited by the sputtering method and subjected to photolithography and dry etching to form the heat resistant gate electrode 7. Here, it was appropriate that the composition ratio x of Si was 0.45. Further, in order to reduce the resistance between the source and the gate, Si may be ion-implanted after forming the heat resistant gate electrode 7. Ion implantation conditions in that case are
The acceleration energy is 40 keV and the dose amount is 1 × 10 14 / cm 2.

Next, in FIG. 6C, a 100 nm thick SiON film 62 is deposited on the entire surface by plasma CVD, and the source and drain electrode portions of the FET and the isolated semiconductor layer are formed by photolithography and reactive ion etching. The SiON film in the portion to be formed is etched to open a window. CF4 and O2 gas are usually used as the etching gas. Then, the semiconductor surface is further etched to a depth of 70 nm by the reactive ion etching method, and FE
Undoped A of the source and drain electrodes of T
The lGaAs layer 5 is removed. SiCl4 is used as the etching gas at this time.

Next, in FIG. 6 (d), a window-opened SiO film is formed.
Using the N film 62 as a mask, the high-concentration n-type selective growth layer 60 and the high-concentration n are formed by MOCVD (Metal Organic Thermal Decomposition) method.
The type isolated semiconductor layer 61 is grown at the same time. The growth temperature is usually 700 ° C., and trimethylgallium and arsine are used as source gases. The layers 60 and 61 have a thickness 320 of Si or Se doped at a concentration of 4 × 10 18 / cm 3.
nm GaAs. High concentration n-type isolated semiconductor layer 61
The shape of is a square with a side of 7 μm as shown in FIG.
They are arranged at equal intervals of 3 μm.

Next, referring to FIG. 6 (e), the SiON film 6 is formed by photolithography and reactive ion etching.
2, the p-type GaAs layer 3 and the undoped GaAs buffer layer 2 are etched to form an element isolation groove 9 having a depth reaching the semi-insulating substrate 1. The groove 9 has a width of 1 μm and a depth of 0.5 μm and reaches the semi-insulating GaAs substrate 1. As shown in FIG. 1, the shape of the groove 9 surrounds each FET. The high-concentration n-type isolated semiconductor layer 61 is arranged so as to surround the trench 9. Particularly in the processing of the groove 9, a reactive ion etching method called ECR is used, SiCl4 is used as an etching gas, microwave discharge power density is 1.54 kW / m2, and pressure is 44 m.
When processing is performed under the condition of Pa, even if a groove having a depth of 0.5 μm is formed, the side etch amount can be suppressed to 0.2 μm or less, and the processed shape of the groove 9 can be made extremely excellent.

After that, the ohmic electrode 8 is formed on the high-concentration n-type selective growth layer 60 by the lift-off method, and the element isolation structure and the field effect transistor as shown in FIGS. 1 and 2 are completed. After that, wiring is performed on the ohmic electrode 8 and the heat resistant gate electrode 7 to complete the integrated circuit. No wiring was formed in the high-concentration n-type isolated semiconductor layer 61, and the potential of the layer 61 was all float.

The effect of this embodiment will be described with reference to FIG. FIG. 7 is a graph in which drain currents of adjacent FETs are measured. The backside electrode of the substrate is 0V, the source potential of one FET is -8V, the source potential of the noted FET is -1V, FE
The spacing between T is 40 μm. The conventional element isolation structure oscillates with an amplitude of 100 μA or more, whereas the element isolation structure of the first embodiment shows a constant drain current.
The low frequency vibration phenomenon could be completely prevented.

As described above, according to the first embodiment, by suppressing the vibration of the minute current between the FET and the substrate, the adjacent FET is
It is possible to prevent low frequency oscillation of the drain current of the.

Further, according to the first embodiment, since the pattern density of the high-concentration n-type selective growth layer 60 and the high-concentration n-type isolated semiconductor layer 61 is high and almost uniform in the chip, the MOC
This has the effect of making the in-plane distribution of the selectively grown film thickness by the VD method uniform.

In the first embodiment, the type of FET is HI.
GFET, but of course these are MESFET (MEt
It may be an al-Semiconductor Field Effect Transistor) or a HEMT (High-Electron Mobility Transistor).

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 8 is a sectional structural view of the HIGFET and the element isolation structure. The difference from the first embodiment is that the undoped GaAs buffer layer 8 is used instead of the undoped GaAs buffer layer 2.
2. An undoped AlGaAs buffer layer 83 and an undoped GaAs buffer layer 84 are provided, and an element isolation groove 89 is further provided to a depth reaching the undoped AlGaAs buffer layer 83. The film thickness of the undoped GaAs buffer layer 82 is 100 nm, and undoped AlGaA
The thickness of the s buffer layer 83 is 300 nm and the composition ratio is Al0.
The film thickness of 3 Ga0.7 As and undoped GaAs buffer layer 84 was 300 nm.

According to the second embodiment, since the low frequency oscillation phenomenon of the HIGFET can be suppressed and the side gate breakdown voltage is improved, the distance between the FETs can be reduced to about 15 μm. As a result, band deterioration due to the wiring capacitance and wiring inductance between the FETs is improved, and the high speed operation of the integrated circuit can be improved. It also has the effect of reducing the chip area and reducing the production cost.

Next, a third embodiment of the present invention will be described with reference to FIGS. 9, 10 and 11. FIG. 9 is a circuit diagram of a basic amplifier,
FIG. 10 is a block diagram of the limit amplifier, and FIG.
1 is a block diagram of an optical regenerator.

The third embodiment is an example in which the element isolation structure shown in the first or second embodiment is specifically applied to an integrated circuit and an optical regenerator. First, F of the circuit diagram shown in FIG.
ET was formed using the element isolation structure as shown in FIGS. 1 and 2 or the element isolation structure shown in FIG. 8 to form a single-stage basic amplifier. An FET having a short-circuited source and drain is usually used as the diode, and the element isolation structure of the present invention is also used as the isolation structure. Gate length is 0.3 for FET
A μm HIGFET was used. Next, as shown in FIG. 10, four basic amplifiers are combined to form a limit amplifier integrated circuit. This limit amplifier is used as the timing extraction circuit in FIG. 11 to construct an optical regenerator for optical communication.

According to the third embodiment, it is possible to realize a high-gain, ultra-high-speed limit amplifier which does not have noise due to low-frequency vibration, and an optical regenerative repeater that operates normally at ultra-high speed, for example, 10 gigabits per second.

In the third embodiment, the basic amplifier circuit shown in FIG. 9 may be applied to the preamplifier, the variable gain amplifier, the main amplifier and the discriminator shown in FIG. In that case, noise due to low frequency vibration in each integrated circuit can be suppressed, and the receiving sensitivity of the optical regenerator can be further improved.

Next, a fourth embodiment of the present invention will be described with reference to FIG. The difference from the first embodiment is the high-concentration n-type isolated semiconductor layer 61.
Is a line in which only one row is arranged around the element isolation groove 9.

According to the fourth embodiment, the layer 61, the groove 9 and the FET are used in the process of manufacturing the mask drawing of the integrated circuit.
You can register and work as one set of data,
The efficiency of mask layout work can be improved.
Further, the amount of numerical data at the time of manufacturing a mask is significantly reduced, so that it is possible to reduce the cost for computer processing at the time of manufacturing a mask.

Next, a fifth embodiment of the present invention will be described with reference to FIG. The difference from the first embodiment is the high-concentration n-type isolated semiconductor layer 61.
The point is that an isolated ohmic electrode 98 is used instead of.
The electrode 98 has no wiring and its potential is all floating.

According to the fifth embodiment, the electrode 98, which is an isolated pattern, can be formed by a process independent of the high concentration n-type selective growth layer 60. For example, the formation process of the layer 60 is an ion implantation method. Changes such as changes can be made, and the process flexibility can be increased.

[0032]

According to the present invention, it is possible to provide an integrated circuit and an optical regenerator using a compound semiconductor field effect transistor which can suppress a low frequency oscillation phenomenon in the field effect transistor and its integrated circuit and which is optimum for an ultra-high speed operation. You can

[Brief description of drawings]

FIG. 1 is a plan view of an element isolation structure according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a field effect transistor and an element isolation structure of Example 1 of the present invention.

FIG. 3 is a diagram showing an example of a conventional element isolation structure.

FIG. 4 is a diagram showing an example of a conventional element isolation structure.

FIG. 5 is a diagram showing an effect of the present invention.

6 (a) to 6 (e) are cross-sectional structural views illustrating a manufacturing process of a field effect transistor and an element isolation structure of Example 1 of the present invention.

FIG. 7 is a graph showing the effect of the first embodiment of the present invention.

FIG. 8 is a sectional view of a field effect transistor and an element isolation structure of Example 2 of the present invention.

FIG. 9 is a circuit diagram of a basic amplifier according to a third embodiment of the present invention.

FIG. 10 is a block diagram of a limit amplifier according to a third embodiment of the present invention.

FIG. 11 is a configuration diagram of an optical regenerator according to a third embodiment of the present invention.

FIG. 12 is a plan view of an element isolation structure of Example 4 of the present invention.

FIG. 13 is a plan view of an element isolation structure of Example 5 of the present invention.

[Explanation of symbols]

1 ... Semi-insulating GaAs substrate, 2 ... Undoped GaAs buffer layer, 3 ... P-type GaAs layer, 4 ... N-type GaAs active layer, 5 ... Undoped AlGaAs layer, 7 ... Heat-resistant gate electrode, 8 ... Ohmic electrode, 9 ... Element isolation groove, 31 ... Semi-insulating GaAs substrate, 32 ... Undoped GaAs buffer layer, 33 ... N-type AlGaAs electron supply layer, 34 ... N-type GaAs contact layer, 35 ... Ohmic electrode, 37 ...
Gate electrode, 38 ... Element isolation band, 39 ... Element isolation band, 4
1 ... Semi-insulating GaAs substrate, 42 ... AlGaAs buffer layer, 43 ... GaAs layer, 44 ... Heterojunction interface, 45
... Ohmic electrodes, 46 ... Isolation trenches between elements, 47, 48 ...
Ohmic electrode, 49 ... Gate electrode, 60 ... High-concentration n-type selective growth layer, 61 ... High-concentration n-type isolated semiconductor layer, 62 ... S
iON film, 82 ... Undoped GaAs buffer layer, 83
... undoped AlGaAs buffer layer, 84 ... undoped GaAs buffer layer, 89 ... element isolation trench, 98 ... isolated ohmic electrode, T1 to T3 ... FET (HEMT).

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Reference number within the agency FI Technical indication location H04B 10/16 (72) Inventor Junji Shigeta 1-280, Higashi-Kengokubo, Kokubunji-shi, Tokyo Hitachi Central In the laboratory

Claims (6)

[Claims] 1. A compound semiconductor integrated circuit comprising a plurality of field effect transistors formed by epi growth on a semi-insulating substrate, wherein an isolated semiconductor layer selectively grown on a semiconductor surface between adjacent field effect transistors. A compound semiconductor integrated circuit, wherein an element isolation groove reaching the semi-insulating substrate is provided between adjacent field effect transistors. 2. A compound semiconductor integrated circuit comprising a plurality of field effect transistors having a heterojunction buffer layer, wherein a selectively grown isolated semiconductor layer is provided on and adjacent to a semiconductor surface between adjacent field effect transistors. A compound semiconductor integrated circuit characterized in that an element isolation groove reaching a heterojunction interface is provided between field effect transistors. 3. The compound semiconductor integrated circuit according to claim 1 or 2, wherein the element isolation trench is formed so as to surround each field effect transistor, and the isolated semiconductor layer is formed in the element isolation trench. A compound semiconductor integrated circuit characterized in that a plurality of them are arranged outside. 4. The compound semiconductor integrated circuit according to claim 3, wherein the isolated semiconductor layers are arranged at equal intervals outside the element isolation trench, and the intervals of the isolated semiconductor layers are greater than the width of the isolated semiconductor layers. A compound semiconductor integrated circuit characterized by being short. 5. A compound semiconductor integrated circuit comprising a plurality of field effect transistors, wherein an electrode not electrically connected to another element is provided on the semiconductor surface between adjacent field effect transistors, and the adjacent field effect transistors are provided. A compound semiconductor integrated circuit characterized in that an element isolation groove reaching a semi-insulating substrate is provided between transistors. 6. An optical regenerator using the compound semiconductor integrated circuit according to any one of claims 1 to 5.