JP3319486B2 - Heterojunction semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a semiconductor device having a heterojunction compound semiconductor lamination and a manufacturing technique thereof.

[0002]

2. Description of the Related Art There are many compound semiconductor devices having a heterojunction compound semiconductor stack. For example, a heterojunction FET (HFET) which is a kind of a field effect transistor (FET) (a high electron mobility transistor (HE
MT)), a compound semiconductor layer having a relatively narrow band gap (carrier traveling layer) serving as a traveling channel for a two-dimensional electron (hole) gas and a compound semiconductor barrier layer having a relatively wide band gap (in the case of HEMT, An impurity-doped carrier supply layer) forms a heterojunction.

[0003] A narrow potential valley is formed at the interface of the carrier traveling layer and the barrier layer to provide a traveling channel for a two-dimensional electron gas. Doping the barrier layer to n-type,
When the carrier transit layer is non-doped or has a low impurity concentration, a high electron mobility transistor (HEMT) is obtained.

[0004] Even if the barrier layer is not doped, a traveling channel for a two-dimensional electron gas is formed. For example, a current flows when carriers are supplied from a source electrode. The lower the impurity concentration of the carrier transit layer, the higher the mobility becomes possible, but the carrier transit layer may be doped. Holes may be used as carriers. A HEMT-like transistor including these modifications is an HFET.

[0005] Complementary HFETs (H
When configuring an EMT) circuit, a carrier traveling channel / barrier layer for the n-channel and a carrier traveling channel / barrier layer for the p-channel are usually laminated.

[0006] In order to form a transistor using a semiconductor layer disposed on the lower side, the semiconductor layer disposed on the upper side is removed by etching. In particular, when mass-producing integrated circuit devices, it is necessary to accurately control the amount of etching to make the characteristics of the semiconductor elements uniform.

FIGS. 8A to 8C show an example of a method for manufacturing a complementary HFET according to the prior art. Note that this HFE
T is a so-called HEMT. As shown in FIG. 8A, an i-type GaAs layer 82, a p-type AlGaAs layer 83, an i-type GaAs layer 84, an n-type GaAs layer 82 are formed on a semi-insulating GaAs wafer 81 by metal organic chemical vapor deposition (MOCVD). AlG
The aAs layer 85 and the i-type GaAs layer 86 are stacked in this order.

As shown in FIG. 8B, a resist mask 89 having an opening in a region for forming a p-type HFET is formed on the wafer surface, and an i-type GaAs layer 86 is formed by using an aqueous solution of H ₂ O ₂ + HF as an etchant. , N-type AlGaAs layer 8
5 and a part of the i-type GaAs layer 84 are etched so that the i-type GaAs layer 84a of a predetermined thickness remains. After that, the resist mask 89 is removed.

[0009] As shown in FIG.
By forming a Si layer and patterning using a resist mask or the like, a gate electrode Gn for an n-type HFET is formed.
Then, a gate electrode Gp for a p-type HFET is formed.

Next, a resist mask for exposing the ohmic electrode formation region of the p-type HFET is formed, and Be
And F are ion-implanted. In addition, B as a p-type impurity
Mg or the like may be used instead of e. Further, F that increases the activation rate of impurities may be omitted.

Next, a resist mask for exposing the ohmic electrode formation region of the n-type HFET is formed, and Si ions are implanted. After ion implantation of these p-type and n-type impurities, the wafer is heated to perform activation annealing. By this annealing, the Si implantation region becomes the n ⁺ type region 87, and Be,
The F implantation region becomes the p ⁺ type region 88.

Next, a resist mask having an opening having a shape for separating the n-type HFET and the p-type HFET is formed, and oxygen ions are implanted to form an isolation region 91.

Thereafter, a resist mask having an opening in an ohmic electrode forming region is formed for each of the p-type HFET and the n-type HFET, an ohmic electrode material is deposited, lift-off is performed, and alloying is performed. Form S / D. As the source / drain electrodes S / Dn of the n-type HFET, an AuGe layer, N
A stacked layer of an i layer and an Au layer is used, and a stacked layer of an Au layer, a Zn layer, and an Au layer is used as a source / drain electrode S / Dp of a p-type HFET. Thereafter, the n-type HFET and the p-type HF
Wiring is connected to each electrode of ET.

An i-type G forming a channel of a p-type HFET
The aAs layer 82 is separated from the gate electrode Gp by the p-type AlGaAs layer 83 and the remaining i-type GaAs layer 84a. Therefore, the threshold voltage of the p-type HFET changes depending on the thickness of the remaining i-type GaAs layer 84a. p
In order to make the characteristics of the type HFET uniform, the i-type GaAs layer 8
It is necessary to precisely control the etching amount of No. 4.

Since the region where the p-type HFET is to be formed is exposed by isotropic wet etching, a slope appears around the region. This slope area is difficult to use as a device area.

[0016]

It is not easy to efficiently and accurately etch a heterojunction structure in which two or more compound semiconductor layers are stacked.

An object of the present invention is to provide a heterojunction semiconductor device which is easy to manufacture and whose characteristics are easy to control. It is another object of the present invention to provide a method of manufacturing a heterojunction field effect transistor including an etching step capable of efficiently and accurately etching a hetero-stacked structure.

[0018]

A heterojunction semiconductor device according to the present invention comprises: a semiconductor substrate; a first compound semiconductor layer formed on the semiconductor substrate and containing no Al in the composition;
Al is formed on the first compound semiconductor layer and has a composition of Al.
And a third compound semiconductor layer formed only on a portion of the second compound semiconductor layer and containing no Al in the composition, and a third compound semiconductor layer containing no Al in the composition. A fourth compound semiconductor layer formed and containing Al in the composition; and a first compound semiconductor layer formed on the second compound semiconductor layer.
And a second set of electrodes formed on the fourth compound semiconductor layer and forming a terminal of the second field effect transistor. A fifth compound semiconductor layer formed on the second compound semiconductor layer between the second compound semiconductor layer and the third compound semiconductor layer and containing no Al in the composition; A sixth compound semiconductor layer formed on the fifth compound semiconductor layer and containing Al in the composition.

According to the present invention, there is provided a method of manufacturing a heterojunction field effect transistor, comprising: a semiconductor substrate; a first compound semiconductor layer formed on the semiconductor substrate and containing no Al in a composition; A second compound semiconductor layer formed on the layer and containing Al in the composition; a third compound semiconductor layer formed on the second compound semiconductor layer and containing no Al in the composition; A part of the third compound semiconductor layer and a fourth compound semiconductor layer of a semiconductor stack including a fourth compound semiconductor layer formed on the compound semiconductor layer and containing Al in the composition, containing Cl or Br. , A first etching step of etching with an etching gas not containing F, and a second etching step of etching the remainder of the third compound semiconductor layer with an etching gas containing F and Cl or F and Br subsequent to the first etching step. Etch Wherein the semiconductor stack is further formed on the second compound semiconductor layer between the second compound semiconductor layer and the third compound semiconductor layer, and the fifth semiconductor layer does not contain Al in the composition. The compound semiconductor layer of
And a sixth compound semiconductor layer containing Al in the composition, wherein the second etching step automatically stops at the surface of the sixth compound semiconductor layer.

[0020]

When a compound semiconductor layer containing Al and a compound semiconductor layer not containing Al are stacked, the compound semiconductor layer containing Al is used as an etch stop layer by adding F to an etching gas. Can be. A
Since the compound semiconductor layer containing 1 can be substantially prevented from being etched by dry etching using an etching gas containing F, accurate etching can be performed.

Since the etching can be controlled accurately, the characteristics of the manufactured heterojunction semiconductor device can be controlled accurately.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.
You. FIG. 1A shows a configuration example of an etching apparatus. main
The etching gas source 1 is, for example, SiCl_FourIncluding gas
The main etch of the airtight chamber 8 via the electromagnetic valve 2a.
Connected to the blowing gas supply port 4a. Additive gas
Source 3 is, for example, SF ₆The gas is stored in the solenoid valve 2b.
Connected to the additive gas supply port 4b of the hermetic chamber 8
Have been.

The degree of opening and closing of the electromagnetic valves 2a, 2b is controlled by control signals supplied via control lines 6a, 6b from the control circuit 5. In the airtight chamber 8, parallel plate electrodes 13a and 13b are arranged.

The lower electrode 13b is connected to the ground potential, on which the wafer 11 to be processed can be mounted. The electrode 13a arranged on the upper side
It is connected to a high frequency power source 14. Airtight chamber 8
Is connected to the exhaust device 9, and the inside thereof can be exhausted to a desired degree of vacuum.

The inside of the airtight chamber 8 is evacuated, and an etching gas is supplied at a predetermined pressure from the main etching gas supply port 4a.
When high-frequency power is supplied between the opposed electrodes 13a and 13b,
An etching gas plasma is generated.

A window 15 is provided at a position of the airtight chamber 8 where light emitted from the plasma can be received. An optical fiber 16 is connected to the window 15 so that light from the incident plasma emission can be led out. The optical fiber 16 is connected to a spectroscope 17 and can separate plasma emission.

The monochromatic light separated by the spectroscope 17 is
It is supplied to a detection circuit 18 including a photodetector such as a high electron multiplier, and generates a detection signal. The detection signal of the detection circuit 18 is supplied to the control circuit 5 via the signal line 21. Other signals such as an etching start signal and an etching end signal are also supplied to the control circuit 5.

The wafer 11 to be etched is Ga
The case where the main etching gas is SiCl ₄ and the additive gas is SF ₆ , including the alternate lamination of the As layer and the AlGaAs layer, will be described below.

FIG. 1B is a graph showing the relationship between the etching rate for GaAs and A when SF ₆ gas is added to SiCl ₄ gas.
4 is a graph showing an etching rate for 1GaAs. In the figure, the horizontal axis indicates the flow rate (addition amount) of the SF ₆ gas with respect to the total flow rate of the SiCl ₄ gas and the SF ₆ gas in V%, and the vertical axis indicates the etching rate in Å / min.

When etching is performed using only SiCl ₄ gas without adding any SF ₆ gas, the etching rate for GaAs is almost equal to the etching rate for AlGaAs. When SF ₆ gas is added to SiCl ₄ gas, the etching rate for GaAs increases slowly, whereas the etching rate for AlGaAs decreases sharply.

When about 20% of SF ₆ gas is added, A
The etching rate for 1GaAs is 1/80 or less of the etching rate for GaAs, and when 30% or more of SF ₆ gas is added, the etching rate for AlGaAs is about 1/10 of the etching rate for GaAs.
0 or less. As described above, when there is a difference of about two digits in the etching rate, it can be considered that the layer having a low etching rate is hardly etched. This state is called a substantially non-etched state.

When SiCl ₄ gas is supplied from the main etching gas source 1 into the hermetic chamber 8 and high-frequency power is supplied between the counter electrodes from the high-frequency power source 14, plasma is generated inside the hermetic chamber 8 and the surface of the wafer 11 is generated. Etching proceeds at a substantially constant speed whether or not is GaAs or AlGaAs. The addition of more than a predetermined amount of SF ₆ gas to the SiCl ₄ gas, AlGaAs will not be substantially etched.

FIG. 2A shows an example of the structure of a hetero-stacked structure in which etching can be efficiently and accurately performed using the etching apparatus shown in FIG. Substrate 2
On n, n sets of a GaAs layer L and an AlGaAs layer K are stacked, and a resist mask 24 having an opening is formed thereon. Such a substrate 22 is placed on the lower electrode 13b of the etching apparatus shown in FIG. 1A, and the GaAs / AlGaAs stack exposed at the opening is etched.

FIG. 2B shows a state in which the substrate shown in FIG. 2A is mounted on the flat electrode 13b of the etching apparatus shown in FIG. 1A, and a main etching gas of SiCl ₄ is supplied. FIG. 3 is a schematic diagram showing a detection signal supplied by a detection circuit 18 when etching is performed. The spectroscope 17 is made of Al-C
is set to 261 nm, which is the emission peak wavelength of 1-bond,
The detection circuit 18 detects light having a wavelength of 261 nm.

While the uppermost GaAs layer L1 is being etched, there is no Al in the composition and no emission peak of the Al-Cl bond occurs, so that the detection signal of the detection circuit is at a low level. When the etching of the next AlGaAs layer K1 starts, the light emission of the Al—Cl bond starts and the detection circuit 1
The detection signal 8 changes to high level. When the etching of the AlGaAs layer K1 ends, the emission peak of the Al—Cl bond disappears, and the detection signal changes to a low level.

While the second set of GaAs layers L2 is being etched, no emission peak of Al-Cl bond is generated, and the detection signal is kept at a low level. Second set of AlGaAs
When the etching of the layer K2 starts, the emission intensity of the Al-Cl bond changes to the high level again.

As described above, while the GaAs layer is being etched, light emission of Al—Cl bond does not occur, and AlGaAs is not etched.
When the s layer is etched, light emission of an Al-Cl bond occurs, and the detection signal changes to a high level. In this manner, by monitoring the detection signal of the detection circuit, it is possible to know which layer is currently being etched.

When the etching is to be stopped at the surface of the i-th set of AlGaAs layer Ki, the (i-1) -th
After the luminescence peak of the l-Cl bond disappears, a predetermined amount of SF ₆ gas as an additional gas is added. SF for etching gas
_{When 6} is added, the i-th GaAs layer Li is etched, but when the AlGaAs layer is exposed on the wafer surface, a fluorine compound of Al is formed, the etching rate is rapidly reduced, and substantially no etching is performed. State.

After etching with SiCl ₄ + SF ₆ gas for a time sufficient to etch the i-th GaAs layer Li, the high-frequency (RIE) power is turned off and the supply of the etching gas is stopped. AlGaAs layer Ki
Etching stops with the surface exposed.

As described above, the predetermined emission peak during plasma emission is detected to monitor which layer is currently being etched, and the SF is determined during the etching of the GaAs layer L.
By adding a predetermined amount of ₆ gases, the next AlGaAs
Etching can be stopped at the layer surface.

By etching the stack with an etching gas capable of etching both the GaAs layer and the AlGaAs layer until reaching the layer to be etched last,
Etching can proceed efficiently. When the additive gas is added, the etching stops automatically,
Etching can be stopped with high accuracy and uniformity.

The case where the GaAs layer is laminated on the AlGaAs layer to form one set of units has been described.
Similar control can be performed even if an AlGaAs layer is disposed on the layer. The composition of each set of AlGaAs layers need not be the same.

Although the case where a layer containing Al as a component and a layer containing no Al as a component are etched is described above, a combination of a layer capable of greatly changing the etching rate and automatically stopping the etching is used. Is Al
It is not limited to a combination of a layer containing Al and a layer not containing Al.
Etching can be automatically stopped for the layer containing In and the layer not containing In using the same etching gas and additive gas. The SiCl ₄ gas can etch both the layer containing In and the layer not containing In almost equally, but when SF ₆ is added to SiCl ₄ by a predetermined amount or more, the InCl
Is not etched.

Therefore, when SiCl ₄ is used as the main etching gas and SF ₆ is used as the additional gas, the etching can be automatically stopped at the surface of the layer containing In. As an example of such a configuration, as a layer containing In, InGaAs is used.
There is a configuration in which a GaAs layer is stacked as an s layer and a layer not containing In.

SiC is used as a gas capable of performing etching regardless of whether Al or In is contained.
was used l _4, In addition, it is also possible to use a CCl ₄ gas.

Further, the layer containing Al or In
SF as an additive gas for stopping₆Using gas
However, as a gas exhibiting the same function, carbon tetrafluoride C
F_Four, Chlorofluorocarbon CCl_xF_y, Hydro
Chlorofluorocarbon CH _xCl_yF_z, Hydrof
Luorocarbon CH_xF_yHalon CBr containing fluorine _x
Cl_yF_zUse one or a combination of
Can be.

Examples of the chlorofluorocarbon include CClF ₃ , CCl ₂ F ₂ and CCl ₃ F. Examples of hydrochlorofluorocarbons include CHClF
₂ , CHCl ₂ F and CH ₂ ClF. Examples of hydrofluorocarbons include CHF ₃ and CH ₃ F.

FIGS. 3A and 3B show another example of a hetero-junction laminated structure capable of performing etching efficiently and with high accuracy by such etching. FIG.
(A) shows a layer L not containing Al and In on a substrate 22.
A shows a configuration in which A and layers LB containing Al and / or In are alternately stacked. A resist mask 24 is formed on the hetero laminated structure. While only the main etching gas is used, the layer A containing no Al and In is used.
1 and the layer LB containing Al or In can be etched together. In the case where a layer containing Al is included, the emission intensity is monitored at a wavelength of 261 nm.
Light emission of Cl bond can be detected.

When a layer containing In is used, the emission of In can be monitored by monitoring the emission intensity at 451 nm. The intensity of these emission peaks is monitored, and after the i-th emission peak has disappeared, if an additional gas is added in a predetermined amount or more, the (i + 1) th Al or I
Etching stops automatically on the surface of the layer containing n.

The hetero-junction stacked structure is not limited to the two types of stacked structures of a layer containing Al or In and a layer not containing Al and In. For example, as shown in FIG. 3B, in a structure in which three types of layers LA, LB, and LC are sequentially stacked, one of the three types of layers is a layer containing Al or In, and the other is a layer containing Al or In. When the layer does not contain In, the same control can be performed.

The layer containing Al or In need not be a single layer. The layer containing Al and the layer containing In contain Al and I
When laminated with a layer not containing n, the spectroscope 1
7, the emission peak at 261 nm and the emission peak at 451 nm can be alternately or simultaneously detected.

The etchant gas A is composed of a layer having a composition x and a composition y.
When the gas B is added to the etchant gas A, when the layer having the composition x can be etched but the layer having the composition y cannot be etched, the above-described etching method can be similarly performed.

FIG. 4 shows a method of manufacturing a complementary HFET to which such etching control can be suitably applied. As shown in FIG. 4A, the semi-insulating GaAs substrate 3
1 on which a thickness of about 500 nm is formed by molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD).
i-type GaAs layer 32 having a thickness of about 20 nm, a p-type Al _0.3 Ga _0.7 As layer 3 having a thickness of about 20 nm and a Mg concentration of about 2 × 10 ¹⁸ cm ⁻³
3. i-type GaAs layer 34 having a thickness of about 5 nm;
I-type AlGaAs layer 35, i-type Ga with a thickness of about 30 nm
As layer 36, thickness about 30 nm, Si concentration about 2 × 10 ¹⁸ c
n-type Al _0.3 Ga _0.7 As layer 37 m ^-3, growing i-type GaAs layer 38 having a thickness of 5nm epitaxially in this order.

As shown in FIG. 4B, a resist mask 39 having an opening at a portion where a p-type HFET is to be formed is formed.
It is formed on the heterojunction epitaxial stack shown in FIG. The wafer on which the resist mask 39 is formed is shown in FIG.
The device is mounted in an etching apparatus as shown in (A), and the opening is etched to stop the etching on the surface of the i-type AlGaAs layer 35. This etching control
This will be described with reference to FIG.

In FIG. 5, the uppermost stage has a wavelength of 261 nm.
5 shows a monitor signal of the light emission intensity of the above. 5 schematically shows the supply state of the main etching gas SiCl ₄ gas and the supply state of the additional gas SF ₆ gas. S
When only iCl ₄ gas is supplied and plasma is generated,
Etching starts. While the uppermost i-type GaAs layer 38 is being etched, Al-Cl having a wavelength of 261 nm is used.
No combined emission peak occurs.

When the etching of the i-type GaAs layer 38 is completed and the etching of the next n-type AlGaAs layer 37 is started, light emission of the Al—Cl bond starts. Therefore,
The monitor signal changes to a high level.

When the etching of the n-type AlGaAs layer 37 is completed, the emission peak at a wavelength of 261 nm disappears. Detecting the end of the monitor signal, to start the addition of the additive gas SF _6. The etching gas becomes a mixed gas of the main etching gas SiCl ₄ and the additive gas SF ₆ . This mixed gas etches the i-type GaAs layer 36, but cannot substantially etch the i-type AlGaAs layer 35 disposed thereunder. Therefore, the etching is automatically stopped with the i-type AlGaAs layer 35 exposed.

The i-type GaAs layer 36 is etched for a time enough to completely etch the i-type GaAs layer 36, and then the high-frequency power, the main etching gas, and the added gas are stopped.

In this manner, the state shown in FIG. 4B can be obtained by automatically stopping the dry etching.
Thereafter, the photoresist mask 39 is removed. FIG.
(C) forming a WSi layer on the wafer surface,
By patterning using a photoresist mask or the like, a gate electrode Gn of an n-type HFET and a gate electrode Gp of a p-type HFET are formed.

The gate electrode Gn thus formed,
Using Gp and a photoresist mask, source / drain regions of an n-type HFET and a p-type HFET are formed.
For example, an n-type impurity-doped region 41 is formed by implanting Si _4, and a p-type impurity-doped region 42 is formed by implanting Be or Mg and F ions. Be and Mg are p-type impurities, and F is an additive for improving the activation rate of the impurities. F need not always be used.

After forming these ion-implanted regions, the resist mask, if any, is removed, and annealing for activating impurities is performed. When the impurities are activated by annealing, an n ⁺ type region 41 and ap ⁺ type region 42 are formed.

Thereafter, in order to separate the p-type HFET and the n-type HFET, a photoresist mask exposing the separation region is formed, and oxygen ions are implanted to form an oxygen ion implantation separation region 43.

Next, a resist mask for exposing a region for forming an ohmic electrode of the n-type HFET is formed, and an AuGe layer, a Ni layer, and an A layer for forming an n-type ohmic electrode are formed.
A stack of u layers is deposited and lifted off to form an ohmic electrode S / Dn of an n-type HFET.

Subsequently, a photoresist mask exposing a region for forming the ohmic electrode of the p-type HFET is formed.
an Au layer and a Zn layer for forming a p-type ohmic electrode;
By depositing an Au layer and lifting off, p-type HFE
A T ohmic electrode S / Dp is formed.

Thereafter, one of the source / drain electrodes S / Dn of the n-type HFET and one of the source / drain electrodes S / Dp of the p-type HFET are connected by wiring, and the p-type HFET is connected.
Gate electrode Gn of FET and gate electrode G of p-type HFET
p is connected by wiring.

When other necessary wirings are formed, the complementary H
The FET circuit is completed. In the embodiment of FIG. 4, the p-type HFET is located at the bottom and the n-type HFET is located at the top, but these arrangements can be reversed.

FIG. 6 shows a configuration example in which an n-type HFET is arranged on the lower side and a p-type HFET is arranged on the upper side. Semi-insulating G
An i-type GaAs layer 32 and an n-type Al
GaAs layer 37, i-type GaAs layer 34, i-type AlGaAs
s layer 35, i-type GaAs layer 36, p-type AlGaAs layer 3
3. An i-type GaAs layer 38 is sequentially epitaxially grown. That is, the n-type AlGaAs layer 37 and the p-type AlGa
The As layer 33 creates an exchanged configuration as compared with the configuration of FIG.

The heterojunction stacked structure in FIG. 6 is the same as the structure in FIG. 4 in terms of a layer containing Al or a layer not containing Al, so that an equivalent etching process or the like can be performed. In this manner, a configuration in which the p-type HFET is arranged on the upper side and the n-type HFET is arranged on the lower side can be created.

4 and 6, an i-type AlGaAs layer 35 was used to automatically stop the etching. This i-type AlGaAs layer is not always necessary.
FIG. 7 shows another configuration example of the complementary HFET circuit. On a semi-insulating GaAs substrate 31, an i-type GaAs layer 32, i
-Type AlGaAs layer 33, i-type GaAs layer 35, n-type Al
A GaAs layer 36 is stacked. The p-type HFET has an i-type AlGaAs layer 33 on an i-type GaAs layer 32,
Although the configuration is different from the so-called HEMT,
The same operation is performed.

When this heterojunction laminated structure is subjected to the same etching as in the embodiment of FIG.
Stop at the surface of the lGaAs layer 33. Thereafter, by performing steps similar to those shown in FIG. 4, the configuration shown in FIG. 7 can be obtained.

In this configuration, the electrodes of the p-type HFET are formed directly on the surface of the i-type AlGaAs layer 33.
In the n-type HFET, the n-type AlGaAs layer 3
6 The electrodes are formed directly on the surface. Also in this configuration, the etching can be automatically stopped at the surface of the i-type AlGaAs layer 33 by adding SF ₆ gas during the etching of the i-type GaAs layer 35. Therefore,
Etching can be performed efficiently and with high precision.

The case where a complementary HFET circuit is formed has been described above, but the present invention is not limited to these embodiments. For example, the present invention can be similarly used for manufacturing a group III-V compound semiconductor optical device in which a layer containing Al or In and a layer not containing Al and In are stacked.

It will be apparent to those skilled in the art that various changes, improvements, combinations, and the like can be made.

[0074]

As described above, by using the main etching gas and the additive gas, the etching can be automatically stopped and efficient and highly accurate etching can be performed.

When a complementary field effect type circuit is manufactured, a high-performance circuit with uniform characteristics, high yield, and high yield can be manufactured.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram and a graph showing an etching apparatus and an etching rate used in an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a configuration example of a heterojunction laminated structure to be etched and a signal waveform of a monitor signal.

FIG. 3 is a schematic cross-sectional view showing another example of the hetero junction stacked structure.

FIG. 4 is a schematic cross-sectional view for explaining a method of manufacturing a complementary HFET structure.

FIG. 5 is a timing chart for explaining an etching step.

FIG. 6 is a schematic sectional view showing another configuration example of the complementary HFET structure.

FIG. 7 is a schematic sectional view showing another configuration example of the complementary HFET structure.

FIG. 8 is a schematic cross-sectional view for explaining a method of manufacturing a complementary HFET structure according to the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Main etching gas source 2 Valve 3 Additive gas source 4 Gas supply port 5 Control circuit 6 Control line 8 Hermetic chamber 9 Exhaust device 11 Wafer 13 Counter electrode 14 High frequency power supply 15 Window 16 Optical fiber 17 Spectroscope 18 Detection circuit 21 Signal line 22 Substrate 24 Resist mask 31 Semi-insulating GaAs substrate 32 i-type GaAs layer 33 p-type (i-type) AlGaAs layer 34, 36, 38 i-type GaAs layer 35 i-type AlGaAs layer 37 n-type AlGaAs layer

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-67275 (JP, A) JP-A-64-12581 (JP, A) JP-A-5-36972 (JP, A) JP-A-6-127 29573 (JP, A) JP-A-4-63425 (JP, A) Applied Physics Letters, U.S.A., October 5, 1987, Vol. 51, No. 14, p. 1083− 1085 (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/095 H01L 21/338 H01L 29/778 H01L 29/812 H01L 21/3065

Claims (3)

(57) [Claims] A first compound semiconductor layer formed on the semiconductor substrate and not containing Al in the composition; a first compound semiconductor layer formed on the first compound semiconductor layer and containing Al in the composition;
A third compound semiconductor layer formed only on a portion on the second compound semiconductor layer and containing no Al in the composition; and a second compound semiconductor layer on the third compound semiconductor layer. Formed, and in the composition
A fourth compound semiconductor layer comprising: a first set of electrodes formed on the second compound semiconductor layer and constituting a terminal of a first field-effect transistor; and And a second set of electrodes forming a terminal of a second field-effect transistor, and further comprising a second compound between the second compound semiconductor layer and the third compound semiconductor layer. A is formed on the semiconductor layer, and A
a fifth compound semiconductor layer not containing l, formed on the fifth compound semiconductor layer,
And a sixth compound semiconductor layer including: 2. A semiconductor substrate; a first compound semiconductor layer formed on the semiconductor substrate and containing no Al in the composition; and a first compound semiconductor layer formed on the first compound semiconductor layer and containing Al in the composition. A second compound semiconductor layer, a third compound semiconductor layer formed on the second compound semiconductor layer and containing no Al in the composition, and a third compound semiconductor layer formed on the third compound semiconductor layer and containing A first compound semiconductor layer including a fourth compound semiconductor layer including Al and a part of the third compound semiconductor layer and a part of the third compound semiconductor layer are etched with an etching gas containing F or F containing Cl or Br; An etching step; and, following the first etching step, a second etching step of etching the remainder of the third compound semiconductor layer with an etching gas containing F and Cl or F and Br, wherein the semiconductor lamination further comprises Second compound Between the conductor layer and the third compound semiconductor layer, formed on the second compound semiconductor layer, and the fifth compound semiconductor layer containing no Al in the composition,
The fifth compound semiconductor layer is formed on the fifth compound semiconductor layer.
A heterojunction field effect transistor, wherein the second etching step automatically stops at the surface of the sixth compound semiconductor layer. 3. The method of manufacturing a hetero-junction field effect transistor according to claim 2, wherein said first etching step is plasma etching, and is performed while monitoring a peak of plasma emission.