JPS5831582A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a preferable field effect transistor (FET) characteristics without deteriorating the characteristics of an active layer or the boundary between an active layer and a high resistance layer by forming the FET with an epitaxially grown GaAs single crystal by ion implanting a resistor and a capacitor. CONSTITUTION:The monolithic IC circuit of this embodiment is a negative feedback type amplifier using an FET, a GaAs single cyrstal is epitaxially grown with N type GaAs 2 on a semi-insulating substrate 1, and an N type GaAs is further continuously grown. An N type GaAs layer is mesa etched, thereby forming a mesa 3 for the FET and a mesa 42 for a feedback capacity. Then, an Si is implanted as an N type impurity in an N type buffer layer, is then annealed, thereby activating the implanted region 41 as a feedback resistor Rf. A reliable vapor epitaxial single crystal is used for the FET part required for high frequency characteristics, and the ion implantation and the merits can be utilized for the other passive circuit parts required for the reproducibility of the thickness of the active layer.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device in which a field effect transistor is formed of epitaxially grown GaAs single crystal, and a resistor and a capacitor are formed by ion implantation.

Field effect transistors using GaAs single crystals have excellent high frequency characteristics and are already in practical use. Integrated circuits based on field effect transistors using GaAs have also been actively developed. This is because GaAs allows the fabrication of semi-insulating single crystals, which is not possible with Si, which reduces parasitic capacitance and allows high-speed monolithic ICs to be fabricated.
This is because it can be manufactured.

Commercially available GaAs FETs generally have an n-type high resistance GaAs buffer layer formed with a thickness of 2 to 4 μm on a semi-insulating GaAs substrate, and a 0.8 to 2.0×
IO"Cm-3 n-type active layer formed with a thickness of 01 to 05 μm by vapor phase epitaxial single crystal growth method.
A structure as shown in FIG. 1 is formed on a single crystal layer. In the figure, l is a semi-insulating QaAs substrate, 2 digits n-
shaped buffer layer, 3 is the mesa which is the active layer, 4 is the source, 5
1 is a drain, 6 is a dirt electrode, and the thickness of mesa 3, which is an active layer, is controlled to a desired value using chemical etching.

In the case of GaAs IC, many elements are formed in this active layer, including not only field effect transistors but also passive circuit elements such as resistors and capacitors, so the controllability of the thickness of this active layer is This is an extremely important factor. However, GaAs vapor phase epitaxial single crystals inevitably have poor uniformity in thickness, which poses a problem. For this reason, the active layer is made of semi-insulating GaAs or n''''GaAs.
s LlCn type impurity Si, Se.

There are attempts to create S and other materials by ion implantation.

Although ion implantation provides extremely good controllability of the active layer thickness, it also has the following problems.

Generally, semi-insulating GaAs single crystals obtain semi-insulating properties by compensating for contamination by 81 during growth with Cr or CrO. In the case of ion implantation, 75
By annealing at a high temperature of 0 to 950'C, electrons are activated and high mobility is obtained. This deteriorates the characteristics of the interface between the layer and the high-resistance layer, making it difficult to obtain good FET characteristics. For this reason, various annealing methods or semi-insulating GaAs with low Cr concentration or no Cr are used.
Single crystal growth has been studied.

The purpose of the present invention is to solve such inconveniences,
An object of the present invention is to provide a GaAs monolithic semiconductor integrated circuit device.

That is, traditionally, implantation was performed in an n''' GaAs buffer layer grown on semi-insulating QaAs or semi-insulating GaAs, and all FETs and other passive circuit components were formed by implantation. In contrast, in the present invention, semi-insulating G
An n-GaAs buffer layer and an nGaAs layer are implanted into a GaAs single crystal that is continuously epitaxially grown on aAs, and this nGaAa epitaxial single crystal is used for the FET part. It is used only for the formation of etc. and is characterized by FIG. 2 is a diagram explaining the present invention in detail, in which (a) shows the case where the ion implantation region 11 of the n-GaAs t4 buffer layer is implanted, and (b) shows the case where the ion implantation region 12 of the n-GaAs layer is implanted. The following shows the case where the following is carried out.

This is based on the knowledge that high-temperature annealing of 750°C or higher is only necessary to form FETs that require high electron mobility, and that high mobility is not required for other circuit components. It is something.

In the present invention, (1) The thickness of this n-buffer layer is increased from the usual 3 to 4
It is formed to have a thickness of 5 to 10 .mu.m, which is thicker than .mu.m, to reduce the influence of Cr diffusion from the semi-insulating substrate during cyan annealing on the n epitaxial layer.

(2) Post-implantation annealing is performed at a low temperature of 750°C or less.
Alternatively, the diffusion of Cr can be reduced by performing the process at a high temperature for a short period of time.

(3) Adjust the Cr concentration of the semi-insulating substrate to 2 to 6 Wt p, p, which is used in normal vapor phase epitaxial growth.
, significantly lower than m 02-1.5 Wt p, p,
Let it be m.

The above three-line properties do not necessarily have to be satisfied, even if only one of them is used, by annealing after implantation,
It was experimentally confirmed that the nGaAs epitaxial layer does not undergo metamorphosis. The ions used for implantation are S+-S, Se for n-type impurities, and Zn*Cd, Mg, Mn, 13e for p-type impurities.
It is possible to use any element such as.

By performing implantation and annealing in this way, reliable vapor phase epitaxial single crystals can be used for FET parts that require high frequency characteristics, and other passive parts that require reproducibility of active layer thickness can be used. GaAs is used for circuit components by taking advantage of the advantages of ion implantation and two active layer formation methods.
It becomes possible to manufacture devices.

Next, we will discuss the GaAa monolithic ivy I, which was prototyped using the present invention.
Example C will be described.

The basic circuit configuration of the monolithic IC is shown in FIG. This circuit is a negative feedback amplifier using FETs, 31 is an FET, 32 is a feedback resistor Rf, and 33 is a capacitor Cf for stopping one DC current flowing through the feedback circuit. F
By optimally designing the gml of the ET 31 and the resistance of the feedback circuit, the input/output impedance can be designed to any value over a wide band. In this example, if the input/output impedance is 50Ω, 17m = 90 to 100
ms, R(=200~400Ω, C,=20pF
~50pF and input/output impedance 75Ω, gm=: 50 ms ~100m5°Rf=100
Using the present invention, a prototype of two rods with ~700 Ω, C, = 20 pF ~ 50 pF, as shown in FIG. 4, was fabricated.

GaA used at this time! The single crystal is made by epitaxially growing non-doped 7' n-GaAs to a thickness of 4 to 6 μm on a semi-insulating substrate with a Cr concentration of 1.5 Wt, p, p, m or less, and then growing it to a thickness of 1 to 2.5×. 10crrL
This is a result of continuous growth of nGaAs. First, this nGaAs layer is mesa-etched up to the n'''GaAa layer to form mesa 3 for FET and mesa 42 for feedback capacitance Cf.

Thereafter, Si was added as an n-type impurity in the 2777 layer of the n''buffer at a dose of !'m-2 and 150 keV.
After implantation at an acceleration voltage of , activation is performed by annealing at 700° C. for 30 minutes. As a result, the injection area 4
1 is activated to a concentration of 2 to 3 x 10"cm-3. Thereafter, ohmic electrodes 4, 5 are formed by a conventional process.
, a dirt Schottky electrode 6, an insulating film 8, a wiring lead 7, and a Schottky electrode 43 for feedback capacitance are formed. This injection region 41 corresponds to the feedback resistor R7.

As described above, by using the present invention, the feedback resistance R
The controllability of the resistance value of f can be improved.

As a result, the distribution of high frequency characteristics of this monolink IC can be reduced.

In the above explanation, the implantation was made into the n-buffer layer, but it may also be implanted into nGaAs as shown in FIG. 2(0).

In this case, it is possible to form a resistor with a low specific resistance,
Also, implantation can be performed before mesa formation.

In the above-described embodiment, the implanted n-layer was used to form the resistor, but by selectively implanting it also into the GaAg layer for the feedback capacitor 42, the capacitor can be formed in a much smaller area.

As described above, the present invention has extremely great practical value.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of a conventional field effect transistor using a GaAs single crystal substrate, and FIG. 2 is a sectional view of a GaAs monolithic IC for explaining the principle of the semiconductor integrated circuit of the present invention. FIG. 3 is a diagram of an amplifier circuit using a monolink IC, and FIG. 4 is a sectional view showing an embodiment of a semiconductor integrated circuit according to the present invention. ■... Semi-insulating QaAs substrate, 2... n'''' type pass layer, 3... active layer, 4... source electrode, 5...
Drain electrode, 6... Dirt electrode, 7... Wiring lead, 8... Insulating film, 11.12... Ion implantation region, 31... FET, 32... Feedback resistor, 33. 4
2...Capacitance inserted in return, 41...Injection region,
43... Schottky electrode for feedback capacitance.

Claims (1)

[Claims] In a semiconductor integrated circuit device formed on a semi-insulating GaAs substrate and including at least a field effect transistor, the field effect transistor activates a GaA1 single crystal layer epitaxially grown on the semi-insulating substrate via a buffer layer. Passive circuit components other than the field effect transistor are formed as a layer, and passive circuit components other than the field effect transistor are formed as a layer of the buffer layer or the Ga layer.
A semiconductor integrated circuit device characterized in that it is formed in an As single crystal layer by ion implantation.