CA1315018C - P-type buffer layers for integrated circuits - Google Patents

Abstract

P-TYPE BUFFER LAYERS FOR INTEGRATED CIRCUITS

Abstract of the Disclosure An integrated circuit having an epitaxial GaAs buffer layer containing p-type dopant is disclosed.
The epitaxial p-doped buffer has a lower point defect/impurity density than bulk, melt-grown GaAs buffer layers and a lower carrier mobility than comparable n-doped buffer layers, and forms p-n junctions with n-doped regions of transistors resident on the buffer layer. The buffer sub-stantially reduces interdevice and intradevice parasitic currents as well as sidegating and back-gating. Furthermore, the p-doped epitaxial buffer enhances device isolation.

Description

``` 131~

P-TYPE BUFFER LAYERS FOR INTEGRATED CIRCUITS

DescriPtion Background of the Invention The effective manufacturing of gallium arsenide 05 ~Ga~s) integrated circuits is currently limited by the relative poor quality of bulk melt-grown GaAs wa~ers and also the limited ~ize of commercially available wafers. Epitaxial GaAs deposited on eit~er melt-grown Ga~ substrates or silicon (Si) 10 substrates offers improved material propertles for IC fabricatlon and operatlon. Addltionally, the use of epitaxial Ga~s on Si wafers offers larger area wafers, improved mechanical and thermal properties, and higher uniformity of the GaAs electronic 15 properties. However, epitaxial GaAs does not have the semi-insulating qualities of bulk-grown wafers prepared using appropriate processes.
Conventional GaAs integrated circult technology makes use of the semi-insulating properties of GaAs ; 20 wafers prepared by an appropriate bulk crystal growth technique. The resulting wafer typically have a resistivity above 107 ohm-cm. The properties of these crystals are derived as a consequence of the formation of defects and imperfections that 25 result in electrically active sltes being created ln the crystal. These states only form in sufficient qualltities to have useful effects under the elevated temperatures assoclated with bulk crystal growth from the melt. However, growth of GaAs by such 30 processes places the material under tremendous , .

~31~

stress due to its poor thermal conductivity, thereby generating a high density of non-uniformly dis-tributed dislocations. Additionally, other defects similar to those which glve the GaA~ itB semi-05 insulating properties also form under the melt-growth proce~s condltions and these have a detrimental effect on device and IC performance.
Such defects are associated with device noise and sidegating phenomena.
10- Thus, a need exists for a method for production of Ga~s integrated circuit~ having low semiconductor defect den~ity and semiconductor properties which reduce device nol~e and sidegatingO Ths ~ame need applied to IC's fabricated in other III-V ~aterlal 15 such as InP and related compounds. For discussion purposes, reference i~ made only to GaA~.

Summary of the Invention The invention pertains to an integrated circuit having an improved buffer layer. More speclfically, 20 the invention pertains to an integrated circuit having an epitaxial, p-doped GaAB buffer layer.
Unlike bulk melt-grown GaAs buffer wafers which contain defect6 that cause para~ltlc currents, sidegating and backgating, epitaxial GaAs layers are 25 substantially free of defects. When doped with p-type dopant material, the buffer forms p-n junc-tions with n-doped regions of devices subsequently deposited on the buffer. These p-n ~unctions create a depletion region having vlrtually no mobile charge 30 carrier5. When this effect ig coupled with the inherent limited carrier mobility of the essentially 1315~1~

defect-free buffer, a buffer layer having very low parasitic currents and excellent ds~ice lsolation is formed. In GaAs, n-channel devices are generally preferred because of tha large electron mobillty and 05 poor hole mobility. Therefore, p-type ~olation is very effective for n-type devices.

Brief DescriPtion of the Drawinqs Figure 1 i8 a sche~atic representation of an integrated circuit having two surface-deposited 10 transistors and a conductor llne on a bulk melt-grown GaAs wafer.
Figure 2 i~ a schematic repre~entation of an integrated circuit having two surfacQ-depo~ited transistors and a conductor line on an ep~taxial, 15 p-doped Ga~s buffer layer.

Detailed DescriPtion of the Invention The use of GaAs and other III-V material buffers containing p-type dopants in metal semi-conductor field effect transistor (MESFET) inte-20 grated circuits (ICs) provides a semi-in~ulating layer in the IC which serves to reduce leakage currents, as well as sidegating and backgating effects while s~multaneously providing improved device isolation. On MESFET ICs having epitaxial 25 Ga~s on Si, the isolation and reduced leakage benefits provided by p-type GaAs buffer layers is even more important because the silicon substrate is highly conductive relative to the semi-insulating GaAs. Si wafer resistivities are usually below 104 30 ohm-cm.

"` 1315~:~$

A section of a conventional GaAs MESFET IC is schematically represented in Figure 1. Generally represented 10, the IC contains a first transistor 20, a second transistor 30 and a conductor line 40 05 on the surface of a melt grown on Si wafer 44. The wafer 44 generally comprises GaAs.
Transistor 20 comprises an n-doped source 22, a metallic gate 24, and an n-doped drain 26. Like-wise, transistor 30 comprises an n-doped source 32, lO a metallic gate 34 and an n-doped drain 36.
The Ga~s wafer 44 has a resistance of about 107 o2lms~cm or higher. Thu~, wh~le the wafer 44 provides slgnificant insulation propertles, it does not entirely elimlnate parasitic leakage currents.
15 SUch leakage currents include an isolation related interdevice shunting current II 50~ an intradevice leakage current IL 52, and a sidegating current ISG
5~, which exists between a transistor channel region 38 and the conductor line 40. The semi-insulating 20 properties of the melt grown wafer 44 and parasitic currents 50, 52 and 54 result from defects within the GaAs wafer material. These typically add noise and exhibit an increased ISG 54 at a high operation frequencies. These qualities prevent optimum device 25 and circuit operation. Such traps also have detri-mental effects on the frequency response of devices and circuits.
The defects in melt grown GaAs wafers can be largely eliminated by epitaxial deposition of GaAs 30 buffer layer. However, the prevention of defects tllat give rise to the para~ltic currents also prevents the occurrence of the ~emi-insulating ` 1315~1~

resistances of the buffer. If the GaA~ bu~fer has n-type conductivity, the n-regions used to form the MESFET source and drain regions will have ohmic-like electrical continuity with the buffer, resulting 05 essentially in mutual contact among all of the devices on the IC. Additionally, epitaxial n-type buffer layers have resistances o~ only about lol to ohm/cm. Thus relatlvely large values of II, IL
and ISG will be present.
If, on the other hand the buffer layer contains p-type doping material ln the epltaxlal layer, the result is greatly improved. A p-doped epitaxial Ga~s buffer layer exh~bits the vlrtually defect-free and much hlgher chemical purity advant~ge~ o~
15 epitaxially deposited materlals ln combination with a reduction in parasitic currents. Thi~ result may be seen in p-doped epitaxial GaAs which has a resistivity of about 30 times that of comparable n-doped material. This effect i8 due to the funda-20 mentally lower carrier mobility of the p-doped material.
Furthermore, when a p-doped buffer layer is used, p-n junctions form between the p-type buffer regions and the n-type transistor regions. The p-n 25 junction has associated with it a depletion region which is devoid of charge carriers and thus exhibits a very high resistance. This depletion region is semi-insulating in nature.
The low carrier mobility and the depletion 30 region together combine to provide improved device isolation, lowered leakage currents and reduced sidegating effects. Additionally, the absence of . ~

131~0~

certain defects (such as traps) ~n the p-doped buffer layer further reduces sidegating effects.
Finally, the p-type buffer layer can be ~iased with respect to the active device region~, thereby 05 enhancing these effectq.
A device having a p-type buffer layer ls represented schematically in Figure 2. As in Figure 1, the MESFET IC is generally represented loo and contains a first transistor 20 comprising a source 10 22, a gate 24 and a drain 26 and a sQcond transistor 30 comprising a source 32, a gate 34 and a drain 36.
As shown previously, a conductor llne 40 iB al80 present. This difference, however, lles in the bufEer layer 60. The buffer 60 is an epitaxial, 15 p-doped GaAs layer which, as previously described, exhibits a number of advantages. The n-doped sources 22 and 32 and the n-doped drains 26 and 36 form p-n ~unctions with the ad~acent p-doped buffer layer 60. As stated previously, the p-n ~unctions 20 create a depletion region 62 which serves to effec-tively isolate each transistor 2~, 30 from both the wafer 44 and from each other. ~he re~ulting MESFET
ICs exhibit low device noise and very low side-gating.
It should be pointed out that the invention is not lntended to be limited to GaAs layers, but rather applies to III-V materials ln general. Such materials are combinations of materials from group IIIA of the perlodic table (for example Ga, In, Al) 30 and materials from group VA of the periodic table (for example A~ and P). Representative III-V
materials include GaAs, GaInAs, GaAlAs and InP.
' - ' ' ' `- 131~

Doping of the buffer layer can be carried out by a variety of methods, however, ion implantation and organometallic chemical vapor deposition (OMCVD) are preferred. A variety of p-type dopant~ are 05 available, but C, Be and Zn are preferred. Doping with C durin~ OMCVD using trimethyl gallium (TMG~
can be achieved with appropriate ad~ustment of the process conditions. For the OMCVD process, the typical buffer layer will be 1 to 5 um thick and be 10 doped in the range of 1ol3 to 1O16 cm 3. For ~on implantation, the required doping may be ad~usted with respect to the implanted layer thicknes~. ~he use of p-type buffer layers is particularly relevant for ICs fabricated in epltaxial GaAs on 51 wafers 15 and for ICs fabricated with advanced heterostructure device structures making use of epitaxial GaA~ and AlGaAs layers on either GaAs or Si substrates.
These heterostructure devices include modulation-doped field effect transistors (high electron 20 mobillty transistors and selectively doped hetero-structure transistors). These structures are formed using epitaxial GaAs and, therefore, the semi-il~sulatin~ wafer properties are not available for isolation, as in the case of MESFET ICs formed in 25 epitaxial Ga~s or GaAs wafers. The p-buffer isola-tion improves the performance of these ICs, as discussed above.

Equivalents Those skilled in the art will recognize, or be 30 able to ascertain using no more than routine experi-131~

mentation, many equivalents to the ~pecific embodi-ments described herein. Such equivalant~ are int~nded to be encompassed in the following claims.

Claims (12)

1. In a MESFET integrated circuit having a plurality of fabricated n-type doped semiconductor devices, the improvement which comprises providing a buffer layer comprising p-type epitaxial GaAs material doped with carbon and formed over a silicon substrate such that p-n junctions are formed between the n-type devices and the p-type epitaxial GaAs with a depletion region at each junction.

2. The MESFET integrated circuit of Claim 1, wherein the buffer layer is doped during a chemical vapor deposition of the epitaxial GaAs material and further compresses a heterostructure.

3. The MESFET integrated circuit of Claim 1, wherein the p-doped buffer layer is fabricated using carbon doping from organometallic group III sources during an organometallic chemical vapor deposition process, the buffer layer having a thickness in a range from 1 micron to 5 microns and having a dopant concentration in a range from 1013/cm3 to 1016/cm3.

4. A metal semiconductor field effect transistor deposited upon a buffer layer, comprising:
an epitaxial III-V semiconductor layer which is p-doped with a vapor constituent during an organometallic chemical vapor deposition process of the III-V semiconductor layer on a silicon substrate to form a buffer layer; and a plurality of n-doped regions formed adjacent the buffer layer such that p-n junctions having depletion regions are created at the interface of the regions and the buffer layer, the n-doped regions forming the source and drain regions of the transistor.

5. The metal semiconductor field effect transistor of Claim 4, wherein the buffer layer comprises p-doped epitaxial GaAs.

6. The metal semiconductor field effect transistor of Claim 4, wherein the buffer layer is subjected to a bias voltage.

7. The metal semiconductor field effect transistor of Claim 5, wherein the epitaxial GaAs is doped with a dopant selected from the group consisting of C, Be and Zn.

8. A method of making an integrated circuit, comprising the steps of:
a) forming a silicon substrate;
b) depositing a III-V semiconductor material on a surface over the silicon substrate using an organometallic chemical vapor deposition process in which the III-V semiconductor is doped with carbon during the deposition such that a p-type buffer layer is formed in the III-V material; and c) doping selected regions of the III-V
material with a n-type dopant to form n-type regions of an integrated circuit wherein depletion regions are formed around the n-type regions.

9. The method of Claim 8, wherein the III-V
material comprises gallium arsenide.

10. The method of Claim 9, wherein the integrated circuit comprises a transistor.

11. The method of Claim 8, further comprising forming a heterostructure within the integrated circuit.

12. The method of Claim 11, wherein the heterostructure comprises GaAs and GaAlAs.