JPH0439775B2 - - Google Patents
Info
- Publication number
- JPH0439775B2 JPH0439775B2 JP59180361A JP18036184A JPH0439775B2 JP H0439775 B2 JPH0439775 B2 JP H0439775B2 JP 59180361 A JP59180361 A JP 59180361A JP 18036184 A JP18036184 A JP 18036184A JP H0439775 B2 JPH0439775 B2 JP H0439775B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductivity type
- channel
- supply layer
- carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 29
- 230000000295 complement effect Effects 0.000 claims description 14
- 238000009792 diffusion process Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 15
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 8
- 230000012010 growth Effects 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 125000005842 heteroatom Chemical group 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004047 hole gas Substances 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000779 depleting effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Bipolar Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、高電子移動度トランジスタと高正孔
移動度トランジスタとで構成される相補型半導体
装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a complementary semiconductor device comprising a high electron mobility transistor and a high hole mobility transistor.
本発明者は、さきに、高電子移動度トランジス
タと高正孔移動度トランジスタとを組み合わせて
構成した相補型半導体装置を提供した（要すれ
ば、特願昭57−30004号：特開昭58−147167号公
報を参照）。
The present inventor has previously provided a complementary semiconductor device constructed by combining a high electron mobility transistor and a high hole mobility transistor (in short, Japanese Patent Application No. 57-30004: JP-A-58 -Refer to Publication No. 147167).
第３図は既提供の相補型半導体装置の要部切断
側面図である。 FIG. 3 is a cutaway side view of essential parts of a previously provided complementary semiconductor device.
図に於いて、１は半絶縁性GaAs基板、２はノ
ン・ドープGaAsバツフア層、３はノン・ドープ
GaAsチヤネル層、４は素子間分離用溝、５はシ
リコン（Si）等のｎ型不純物を含有するAlGaAs
電子供給層、６は亜鉛（Zn）等のｐ型不純物を
含有するAlGaAs正孔供給層、７はｎ型GaAs補
助層、７′はｐ型GaAs補助層、８は２次元電子
ガス層、９は２次元正孔ガス層、１０は高電子移
動度トランジスタ（ｎチヤネル側）の制御電極、
１１は高正孔移動度トランジスタ（ｐチヤネル
側）の制御電極、１２はｎチヤネルの入力電極、
１４はｐチヤネル側の入力電極、１３はｎチヤネ
ル側の出力電極、１５はｐチヤネル側の出力電
極、TINは入力端子、Tprは出力端子をそれぞれ示
している。 In the figure, 1 is a semi-insulating GaAs substrate, 2 is a non-doped GaAs buffer layer, and 3 is a non-doped
GaAs channel layer, 4 is a groove for isolation between elements, 5 is AlGaAs containing n-type impurities such as silicon (Si)
An electron supply layer, 6 is an AlGaAs hole supply layer containing p-type impurities such as zinc (Zn), 7 is an n-type GaAs auxiliary layer, 7' is a p-type GaAs auxiliary layer, 8 is a two-dimensional electron gas layer, 9 is a two-dimensional hole gas layer, 10 is a control electrode of a high electron mobility transistor (n-channel side),
11 is the control electrode of the high hole mobility transistor (p channel side), 12 is the input electrode of the n channel,
14 is an input electrode on the p-channel side, 13 is an output electrode on the n-channel side, 15 is an output electrode on the p-channel side, T IN is an input terminal, and T pr is an output terminal.
図示の構成から明らかなように、ｎチヤネル側
トランジスタにはｎ型AlGaAs電子供給層５を用
い、また、ｐチヤネル側トランジスタにはｐ型
AlGaAs正孔供給層６を用いている。 As is clear from the illustrated configuration, the n-type AlGaAs electron supply layer 5 is used for the n-channel side transistor, and the p-type AlGaAs electron supply layer 5 is used for the p-channel side transistor.
An AlGaAs hole supply layer 6 is used.
前記従来技術に依ると、ｎ型AlGaAs電子供給
層５及びｐ型AlGaAs正孔供給層６を形成するの
に２回の成長工程を必要としている。
According to the prior art, two growth steps are required to form the n-type AlGaAs electron supply layer 5 and the p-type AlGaAs hole supply layer 6.
従つて、工程が複雑化すると共に選択成長で２
回目に成長される側の結晶の界面に於ける結晶性
が悪くなる旨の欠点がある。 Therefore, as the process becomes more complex, selective growth
There is a drawback that the crystallinity at the interface of the crystal on the side that is grown the second time becomes poor.
本発明は、１回のAlGaAs層の成長で相補型半
導体装置の製造を可能とし、前記の欠点を解消す
るものである。 The present invention eliminates the above-mentioned drawbacks by making it possible to manufacture a complementary semiconductor device by growing an AlGaAs layer once.
本発明者は、第３図に関して説明した相補型半
導体装置に於いて、例えば、ｐチヤネル側トラン
ジスタ、即ち、高正孔移動度トランジスタの構造
として第１図に見られるものを作製し、高正孔移
動度トランジスタとして正常に動作することを確
認した。
In the complementary semiconductor device explained with reference to FIG. 3, the present inventor fabricated the structure shown in FIG. It was confirmed that it operates normally as a hole mobility transistor.
第１図は本発明に依る相補型半導体装置に於け
る高正孔移動度トランジスタ側の要部切断側面図
を表している。 FIG. 1 is a cross-sectional side view of a main part of a high hole mobility transistor side in a complementary semiconductor device according to the present invention.
図に於いて、２１は半絶縁性GaAs基板、２２
はノン・ドープGaAsバツフア層、２３はノン・
ドープGaAsチヤネル層、２５はｎ型AlxGa1-xAs
電子供給層（一導電型キヤリヤ供給層）、３１は
高正孔移動度トランジスタ（ｐチヤネル側）の制
御電極、３４はｐチヤネル側の入力電極、３５は
ｐチヤネル側の出力電極、３６及び３７はｐ型不
純物拡散領域（反対導電型キヤリヤ拡散領域）で
あるソース領域及びドレイン領域をそれぞれ示し
ている。 In the figure, 21 is a semi-insulating GaAs substrate, 22
is a non-doped GaAs buffer layer, and 23 is a non-doped GaAs buffer layer.
Doped GaAs channel layer, 25 is n-type Al x G a1-x As
Electron supply layer (carrier supply layer of one conductivity type), 31 is a control electrode of a high hole mobility transistor (p channel side), 34 is an input electrode on the p channel side, 35 is an output electrode on the p channel side, 36 and 37 1A and 1B respectively indicate a source region and a drain region, which are p-type impurity diffusion regions (carrier diffusion regions of opposite conductivity type).
図示の半導体装置に於けるｎ型AlxGa1-xAs電
子供給層２５のドナー濃度と厚さは熱平衡状態に
てヘテロ界面に電子の蓄積がないような程度、即
ち、ノーマリ・オフとなるように選択される。ま
た、制御電極３１は、ｎ型AlxGa1-xAs電子供給
層２５を熱平衡状態において空乏化させる機能を
有するものであり、シヨツトキ金属、ｐ型半導
体、絶縁物／金属など、目的に応じて選択すれば
良い。 In the illustrated semiconductor device, the donor concentration and thickness of the n-type Al x G a1-x As electron supply layer 25 are such that no electrons are accumulated at the hetero interface in a thermal equilibrium state, that is, it is normally off. selected as follows. The control electrode 31 has a function of depleting the n-type Al x G a1-x As electron supply layer 25 in a thermal equilibrium state, and may be made of a Schottky metal, a p-type semiconductor, an insulator/metal, etc. depending on the purpose. All you have to do is choose.
さて、前記半導体装置に於いて、ソース領域と
して動作するｐ型不純物拡散領域３６に加わる電
圧に対して負の電圧を制御電極３１に印加すると
ノン・ドープGaAsチヤネル層２３のヘテロ界面
側表面ポテンシヤルが低下し、その結果、ｐ型ソ
ース領域３６から正孔が流れ込んでｐチヤネルが
生成されてノーマリ・オフ・モード動作が可能と
なる。尚、この場合、高電子移動度トランジス
タ、即ち、ｎチヤネル側トランジスタの構成及び
動作は第３図について説明した相補型半導体装置
に於けるそれと全く変わりない。 Now, in the semiconductor device, when a negative voltage is applied to the control electrode 31 with respect to the voltage applied to the p-type impurity diffusion region 36 that operates as a source region, the surface potential of the non-doped GaAs channel layer 23 on the hetero interface side changes. As a result, holes flow from the p-type source region 36 to generate a p-channel, allowing normally off mode operation. In this case, the structure and operation of the high electron mobility transistor, that is, the n-channel side transistor, are completely the same as those in the complementary semiconductor device explained with reference to FIG.
そこで、本発明の相補型半導体装置では、半
絶縁性結晶基板上に形成されたノン・ドープ半導
体チヤネル層と、該チヤネル層上に形成され該チ
ヤネル層より小さいキヤリヤ親和力を有してヘテ
ロ接合を形成する一導電型キヤリヤ供給層と、該
一導電性キヤリヤ供給層上に形成された制御電極
と、該制御電極を挟んで前記一導電型キヤリヤ供
給層上に形成された入力電極及び出力電極とを有
しヘテロ界面に一導電型キヤリヤを誘起して動作
するノーマリ・オフ・モードの一導電型チヤネ
ル・トランジスタ、前記一導電型キヤリヤ供給
層上に形成された制御電極を挟んで対向し且つ該
一導電型キヤリヤ供給層表面から前記ノン・ドー
プ半導体チヤネル層内に達する反対導電型キヤリ
ヤ拡散領域と、該反対導電型キヤリヤ拡散領域上
にそれぞれ別個に対応させて形成された入力電極
及び出力電極とを有しヘテロ界面に反対導電型キ
ヤリヤを誘起して動作するノーマリ・オフ・モー
ドの反対導電型チヤネル・トランジスタ、の前記
及びの２種類のトランジスタからなり、その
２種類のトランジスタに於ける制御電極を相互に
接続して出力端子とし、同じく入力電極を電源接
続電極としている。 Therefore, in the complementary semiconductor device of the present invention, a non-doped semiconductor channel layer formed on a semi-insulating crystal substrate and a heterojunction formed on the channel layer and having a carrier affinity smaller than that of the channel layer are formed. A carrier supply layer of one conductivity type to be formed, a control electrode formed on the carrier supply layer of one conductivity type, and an input electrode and an output electrode formed on the carrier supply layer of one conductivity type with the control electrode in between. a normally-off mode one-conductivity type channel transistor that operates by inducing a one-conductivity type carrier at the hetero interface; a carrier diffusion region of an opposite conductivity type extending from the surface of the carrier supply layer of one conductivity type into the non-doped semiconductor channel layer; an input electrode and an output electrode formed separately and correspondingly on the carrier diffusion region of the opposite conductivity type; A normally-off mode opposite conductivity type channel transistor which operates by inducing carriers of opposite conductivity type at the hetero-interface. are connected to each other to form an output terminal, and the input electrode is also used as a power supply connection electrode.
前記のような構成を採ると、ノン・ドープ半導
体チヤネル層上に形成され該チヤネル層より小さ
いキヤリヤ親和力を有してヘテロ接合を生成する
一導電型キヤリヤ供給層は、一導電型チヤネル・
トランジスタ及び反対導電型チヤネル・トランジ
スタの両者に共通とすることができる。
When the above configuration is adopted, the carrier supply layer of one conductivity type, which is formed on the non-doped semiconductor channel layer and has a carrier affinity smaller than that of the channel layer to form a heterojunction, is a carrier supply layer of one conductivity type that is formed on the non-doped semiconductor channel layer.
It can be common to both transistors and opposite conductivity type channel transistors.
従つて、キヤリヤ供給層は１回の成長工程で完
成させることが可能であるから、第３図に関して
説明した従来技術に依る相補型半導体装置のよう
に、選択成長で２回目に成長させるキヤリヤ供給
層の結晶性が悪くなる旨の欠点は完全に解消され
る。 Therefore, since the carrier supply layer can be completed in one growth step, the carrier supply layer is grown in a second time by selective growth, as in the complementary semiconductor device according to the prior art described with reference to FIG. The disadvantage of poor crystallinity of the layer is completely eliminated.
第２図は本発明一実施例の要部切断面図を表
し、第１図に関して説明した部分と同部分は同記
号で指示してある。
FIG. 2 shows a cross-sectional view of essential parts of an embodiment of the present invention, and the same parts as those explained in connection with FIG. 1 are indicated by the same symbols.
図に於いて、２４は素子間分離用溝、２８は２
次元電子ガス層、３０は高電子移動度トランジス
タ（ｎチヤネル側）の制御電極、３２はｎチヤネ
ル側の入力電極、３３はｎチヤネル側の出力電極
をそれぞれ示している。 In the figure, 24 is a groove for isolation between elements, 28 is 2
30 is a control electrode of a high electron mobility transistor (on the n-channel side), 32 is an input electrode on the n-channel side, and 33 is an output electrode on the n-channel side.
図から判るように、本実施例では、ｎチヤネル
側トランジスタに於けるｎ型AlxGa1-xAs電子供
給層２５をそのままｐチヤネル側トランジスタに
も用いているので、従来技術に於けるように、２
回の成長を行う必要はない。 As can be seen from the figure, in this embodiment, the n-type Al x G a1-x As electron supply layer 25 in the n-channel transistor is also used as it is in the p-channel transistor, so it is different from the conventional technology. To, 2
There is no need to perform multiple growths.
本発明の相補型半導体装置では、ｐチヤネル側
トランジスタの構造が第３図に見られる従来例と
相違しているので、それを製造する場合の要点に
ついて説明する。 In the complementary semiconductor device of the present invention, the structure of the p-channel side transistor is different from that of the conventional example shown in FIG. 3, so the main points in manufacturing it will be explained.
(1) 制御電極３１は、例えばチタン（Ti）／タ
ングステン(W)、Ｗ／シリコン（Si）等の高融点
金属で作製する。(1) The control electrode 31 is made of a high melting point metal such as titanium (Ti)/tungsten (W) or W/silicon (Si).
(2) ｎチヤネル側トランジスタの部分にフオト・
レジストなどで保護膜を形成し、制御電極３１
をマスクとして、例えばベリリウム（Be）な
どのｐ型ドーパントをイオン注入し、その後、
アニールを行つてｐ型ソース領域３６及びｐ型
ドレイン領域３７を形成する。(2) Add a photo to the n-channel side transistor part.
A protective film is formed using resist or the like, and the control electrode 31
Using this as a mask, a p-type dopant such as beryllium (Be) is ion-implanted, and then,
Annealing is performed to form a p-type source region 36 and a p-type drain region 37.
この場合の条件は次の通りである。 The conditions in this case are as follows.
イオン注入
注入形式：保護膜スルー注入
ドーパント：Be
加速エネルギ：175〔KeV〕
保護膜：窒化アルミニウム（AlN）
ドーズ量：１×1019〔cm-2〕
アニール
アニール形式：ランプ・アニール
温度：950〔℃〕
時間：10〔秒〕
(3) ｎチヤネル側のオーミツク電極、即ち、入力
電極３２及び出力電極３３は金（Au）・ゲルマ
ニウム（Ge）／Auで形成し、温度45〔℃〕で
時間２（分）の合金化アニールを行つた。 Ion implantation type: Through protective film implantation Dopant: Be Acceleration energy: 175 [KeV] Protective film: Aluminum nitride (AlN) Dose: 1×10 19 [cm -2 ] Annealing Annealing type: Lamp annealing temperature: 950 [ °C] Time: 10 [seconds] (3) The ohmic electrodes on the n-channel side, that is, the input electrode 32 and the output electrode 33, are made of gold (Au), germanium (Ge)/Au, and are heated at a temperature of 45 [°C] for a period of time. Alloying annealing was performed for 2 minutes.
また、ｐチヤネル側のオーミツク電極、即ち、
入力電極３４及び出力電極３５はAu・亜鉛
（Zn）／Auで形成し、ｎチヤネル側と同じ条件
で合金化アニールを行つた。 In addition, the ohmic electrode on the p-channel side, that is,
The input electrode 34 and the output electrode 35 were formed of Au/zinc (Zn)/Au, and were alloyed and annealed under the same conditions as the n-channel side.
前記説明した実施例では、ノン・ドープGaAs
チヤネル層２３上に成長させた半導体層はｎ型
AlxGa1-xAs電子供給層２５であるが、これをｐ
型AlxGa1-xAsに変えて正孔供給層とし、ヘテロ
界面のノン・ドープGaAsチヤネル層２３側に２
次元正孔ガス層を生成させてｐチヤネル側トラン
ジスタを構成し、ｎチヤネル側トランジスタには
不純物拡散に依りｎ型ソース領域及びｎ型ドレイ
ン領域を形成するようにしても良い。 In the embodiment described above, non-doped GaAs
The semiconductor layer grown on the channel layer 23 is of n-type.
The Al x G a1-x As electron supply layer 25 is
The type Al x G a1-x As was replaced with a hole supply layer, and 2
A p-channel transistor may be formed by generating a dimensional hole gas layer, and an n-type source region and an n-type drain region may be formed in an n-channel transistor by impurity diffusion.
本発明の相補型半導体装置では、電子供給層或
いは正孔供給層として用いられる半導体層をｎチ
ヤネル側とｐチヤネル側とで共通に用い、その半
導体層の導電型の如何に依りｎチヤネル側或いは
ｐチヤネル側に該半導体層と反対導電型の領域を
形成し、そこからヘテロ界面近接のチヤネル層に
正孔或いは電子を供給してチヤネルを生成させて
相補型半導体装置の一方のトランジスタとして動
作させるようにしている。
In the complementary semiconductor device of the present invention, a semiconductor layer used as an electron supply layer or a hole supply layer is used in common on the n-channel side and the p-channel side, and depending on the conductivity type of the semiconductor layer, the semiconductor layer is used on the n-channel side or the p-channel side. A region of the opposite conductivity type to the semiconductor layer is formed on the p-channel side, and holes or electrons are supplied from there to the channel layer near the hetero interface to generate a channel and operate as one transistor of a complementary semiconductor device. That's what I do.
従つて、電子供給層或いは正孔供給層として用
いられる前記半導体層は１回の成長で形成され、
その結果、従来、電子供給層と正孔供給層と２回
に分けて成長させる場合のような結晶性の不良は
解消され、簡単な製造工程で高速且つ低消費電力
の相補型半導体装置が得られる。 Therefore, the semiconductor layer used as an electron supply layer or a hole supply layer is formed by one growth,
As a result, the crystallinity defects that conventionally occur when the electron supply layer and hole supply layer are grown in two steps are eliminated, and a complementary semiconductor device with high speed and low power consumption can be obtained with a simple manufacturing process. It will be done.
第１図及び第２図は本発明一実施例の要部切断
側面図、第３図は従来例の要部切断側面図をそれ
ぞれ表している。
図に於いて、２１は半絶縁性GaAs基板、２２
はノン・ドープGaAsバツフア層、２３はノン・
ドープGaAsチヤネル層、２４は素子間分離用
溝、２５はｎ型AlxGa1-xAs電子供給層、２８は
２次元電子ガス層、３０は高電子移動度トランジ
スタ（ｎチヤネル側）の制御電極、３１は高正孔
移動度トランジスタ（ｐチヤネル側）の制御電
極、３２はｎチヤネル側の入力電極、３３はｎチ
ヤネル側の出力電極、３４はｐチヤネル側の入力
電極、３５はｐチヤネル側の出力電極、３６及び
３７はｐ型不純物拡散領域であるソース領域及び
ドレイン領域をそれぞれ示している。
1 and 2 are cross-sectional side views of essential parts of an embodiment of the present invention, and FIG. 3 is a cross-sectional side view of essential parts of a conventional example. In the figure, 21 is a semi-insulating GaAs substrate, 22
is a non-doped GaAs buffer layer, and 23 is a non-doped GaAs buffer layer.
Doped GaAs channel layer, 24 is groove for isolation between elements, 25 is n-type Al x G a1-x As electron supply layer, 28 is two-dimensional electron gas layer, 30 is control of high electron mobility transistor (n channel side) Electrodes, 31 is the control electrode of the high hole mobility transistor (p channel side), 32 is the input electrode on the n channel side, 33 is the output electrode on the n channel side, 34 is the input electrode on the p channel side, 35 is the p channel side The output electrodes 36 and 37 on the side respectively indicate a source region and a drain region which are p-type impurity diffusion regions.
Claims (1)
プ半導体チヤネル層と、該チヤネル層上に形成さ
れ該チヤネル層より小さいキヤリヤ親和力を有し
てヘテロ接合を形成する一導電型キヤリヤ供給層
と、該一導電型キヤリヤ供給層上に形成された制
御電極と、該制御電極を挟んで前記一導電型キヤ
リヤ供給層上に形成された入力電極及び出力電極
とを有するノーマリ・オフ・モードの一導電型チ
ヤネル・トランジスタ、 ２ 前記一導電型キヤリヤ供給層上に形成された
制御電極を挟んで対向し且つ該一導電型キヤリヤ
供給層表面から前記ノン・ドープ半導体チヤネル
層内に達する反対導電型キヤリヤ拡散領域と、該
反対導電型キヤリヤ拡散領域上にそれぞれ別個に
対応させて形成された入力電極及び出力電極とを
有するノーマリ・オフ・モードの反対導電型チヤ
ネル・トランジスタ、 の２種類のトランジスタからなり、該２種類のト
ランジスタに於ける制御電極を相互に接続して入
力端子、同じく出力電極を相互に接続して出力端
子、同じく入力電極を電源接続電極としてなるこ
とを特徴とする相補型半導体装置。[Claims] 1. A non-doped semiconductor channel layer formed on a semi-insulating crystal substrate, and a conductive layer formed on the channel layer and having a carrier affinity smaller than that of the channel layer to form a heterojunction. A normal type carrier supply layer comprising a carrier supply layer of one conductivity type, a control electrode formed on the carrier supply layer of one conductivity type, and an input electrode and an output electrode formed on the carrier supply layer of one conductivity type with the control electrode in between. a channel transistor of one conductivity type in an off mode, 2 facing across a control electrode formed on the carrier supply layer of one conductivity type and extending from the surface of the carrier supply layer of one conductivity type into the non-doped semiconductor channel layer; 2. A normally-off mode opposite conductivity type channel transistor having an opposite conductivity type carrier diffusion region, and an input electrode and an output electrode formed separately and correspondingly on the opposite conductivity type carrier diffusion region. The control electrodes of the two types of transistors are connected to each other to form an input terminal, the output electrodes of the two types of transistors are connected to each other to form an output terminal, and the input electrode is used as a power supply connection electrode. Complementary semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59180361A JPS6159875A (en) | 1984-08-31 | 1984-08-31 | Complementary semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59180361A JPS6159875A (en) | 1984-08-31 | 1984-08-31 | Complementary semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6159875A JPS6159875A (en) | 1986-03-27 |
| JPH0439775B2 true JPH0439775B2 (en) | 1992-06-30 |
Family
ID=16081899
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59180361A Granted JPS6159875A (en) | 1984-08-31 | 1984-08-31 | Complementary semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6159875A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2549795B2 (en) * | 1992-03-17 | 1996-10-30 | 株式会社東芝 | Compound semiconductor integrated circuit and manufacturing method thereof |
| US7119381B2 (en) * | 2004-07-30 | 2006-10-10 | Freescale Semiconductor, Inc. | Complementary metal-oxide-semiconductor field effect transistor structure having ion implant in only one of the complementary devices |
-
1984
- 1984-08-31 JP JP59180361A patent/JPS6159875A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6159875A (en) | 1986-03-27 |
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