JP2679333B2 - Schottky barrier junction gate type field effect transistor - Google Patents

Schottky barrier junction gate type field effect transistor

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Publication number
JP2679333B2
JP2679333B2 JP2045068A JP4506890A JP2679333B2 JP 2679333 B2 JP2679333 B2 JP 2679333B2 JP 2045068 A JP2045068 A JP 2045068A JP 4506890 A JP4506890 A JP 4506890A JP 2679333 B2 JP2679333 B2 JP 2679333B2
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JP
Japan
Prior art keywords
crystal layer
layer
carrier concentration
type
gaas
Prior art date
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Expired - Fee Related
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JP2045068A
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Japanese (ja)
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JPH03248436A (en
Inventor
史明 片野
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NEC Corp
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NEC Corp
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Priority to JP2045068A priority Critical patent/JP2679333B2/en
Priority to US07/660,897 priority patent/US5087950A/en
Publication of JPH03248436A publication Critical patent/JPH03248436A/en
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Publication of JP2679333B2 publication Critical patent/JP2679333B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863—Lateral single gate transistors
    • H01L29/66878—Processes wherein the final gate is made before the formation, e.g. activation anneal, of the source and drain regions in the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明はショットキー障壁接合ゲート型電界効果トラ
ンジスタに関し、特に、その寄生抵抗および寄生容量の
低減に関する。TECHNICAL FIELD The present invention relates to a Schottky barrier junction gate type field effect transistor, and more particularly to reduction of its parasitic resistance and parasitic capacitance.

［従来の技術］ ショットキー障壁接合ゲート型電界効果トランジスタ
（以下、MESFETと称する）のうち、特にｎ型のガリウム
・ヒ素（以下、GaAsと記す）結晶層を動作層として用い
たGaAs MESFETは高周波デバイスとして優れた特性を有
し、高周波増幅素子に代表されるものが開発されて商品
化がなされている。[Prior Art] Among Schottky barrier junction gate type field effect transistors (hereinafter referred to as MESFETs), GaAs MESFETs using an n-type gallium arsenide (hereinafter referred to as GaAs) crystal layer as an operating layer are high frequency A device having excellent characteristics as a device and represented by a high frequency amplification element has been developed and commercialized.

第２図は従来のこの種のGaAs MESFETの要部を示す断
面図である。FIG. 2 is a sectional view showing a main part of a conventional GaAs MESFET of this type.

第２図において、11は半絶縁性GaAs基板であり、この
上に各結晶層12,35,36,37が順にエピタキシャル成長で
形成されている。12は厚さ0.5μｍのアンドープGaAs
層、35は厚さ530Å、キャリア濃度５×1017cm-3のｎ型G
aAs層、36は厚さ1000Å、キャリア密度３×1016cm-3n型
GaAs層、37は厚さ600Å、キャリア密度１×1018cm-3の
高濃度ｎ型GaAs層である。また、38はゲート電極、39は
ソース電極、40はドレイン電極であり、ゲート電極30は
高濃度ｎ型GaAs層37を堀込んでｎ型GaAs層36上に設けら
れている。In FIG. 2, 11 is a semi-insulating GaAs substrate, on which crystal layers 12, 35, 36, 37 are sequentially formed by epitaxial growth. 12 is 0.5 μm thick undoped GaAs
Layer, 35 is n-type G with thickness 530Å and carrier concentration 5 × 10 17 cm -3
aAs layer, 36 is 1000 Å, carrier density is 3 × 10 16 cm -3 n type
The GaAs layer 37 is a high-concentration n-type GaAs layer having a thickness of 600Å and a carrier density of 1 × 10 18 cm -3 . 38 is a gate electrode, 39 is a source electrode, and 40 is a drain electrode. The gate electrode 30 is provided on the n-type GaAs layer 36 by engraving the high-concentration n-type GaAs layer 37.

このような構造のGaAs MESFETは、ゲート電極下のｎ
型GaAs層が低キャリア濃度の層36と高キャリア濃度の層
37の２層構造になっているので相互コンダクタンスが大
きく且つゲートバイアス依存性が小さく、更に、ゲート
電極が低キャリア濃度の層36上にあるのでゲート耐圧が
大きく、ゲート電極とｎ型GaAsの間に形成されるショッ
トキー障壁接合の持つ容量が小さいという利点を持って
いる。The GaAs MESFET with such a structure has n under the gate electrode.
-Type GaAs layer has a low carrier concentration layer 36 and a high carrier concentration layer
The two-layered structure of 37 has a large mutual conductance and a small gate bias dependency. Furthermore, since the gate electrode is on the layer 36 having a low carrier concentration, the gate breakdown voltage is large, and between the gate electrode and the n-type GaAs. It has the advantage that the Schottky barrier junction formed in 1 has a small capacitance.

また、ゲート電極領域とソースおよびドレイン電極領
域の間の領域のGaAs層には高濃度ｎ型GaAs層37が設けら
れており、寄生抵抗の低減が図られている。Further, a high-concentration n-type GaAs layer 37 is provided in the GaAs layer in the region between the gate electrode region and the source and drain electrode regions to reduce the parasitic resistance.

［発明が解決しようとする課題］ しかしながら、上述した従来のGaAs MESFETでは、オ
ーミック電極であるソース電極39,ドレイン電極40が動
作層であるｎ型GaAs層35に直接つながっておらずに低濃
度のｎ型GaAs36層を介しているため、寄生抵抗の低減が
充分でないという問題があった。また、ゲート電極38が
高濃度ｎ型GaAs層37に近接しているため、寄生容量が大
きいという問題があった。[Problems to be Solved by the Invention] However, in the above-described conventional GaAs MESFET, the source electrode 39 and the drain electrode 40, which are ohmic electrodes, are not directly connected to the n-type GaAs layer 35, which is an operating layer. Since the n-type GaAs36 layer is provided, there is a problem that the parasitic resistance is not sufficiently reduced. Further, since the gate electrode 38 is close to the high concentration n-type GaAs layer 37, there is a problem that the parasitic capacitance is large.

また、ゲート電極38を設けるのに高濃度GaAs層37を堀
込む工程が必要となるため、この工程での作業バラツキ
により、MESFETの特性が安定しないという問題点もあっ
た。Further, since the step of digging the high-concentration GaAs layer 37 is required to provide the gate electrode 38, there is a problem that the characteristics of the MESFET are not stable due to the work variation in this step.

［課題を解決するための手段］ 本発明のショットキー障壁接合ゲート型電界効果トラ
ンジスタ（MESFET）は、半絶縁性ガリウム・ヒ素基板上
にアンドーブのガリウム・ヒ素結晶層を含めて形成され
たバッファ層と、バッファ層上に形成された第１キャリ
ア濃度の第1n型ガリウム・ヒ素結晶層と、第1n型ガリウ
ム・ヒ素結晶上に形成された第１キャリア濃度より低い
第２キャリア濃度の第2n型ガリウム・ヒ素結晶層と、第
2n型ガリウム・ヒ素結晶層上にショットキー障壁金属を
用いて設けられたゲート電極と、ゲート電極の両側に設
けられた一対のオーミック電極とを有するショットキー
障壁接合ゲート型電界効果トランジスタであって、一対
のオーミック電極下に第１キャリア濃度より高い第３キ
ャリア濃度の第3n型ガリウム・ヒ素結晶層を設け、第3n
型ガリウム・ヒ素結晶層と第1n型ガリウム・ヒ素結晶層
および第2n型ガリウム・ヒ素結晶層との間に、キャリア
濃度が第１キャリア濃度以上で且つ層厚が第1n型ガリウ
ム・ヒ素結晶層と第2n型ガリウム・ヒ素結晶層との和に
等しい第4n型ガリウム・ヒ素結晶層を設けたことを特徴
とする。[Means for Solving the Problem] A Schottky barrier junction gate type field effect transistor (MESFET) of the present invention is a buffer layer formed on a semi-insulating gallium arsenide substrate including an Andove gallium arsenide crystal layer. And a first n-type gallium arsenide crystal layer having a first carrier concentration formed on the buffer layer, and a second n-type second carrier concentration having a second carrier concentration lower than the first carrier concentration formed on the first n-type gallium arsenide crystal Gallium arsenide crystal layer,
A Schottky barrier junction gate type field effect transistor having a gate electrode provided by using a Schottky barrier metal on a 2n type gallium arsenide crystal layer and a pair of ohmic electrodes provided on both sides of the gate electrode. , A third n-type gallium arsenide crystal layer having a third carrier concentration higher than the first carrier concentration is provided under the pair of ohmic electrodes, and
Type gallium / arsenic crystal layer and the first n-type gallium / arsenic crystal layer and the second n-type gallium / arsenic crystal layer having a carrier concentration equal to or higher than the first carrier concentration and a layer thickness of the first n-type gallium / arsenic crystal layer And a fourth n-type gallium-arsenic crystal layer equal to the sum of the second n-type gallium-arsenic crystal layer.

［実施例］ 次に本発明について図面を参照して説明する。Example Next, the present invention will be described with reference to the drawings.

第１図は本発明の一実施例に係るGaAsMESFETの断面図
である。第１図において、11は半絶縁性GaAs基板、12は
厚さ１μｍのアンドープGaAs結晶層、13は厚さ2000Åの
アンドープAlGaAs結晶層、14は厚さ500ÅのアンドーブG
aAs結晶層であり、これら結晶層12〜14がバッファ層を
形成している。結晶層15は厚さ730Å、キャリア濃度３
×1017cm-3のｎ型GaAs結晶層であり、結晶層14上に形成
されている。結晶層16は厚さ600Å、キャリア濃度５×1
016cm-3のｎ型GaAs結晶層であり、結晶層15上に形成さ
れている。FIG. 1 is a sectional view of a GaAs MESFET according to an embodiment of the present invention. In FIG. 1, 11 is a semi-insulating GaAs substrate, 12 is an undoped GaAs crystal layer having a thickness of 1 μm, 13 is an undoped AlGaAs crystal layer having a thickness of 2000 Å, and 14 is an Andove G having a thickness of 500 Å.
It is an aAs crystal layer, and these crystal layers 12 to 14 form a buffer layer. Crystal layer 15 has a thickness of 730Å and carrier concentration of 3
It is an n-type GaAs crystal layer of × 10 17 cm -3 and is formed on the crystal layer 14. Crystal layer 16 has a thickness of 600Å and carrier concentration of 5 × 1
It is an n-type GaAs crystal layer of 16 cm −3 and is formed on the crystal layer 15.

尚、結晶層12〜16はMBE法あるいはMOVPE法により順次
エピタキシャル成長された結晶層である。The crystal layers 12 to 16 are crystal layers sequentially epitaxially grown by the MBE method or the MOVPE method.

結晶層17は元々結晶層15および16として形成された層
の一部から形成され、結晶層17の層厚は結晶層15と16と
の和に等しくなっている。すなわち、結晶層17の上層部
分は、ｎ型GaAs結晶層16として形成された層の一部にシ
リコンを、加速エネルギー50keVで２×1012個/cm2イオ
ン注入した後、電気的に活性化して形成したＮ型GaAs結
晶層であり、その平均的キャリア濃度は結晶層17の下層
部分を成すｎ型GaAs結晶層15と同等となっている。結晶
層18は、元々GaAs結晶層14,15,16として形成された層の
一部に、シリコンを加速エネルギー100kevで２×1013個
/cm2イオン注入した後、活性化して形成した高濃度ｎ型
GaAs結晶層であり、その平均的キャリア濃度は１×1018
cm-3である。The crystal layer 17 is formed from a part of the layers originally formed as the crystal layers 15 and 16, and the layer thickness of the crystal layer 17 is equal to the sum of the crystal layers 15 and 16. That is, the upper portion of the crystal layer 17 is electrically activated after implanting 2 × 10 12 ions / cm 2 of silicon at an acceleration energy of 50 keV into a part of the layer formed as the n-type GaAs crystal layer 16. The N-type GaAs crystal layer 15 is formed as described above, and its average carrier concentration is equal to that of the n-type GaAs crystal layer 15 forming the lower part of the crystal layer 17. The crystal layer 18 is a layer originally formed as the GaAs crystal layers 14, 15 and 16 and contains 2 × 10 13 silicon with acceleration energy of 100 kev.
/ cm 2 Ion implantation followed by activation to form high concentration n-type
GaAs crystal layer with an average carrier concentration of 1 × 10 18
cm -3 .

また、結晶層16上に設けられた電極19はｎ型GaAs結晶
層16とショットキー障壁と成す金属（例えば、タングス
テンシリサイド）で形成されている。電極19上の電極20
はゲート抵抗を小さくするための低抵抗金属（例えばチ
タン，白金，金の積構造の金属）で形成されており、こ
れら電極19と20でゲート長0.3μｍのゲート電極が構成
されている。ゲート電極の両側の高濃度ｎ型GaAs結晶層
18上に設けられた電極21,22は高濃度ｎ型GaAs結晶層18
とオーミック接合を形成する金属（例えば金とゲルマニ
ウムの合金とニッケルをアロイしたもの）で形成されて
おり、電極21がソース電極、電極22がドレイン電極であ
る。The electrode 19 provided on the crystal layer 16 is formed of the n-type GaAs crystal layer 16 and a metal (for example, tungsten silicide) that forms a Schottky barrier. Electrode 20 on electrode 19
Is formed of a low resistance metal (for example, a metal having a laminated structure of titanium, platinum and gold) for reducing the gate resistance, and these electrodes 19 and 20 form a gate electrode having a gate length of 0.3 μm. High concentration n-type GaAs crystal layer on both sides of the gate electrode
Electrodes 21 and 22 provided on 18 are high-concentration n-type GaAs crystal layer 18
Is formed of a metal that forms an ohmic junction (for example, alloy of gold and germanium alloy and nickel), the electrode 21 is a source electrode, and the electrode 22 is a drain electrode.

すなわち、本実施例のGaAsMESFETは、半絶縁性GaAs基
板11上にアンドープGaAs結晶層を含めて構成したバッフ
ァ層12〜14を形成し、このバッファ層上に中程度のキャ
リア濃度（３×1017cm-3）のｎ型GaAs結晶層15を形成
し、このｎ型GaAs結晶層15上に低いキャリア濃度（５×
1016cm-3）のｎ型GaAs結晶層16を形成し、このｎ型GaAs
結晶層16上にショットキー障壁金属を用いてゲート電極
19を設け、ゲート電極両側に一対のオーミック電極21,2
2を設け、オーミック電極21,22下に高いキャリア濃度
（１×1018cm-3）のｎ型GaAs結晶層18を形成し、ｎ型Ga
As結晶層18とｎ型GaAs結晶層15およびｎ型GaAs結晶層16
との間に、キャリア濃度がｎ型GaAs結晶層15と等しく且
つ層厚がｎ型GaAs結晶層15とｎ型GaAs結晶層16との和に
等しいｎ型GaAs結晶層17を形成した構造となっている。That is, in the GaAs MESFET of this embodiment, buffer layers 12 to 14 including an undoped GaAs crystal layer are formed on a semi-insulating GaAs substrate 11, and a medium carrier concentration (3 × 10 17) is formed on this buffer layer. cm −3 ) n-type GaAs crystal layer 15 is formed, and a low carrier concentration (5 ×
An n-type GaAs crystal layer 16 of 10 16 cm -3 ) is formed, and this n-type GaAs is formed.
Gate electrode using Schottky barrier metal on crystalline layer 16
19 is provided, and a pair of ohmic electrodes 21 and 2 are provided on both sides of the gate electrode.
2 is provided, an n-type GaAs crystal layer 18 having a high carrier concentration (1 × 10 18 cm −3 ) is formed under the ohmic electrodes 21 and 22, and n-type Ga is formed.
As crystal layer 18, n-type GaAs crystal layer 15 and n-type GaAs crystal layer 16
An n-type GaAs crystal layer 17 having a carrier concentration equal to that of the n-type GaAs crystal layer 15 and a layer thickness equal to the sum of the n-type GaAs crystal layer 15 and the n-type GaAs crystal layer 16. ing.

このような構造のGaAs MESFETは、オーミック電極21,
22が高濃度ｎ型GaAs結晶層18を介して動作層15とつなが
っており、また、ゲート電極領域と高濃度ｎ型GaAs結晶
層18の間の領域のGaAs結晶層17もキャリア濃度が高めら
れているため寄生抵抗が低減され、ソース抵抗として0.
7Ω・mmが得られた。また、ゲート電極19がキャリア濃
度が５×1016cm-3と低濃度のGaAs結晶層16上にあるた
め、ゲート・ドレイン間耐圧が19Vと大きく、第２図に
示した従来例のように高濃度ｎ型GaAs結晶層がゲート電
極に近接していないので寄生容量が低減された。The GaAs MESFET having such a structure has an ohmic electrode 21,
22 is connected to the operating layer 15 through the high-concentration n-type GaAs crystal layer 18, and the carrier concentration of the GaAs crystal layer 17 in the region between the gate electrode region and the high-concentration n-type GaAs crystal layer 18 is also increased. Therefore, the parasitic resistance is reduced and the source resistance is 0.
7 Ω · mm was obtained. Further, since the gate electrode 19 is on the GaAs crystal layer 16 having a low carrier concentration of 5 × 10 16 cm −3 , the gate-drain breakdown voltage is as large as 19 V, which is similar to the conventional example shown in FIG. Since the high-concentration n-type GaAs crystal layer is not close to the gate electrode, the parasitic capacitance is reduced.

尚、本実施例ではドレイン側の高濃度Ｎ型GaAs結晶層
18とゲート電極19との間隔t1（0.6μｍ）を、ソース側
の高濃度ｎ型GaAs結晶層18とゲート電極19との間隔t2
（0.3μｍ）より大きくしており、ゲート・ドレイン間
耐圧の向上、寄生容量の低減に寄与させている。本構造
のパワーFETとしての特性は、ゲート幅840μｍ測定周波
数18GH8で1dB圧縮点出力24.8dBm、線形利得8.4dBが得ら
れた。また、本構造ではゲート電極下と他の領域のGaAs
結晶層の結晶学的厚さが等しく、ゲート電極下の領域の
GaAs結晶層を堀込む必要がないので、工程上のバラツキ
要因が少なくなり、歩留まりも向上した。In this embodiment, the high-concentration N-type GaAs crystal layer on the drain side is used.
The distance t1 (0.6 μm) between the gate electrode 19 and 18 is the distance t2 between the high-concentration n-type GaAs crystal layer 18 on the source side and the gate electrode 19.
(0.3 μm), which contributes to improvement of gate-drain breakdown voltage and reduction of parasitic capacitance. Regarding the characteristics of this structure as a power FET, at a gate width of 840 μm, a measurement frequency of 18GH8, a 1 dB compression point output of 24.8 dBm and a linear gain of 8.4 dB were obtained. In this structure, GaAs under the gate electrode and other regions
The crystallographic thickness of the crystal layers is equal and
Since it is not necessary to dig the GaAs crystal layer, the factor of process variation is reduced and the yield is improved.

尚、本実施例ではバッファ層としてオンドープGaAs結
晶層12とアンドープAlGaAs結晶層13とアンドープGaAs結
晶層14の三層構造の層を用いた。これは、アンドープAl
GaAs結晶層により、基板側を流れる電流を抑え相互コン
ダクタンスの下づまりを小さくしたものである。同様の
効果はアンドープAlGaAs結晶層に限らず、Ｐ型GaAs結晶
層あるいは、Ｐ型AlGaAs結晶層、あるいはGaAs層とAlGa
As層を用いた超格子層を用いても得られる。In this embodiment, a three-layer structure of an on-doped GaAs crystal layer 12, an undoped AlGaAs crystal layer 13 and an undoped GaAs crystal layer 14 is used as the buffer layer. This is undoped Al
The GaAs crystal layer suppresses the current that flows on the substrate side, and reduces the underconductance of the mutual conductance. The same effect is not limited to the undoped AlGaAs crystal layer, but is also applicable to the P-type GaAs crystal layer, the P-type AlGaAs crystal layer, or the GaAs layer and AlGa.
It can also be obtained by using a superlattice layer using the As layer.

但し、製造上これらの結晶層を用いることができない
場合は、バッファ層をアンドーブGaAs結晶層のみで形成
してもよい。However, if these crystal layers cannot be used in manufacturing, the buffer layer may be formed of only the Andove GaAs crystal layer.

また、本発明はゲート電極領域と高濃度ｎ型GaAs結晶
層18の間の領域のGaAs結晶層17のキャリア濃度をｎ型Ga
As結晶層15のキャリア濃度より大きく且つ高濃度ｎ型Ga
As結晶層18のキャリア濃度より小さくしてもよい。例え
ば、上記実施例の条件下で、GaAs結晶層17のキャリア濃
度を６×1017cm-3にした場合、上記の実施例より寄生抵
抗が低減され、ソース抵抗として0.6Ω・mmが得られ
た。尚、この構造は上記の実施例において、結晶層17を
形成するために実施したイオン注入を、例えば加速エネ
ルギー80keVと加速エネルギー50keVとして元々は結晶層
16,15として形成された部分に二重注入とすることによ
り得られる。Further, according to the present invention, the carrier concentration of the GaAs crystal layer 17 in the region between the gate electrode region and the high concentration n-type GaAs crystal layer 18 is set to n-type Ga.
Higher than the carrier concentration of As crystal layer 15 and high concentration n-type Ga
It may be lower than the carrier concentration of the As crystal layer 18. For example, when the carrier concentration of the GaAs crystal layer 17 is set to 6 × 10 17 cm -3 under the conditions of the above embodiment, the parasitic resistance is reduced and the source resistance of 0.6 Ω · mm is obtained as compared with the above embodiment. It was In addition, this structure is obtained by using the ion implantation performed to form the crystal layer 17 in the above embodiment, for example, with an acceleration energy of 80 keV and an acceleration energy of 50 keV.
It can be obtained by double injection into the portions formed as 16,15.

［発明の効果］ 以上説明したように、本発明のGaAs MESFETは、ゲー
ト電極を低濃度のｎ型GaAs結晶層上に形成し、また、ソ
ースおよびドレイン電極を、低濃度のｎ型GaAs結晶層を
介さずに、高濃度ｎ型GaAs結晶層を介して動作層である
ｎ型GaAs結晶層と電気的に接続し、また、ゲート電極領
域と高濃度ｎ型GaAs結晶層の間の領域のGaAs結晶層も低
抵抗化されているため、寄生抵抗が小さく、また、高濃
度ｎ型GaAs結晶層がゲート電極に近接していないので寄
生容量が小さいという効果を有する。また、ゲート電極
下の領域の結晶層を堀込む必要がなくなるため、工程上
のバラツキを防止して、歩留まり良く特性の安定したGa
As MESFETを得ることができる。[Effects of the Invention] As described above, in the GaAs MESFET of the present invention, the gate electrode is formed on the n-type GaAs crystal layer of low concentration, and the source and drain electrodes are formed on the n-type GaAs crystal layer of low concentration. Via the high-concentration n-type GaAs crystal layer, and is electrically connected to the n-type GaAs crystal layer which is the operating layer, and the GaAs in the region between the gate electrode region and the high-concentration n-type GaAs crystal layer. Since the crystal layer is also made low in resistance, the parasitic resistance is small, and since the high-concentration n-type GaAs crystal layer is not close to the gate electrode, the parasitic capacitance is small. In addition, since it is not necessary to dig the crystal layer in the region under the gate electrode, variations in the process can be prevented, and Ga with stable yield and stable characteristics can be obtained.
You can get As MESFET.

【図面の簡単な説明】[Brief description of the drawings]

第１図は本発明の一実施例に係るGaAs MESFETの断面
図、第２図は従来例に係るGaAs MESFETの断面図であ
る。 11……半絶縁性GaAs基板、 12……アンドープGaAs結晶層、 13……アンドープAlGaAs層、 14……アンドープGaAs層、 15……キャリア濃度が中程度のｎ型GaAs結晶層、 16……キャリア濃度が低いｎ型GaAs結晶層、 17……ｎ型GaAs結晶層、 18……キャリア濃度が高いｎ型GaAs結晶層、 19,20……ゲート電極、 21……ソース電極、 22……ドレイン電極。FIG. 1 is a sectional view of a GaAs MESFET according to an embodiment of the present invention, and FIG. 2 is a sectional view of a GaAs MESFET according to a conventional example. 11 ... Semi-insulating GaAs substrate, 12 ... Undoped GaAs crystal layer, 13 ... Undoped AlGaAs layer, 14 ... Undoped GaAs layer, 15 ... N-type GaAs crystal layer with medium carrier concentration, 16 ... Carrier N-type GaAs crystal layer with low concentration, 17 ... n-type GaAs crystal layer, 18 ... n-type GaAs crystal layer with high carrier concentration, 19,20 ... gate electrode, 21 ... source electrode, 22 ... drain electrode .

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】半絶縁性ガリウム・ヒ素基板上にアンドー
プのガリウム・ヒ素結晶層を含めて形成されたバッファ
層と、バッファ層上に形成された第１キャリア濃度の第
1n型ガリウム・ヒ素結晶層と、第1n型ガリウム・ヒ素結
晶上に形成された第１キャリア濃度より低い第２キャリ
ア濃度の第2n型ガリウム・ヒ素結晶層と、第2n型ガリウ
ム・ヒ素結晶層上にショットキー障壁金属を用いて設け
られたゲート電極と、ゲート電極の両側に設けられた一
対のオーミック電極とを有するショットキー障壁接合ゲ
ート型電界効果トランジスタであって、一対のオーミッ
ク電極下に第１キャリア濃度より高い第３キャリア濃度
の第3n型ガリウム・ヒ素結晶層を設け、第3n型ガリウム
・ヒ素結晶層と第1n型ガリウム・ヒ素結晶層および第2n
型ガリウム・ヒ素結晶層との間に、キャリア濃度が第１
キャリア濃度以上で且つ層厚が第1n型ガリウム・ヒ素結
晶層と第2n型ガリウム・ヒ素結晶層との和に等しい第4n
型ガリウム・ヒ素結晶層を設けたことを特徴とするショ
ットキー障壁接合ゲート型電界効果トランジスタ。1. A buffer layer formed by including an undoped gallium arsenide crystal layer on a semi-insulating gallium arsenide substrate, and a first carrier concentration first layer formed on the buffer layer.
1n-type gallium-arsenic crystal layer, second n-type gallium-arsenic crystal layer having a second carrier concentration lower than the first carrier concentration formed on the first n-type gallium-arsenic crystal, and second n-type gallium-arsenic crystal layer A Schottky barrier junction gate type field effect transistor having a gate electrode provided above using a Schottky barrier metal and a pair of ohmic electrodes provided on both sides of the gate electrode, wherein the Schottky barrier junction gate type field effect transistor is provided below the pair of ohmic electrodes. A third n-type gallium-arsenic crystal layer having a third carrier concentration higher than the first carrier concentration is provided, and the third-n-type gallium-arsenic crystal layer, the first-n-type gallium-arsenic crystal layer, and the second-n
The first carrier concentration is between the n-type gallium arsenide crystal layer
The fourth n having a carrier concentration or more and a layer thickness equal to the sum of the first n-type gallium-arsenic crystal layer and the second n-type gallium-arsenic crystal layer
Schottky barrier junction gate type field effect transistor characterized in that a gallium arsenide crystal layer is provided. 【請求項２】前記第4n型ガリウム・ヒ素結晶層のキャリ
ア濃度が第１キャリア濃度と略同一である特許請求の範
囲第１項記載のショットキー障壁接合ゲート型電界効果
トランジスタ。2. The Schottky barrier junction gate type field effect transistor according to claim 1, wherein the carrier concentration of the fourth n-type gallium arsenide crystal layer is substantially the same as the first carrier concentration.
JP2045068A 1990-02-26 1990-02-26 Schottky barrier junction gate type field effect transistor Expired - Fee Related JP2679333B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2045068A JP2679333B2 (en) 1990-02-26 1990-02-26 Schottky barrier junction gate type field effect transistor
US07/660,897 US5087950A (en) 1990-02-26 1991-02-26 Schottky barrier junction gate field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2045068A JP2679333B2 (en) 1990-02-26 1990-02-26 Schottky barrier junction gate type field effect transistor

Publications (2)

Publication Number Publication Date
JPH03248436A JPH03248436A (en) 1991-11-06
JP2679333B2 true JP2679333B2 (en) 1997-11-19

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Country Link
US (1) US5087950A (en)
JP (1) JP2679333B2 (en)

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* Cited by examiner, † Cited by third party
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JPH0653241A (en) * 1992-08-03 1994-02-25 Nec Corp Manufacture of field effect transistor
US5364816A (en) * 1993-01-29 1994-11-15 The United States Of America As Represented By The Secretary Of The Navy Fabrication method for III-V heterostructure field-effect transistors
JP2674495B2 (en) * 1993-12-27 1997-11-12 日本電気株式会社 Semiconductor device
KR100211070B1 (en) * 1994-08-19 1999-07-15 아끼구사 나오유끼 Semiconductor device and manufacturing method thereof
US6150680A (en) * 1998-03-05 2000-11-21 Welch Allyn, Inc. Field effect semiconductor device having dipole barrier
JP3705431B2 (en) * 2002-03-28 2005-10-12 ユーディナデバイス株式会社 Semiconductor device and manufacturing method thereof
US8174048B2 (en) * 2004-01-23 2012-05-08 International Rectifier Corporation III-nitride current control device and method of manufacture
EP1641029A1 (en) * 2004-09-27 2006-03-29 STMicroelectronics S.r.l. Process for manufacturing a Schottky contact on a semiconductor substrate
US7553704B2 (en) * 2005-06-28 2009-06-30 Freescale Semiconductor, Inc. Antifuse element and method of manufacture
US9818857B2 (en) 2009-08-04 2017-11-14 Gan Systems Inc. Fault tolerant design for large area nitride semiconductor devices
EP2465141B1 (en) * 2009-08-04 2021-04-07 GaN Systems Inc. Gallium nitride microwave and power switching transistors with matrix layout
US9029866B2 (en) * 2009-08-04 2015-05-12 Gan Systems Inc. Gallium nitride power devices using island topography
US8791508B2 (en) 2010-04-13 2014-07-29 Gan Systems Inc. High density gallium nitride devices using island topology

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US4393578A (en) * 1980-01-02 1983-07-19 General Electric Company Method of making silicon-on-sapphire FET
USH368H (en) * 1980-09-16 1987-11-03 The United States Of America As Represented By The Secretary Of The Navy Field-effect transistor
US4636822A (en) * 1984-08-27 1987-01-13 International Business Machines Corporation GaAs short channel lightly doped drain MESFET structure and fabrication
JPH0831484B2 (en) * 1986-10-16 1996-03-27 株式会社日立製作所 Method for manufacturing field effect transistor
JPS63182866A (en) * 1987-01-26 1988-07-28 Hitachi Ltd Semiconductor device

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JPH03248436A (en) 1991-11-06
US5087950A (en) 1992-02-11

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