KR970004485B1 - Hetero-junction field effect transistor - Google Patents

Abstract

No summary.

Description

Semiconductor device and manufacturing method

1 is a block diagram of a conventional HEMT.

2 is a block diagram of a conventional pulse-doped MESFET.

3 is a characteristic diagram of this embodiment and a conventional example.

4A and 4B show the energy band chart of the HEMT, FIG. 4A shows the energy band chart when the gate voltage VGS is 0, and FIG. 4B shows the gate voltage VGS. Energy band chart when ^& gt ^; 0 and a part of the two-dimensional electron gas is transferred to n ⁺ AlGaAs layer 230.

5 is a configuration diagram of the first embodiment.

6A to 6C are manufacturing process diagrams of the first embodiment.

7 is a configuration diagram of the second embodiment.

8A and 8B are structural diagrams of the energy band of the HEMT of the present invention. In FIG. 8A, when the gas voltage VGS = 0, FIG. 8B shows the gas voltage VGS>. Energy band structure diagram when 0.

9 (A) to 9 (C) are manufacturing process diagrams of the HEMT of the planar structure of one embodiment of the present invention.

10 is a graph showing the dependence on (gm) gate bias in an AlGaAs / GaAs-based HEMT, a pulsed-doped MESFET, and the HEMT of the present invention.

11A to 11C are manufacturing process diagrams of the HEMT of the planar structure of the third embodiment.

* Description of the symbols for the main parts of the drawings *

110: substrate, 120: buffer layer,

(130a) (130b): undoped GaInAs layer, (140): GaAs layer,

(142): n-type GaAs layer, 220: undoped AlGaAs spacer layer,

(340): gate nation, (350a) (350b): n ⁺ ion implantation layer,

(360): source nation, (370): drain nation

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and in particular to heterojunction deployment effect transistors (FETs) that operate at low noise and high speed, and to monolithic integrated circuits (MMICs) for microwaves using the FETs.

As a transistor operating at high speed, a heterojunction field effect transistor (or high electron mobility transistor (HEMT)) using a selectively doped (selected dope) heterojunction has been proposed. The structure of the mobility transistor is shown, which will be described below.

An undoped GaAs layer 210 is formed on the semi-insulating GaAs substrate 110, and an AlGaAs layer (undoped AlGaAs spacer layer) 22 having a lower electron affinity than the GaAs is formed on the GaAs layer 210. It is. The AlGaAs layer is composed of an undoped AlGaAs spacer layer 220 and an AlGaAs layer 230 doped with n-type dopants (elements such as Si and Se), which are formed on the AlGaAs layer 210. The gate station 250 is formed on the AlGaAs layer, and the source station 270 and the drain station 280 are formed on the Si-GAaAs layer 260 by sandwiching the gate station 250 therebetween. This national structure is called a recessed structure because the entire gate is formed at the bottom of the groove (recess), and in HEMT, it is a general gate national structure. With this structure, the two-dimensional electron gas 240 is formed on the GaAs side on the AlGaAs / GaAs interface, which serves as a drain-source channel (current path). Thus, the concentration of the two-dimensional electron gas 240 is controlled by the gate station 250, and the current between the source station 270 and the drain station 280 is modulated.

On the other hand, as a transistor having a structure other than HEMT and operating at a low noise and at high speed, a pulsed MESFET is reported in the Institute of Electronics and Information Sciences study document ED89-152. The pulse-doped MESFET uses a GaAs layer with Si pulse-dope as a channel, and has a structure shown in FIG. 2, which will be described below.

On the semi-insulating GaAs substrate 110, an undoped GaAs buffer layer 310 having a carrier type P-type (carrier density: ˜5 × 10 ¹⁵ cm 3) is formed and a Si-doped GaAs channel layer (˜4 × 10 ¹⁸⁾ cm- ³ ) 320 is formed to a thickness of 100 mm ³ . On the Si-doped GaAs channel layer 320, an undoped GaAs cap layer 330 is formed in which the conductivity type of the carrier is n-type (˜1 × 10 ¹⁵ cm ⁻³ ). Since the impurity distribution profile is low in the GaAs buffer layer 310 and the GaAs cap layer 330, and high in the shape of a pulse in the Si-doped GaAs layer 320, this structure is called a pulse-doped structure. The gate station 340, the n ⁺ ion implantation layers 350a and 350b, the source station 360, and the drain station 370 formed in this manner on the pulsed dope structure are self-aligned with respect to the gate station 340. Formed. This national structure is called a planar structure because the gate nation is flat.

3 shows an example of the characteristics of AlGaAs / GaAs-based HEMTs and pulse-doped MESFETs, showing the gate bias dependence of the transfer conductance (gm) when an element having a gate length of 0.3 µm is used. Pulsed-doped MESFETs have mesapropyl (dotted line) of the transfer conductance (gm) with respect to the gate bias, and if the bias point is slightly displaced, the change in transfer conductance (gm) is small, but the value of the transfer conductance (gm) is higher than that of HEMT. little. In addition, the sharpness of the rising edge of the transfer conductance gm in the gate bias near the threshold Vth, which is important as a low noise device, is inferior to that of the HEMT.

On the other hand, HEMT shows a sharp rise in the transfer conductance (gm) and its peak value is high, but has a peak-shaped profile (single dashed line) with respect to the gate bias. Therefore, when the bias point is slightly displaced, the transfer conductance (gm) is greatly reduced. The decrease in the gate bias of the transfer conductance (gm) of the HEMT is caused by a phenomenon called "real space transition" in which a part of two-dimensional electrons are transferred to an AlGaAs layer having a low electron velocity. .

4 is an energy band chart along the line XX of the HEMT shown in FIG. 1, where Ec represents the bottom of the conduction band and Ef represents the Fermi level. As shown in FIG. 4A, a portion of the two-dimensional electron gas generated at the interface of the undoped GaAs layer 210 raises the gate voltage VGS to the + side. As shown in FIG. 9, the n ⁺ AlGaAs layer 230 is transferred. As a result, the electron mobility decreases as a whole and rapidly falls from the peak value at (gm).

The peak profile of the transfer conductance gm causes a problem that the design margin is low and the yield of the integrated circuit IC is lowered when the integrated circuit is manufactured using the HEMT. In the HEMT structure, since the sharpness of the AlGaAs / GaAs interface is important, a planar gate station by self-aligned ion implantation is not employed. That is, it is necessary to anneal at high temperature in order to activate ion implanted Si, and in this annealing process, when Al in an AlGaAs layer diffuses into a GaAs layer, electron mobility and saturation speed will fall significantly. Therefore, the gate station in the HEMT is generally a recess type, and the variation in the recess depth in the etching step in forming the recess is reflected in the variation in (Vth). Thus, even in the process margin, the conventional HEMT is not necessarily suitable as a device constituting the integrated circuit.

In view of the foregoing, it is an object of the present invention to provide a high speed transistor having the characteristics of a pulsed MESFET (wide operating range) and HEMT (high gain) quantum.

Another object of the present invention is to provide a HEMT having a high (gm) and a small change in (gm) with respect to the gate bias, such as a pulsed-doped MESFET.

In order to achieve the above object, the semiconductor device of the present invention (e.g., having a drain nation, a source nation, and a gate nation) and controlling a current flowing through a channel (current path) between a drain and a source by a voltage applied to a gate voltage (for example, In a monolithic integrated circuit comprising a field effect transistor (FET) or a FET, a GaAs layer containing an n-type dopant (for example, Si, Se, S or Te) and a GaAs layer are sandwiched therebetween. A channel layer consisting of an undoped GaInAs layer (including a layer without a dopant, even when impurities are introduced), and an undoped semiconductor having a higher electronegativity than GaInAs (for example, GaAs , GaInP eHSMS AlGaAs). The channel layer is formed between the buffer layer and the gate station. The semiconductor device of the present invention may further include an undoped cap layer made of a semiconductor that is electrically connected to the gate station and has a larger bandgap than GaInAs. The channel layer includes at least one two-dimensional layer containing an n-type dopant, an undoped GaAs layer sandwiching the two-dimensional layer, and an undoped GaInAs layer sandwiching the GaAs layer. It can also be configured.

The channel layer may be composed of an n-type GaAs layer doped with an n-type dopant and a GaInAs layer sandwiching the GaAs layer.

The method of manufacturing a semiconductor device of the present invention comprises the steps of sequentially forming a buffer layer and an undoped GaInAs layer of undoped GaAs on a GaAs substrate, and the delta doped undoped GaAs layer and n-type dopant on the GaInAs layer Forming a channel layer by alternately growing a dope layer, forming a GaInAs layer and an undoped GaAs layer on the channel layer, and forming a gate station in a predetermined region on the undoped GaAs layer; It is composed of a process of forming a source region and a drain region by ion implantation in a self-aligned manner and forming a source nation and a whole drain region.

Another method of manufacturing a semiconductor device of the present invention comprises the steps of sequentially forming a buffer layer and an undoped GaInAs layer of undoped GaAs on the GaAs substrate, and the undoped GaAs layer, n-type dopant on the GaInAs layer Continuing to grow a delta-doped layer and an undoped GaAs layer to form a channel layer, forming a GaInAs layer and an undoped GaAs layer on the channel layer, and forming a gate station in a predetermined region on the undoped GaAs layer; And forming a source region and a drain region by ion implantation in self-alignment with respect to the gate station, and forming a source station and a drain station.

In the semiconductor device of the present invention, a two-dimensional electron gas is formed in the vicinity of a hetero interface between a GaAs layer including at least one two-dimensional layer containing an n-type dopant and a GaInAs layer immediately below. The electrons of the two-dimensional electron gas have a very high saturation speed, so the operating speed is very fast. In addition, a heterojunction is formed by a GaInAs layer and a buffer layer made of a semiconductor having a higher electronegativity and a larger bandgap than GaInAs, and an energy barrier of the conduction band is formed on this heterointerface. As a result, electrons of the two-dimensional electron gas are less likely to flow into the buffer layer, so that the transfer conductance gm in the gate bias near the threshold voltage Vth increases rapidly.

In addition, since the channel layer has a stacked structure of a two-dimensional layer including an n-type dopant and an undoped GaAs layer, a part of the two-dimensional electrons is applied when a gate bias (positive voltage bias) is applied to increase the drain current. Even if a temporary space transition occurs and jumps to the GaAs layer, the decrease in electron mobility and saturation rate is suppressed as compared to the HEMT using the conventional Si-doped AlGaAs layer. In addition, since the electrons transferred to the GaAs layer in the GaInAs layer on the GaInAs layer are separated from the GaAs layer to form a two-dimensional electron gas, the transfer conductance (gm) on the positive voltage side of the gate bias characteristic of the conventional HEMT is abrupt. Deterioration is prevented.

According to the semiconductor device of the present invention, since the two-dimensional electron gas is formed in the vicinity of the hetero interface, it is possible to operate at a very high speed, and the transfer conductance (gm) can be increased rapidly by the energy barrier of the conduction band of the hetero interface. In addition, the hetero-interface band structure between the GaAs layer and the GaInAs layer prevents a sudden drop in the transfer conductance gm, and high gain and high speed operation can be obtained over a wide gate bias range.

The invention will be more fully understood from the accompanying drawings and the following detailed description, which is not to be regarded as limiting the invention which has been given for the purpose of illustration only.

Further scope of applicability of the present invention will become apparent from the following detailed description. However, it is apparent from the above description that various modifications and variations can be made by those skilled in the art within the spirit and scope of the present invention, and therefore, it is understood that the description and the specifics indicating the preferred embodiments of the present invention are given only by way of example. .

Hereinafter, with reference to the accompanying drawings, a preferred embodiment of the present invention will be described in detail. The same or similar elements as the above-described conventional example will be simplified or omitted. In addition, "doping" means adding an impurity, and "undoping" means not adding an impurity.

5 shows a first embodiment in which the present invention is applied to a field effect transistor. The transistor is characterized by a three-layer channel layer in which undoped GaInAs layers 130a and 130b are disposed above and below the GaAs layer 140 containing at least one delta-doped layer (n-type). Here, the delta dope layer is a thin layer doped with an impurity in a planar shape, and has a substantially stepped impurity distribution with respect to the upper and lower layers.

In the upper and lower portions (undoped GaInAs layers 130a and 130b) of the three-layered channel layer, a cap layer 150 and a buffer layer 120 which are undoped GaAs layers are formed, which are formed on the substrate 110. Like the pulse-doped MESFET, the gate station 340, the n ⁺ ion implantation layers (source and drain regions) 350a and 350b formed in a self-alignment with respect to the gate station, and the source station ( 360 and a drain station 370 are formed.

The transfer conductance gm characteristic of the present transistor is regarded as shown by the solid line in FIG. The rise of the transfer conductance gm near the threshold level Vth is more rapid than that of the pulsed-doped MESFET, and the transfer conductance gm can be suppressed even if the gate bias is driven to the + side. In addition, the transfer conductance gm is considered to be higher than that of the pulse-doped MESFET as a whole. In other words, it is considered to have a characteristic that combines the wide operating range of the pulse-doped MESFET with the high gain of the HEMT. These characteristics are considered to be due to the following.

The transistor has a three-layered channel layer as a channel layer, and has a two-dimensional electron gas at an interface between the GaAs layer 140 and the GaInAs layer 130a and an interface between the cap layer 150 (GaAs) and the GaInAs layer 130b. Is formed. The electrons of the two-dimensional electron gas have a higher saturation speed than traveling in the pulsed-doped GaAs layer. As a result, the response or operating speed becomes faster. The driving control of the current flowing between the source station 360 and the drain station 370, that is, the electrons of the two-dimensional electron gas, is performed by controlling the band structure of this interface by the voltage applied to the gate station 340. Thereby, high speed equivalent to the above-described HEMT can be obtained.

In the hetero interface between the GaInAs layer 120a and the buffer layer 120 (GaAs), energy barriers are formed in the conduction band due to the difference between the band structures. Because of this energy barrier, electrons are less likely to flow into the buffer layer 120, so that when the gate bias is near the threshold level Vth, the transfer conductance gm rises rapidly. This is the cause of the difference in characteristics with the above-described MESFET.

Further, at the gate bias point for increasing the drain current, that is, the gate bias point for driving the gate bias toward the + side, even if a part of the two-dimensional electrons of the GaInAs layer 130a is brought to the real space before the jump to the GaAs layer 140, Like the HE-doped Si-doped AlGaAs layer, electron mobility and saturation rate do not decrease. This is because the GaAs layer 140 contains a GaAs layer delta-doped. A GaInAs layer 130b is formed directly under the GaAs layer 140, and electrons flow into the GaInAs layer 130b having a low potential of the conduction band to form two-dimensional electrons. In this manner, a sudden drop in the transfer conductance gm peculiar to the HEMT is prevented, and a wide operating range with respect to the gate bias can be obtained. Moreover, since the gate station is a planar structure, it is very suitable as a transistor constituting an integrated circuit. Hereinafter, the manufacturing process of the transistor of FIG. 6 (A)-FIG. 6 (C) is demonstrated. First, on the semi-insulating GaAs substrate 110 by using the organometallic vapor phase growth method (OMVPE method) or the molecular beam epitaxial method (MBE method), the conductivity type of the carrier is P type (carrier density is -5 x 10). ^A buffer layer 120 made of undoped GaAs, which is almost equivalent to an impurity concentration of ¹⁵ cm &lt; 3 &gt; Then, on the buffer layer 120, the undoped Ga0. Whose carrier type is n type (carrier density-5 * 10 <^5> cm <^-3> ). 72 In0. A GaInAs layer 130a made of 18 As is formed to have a thickness of 80 kHz. Subsequently, an undoped GaAs layer 140a having a conductivity type of carrier n-type (carrier density ˜ × 10 ¹⁵ cm ⁻³ ) is formed to have a thickness of 25 μs (FIG. 6A).

On the undoped GaAs layer 140al, after forming a delta-doped layer 140b1 delta-doped n-type impurities such as Si or Se, the carrier conductivity type is n-type (carrier density-1 x 10 ¹⁵ cm ^-3). The undoped GaAs layer 140a2 is formed to have a thickness of 25 kHz. The same process is repeated to form the delta-doped layer 140b2 and the undoped GaAs layer 140a3. Then, on the undoped GaAs layer 140a3, the undoped Ga0. Whose carrier type is n type (carrier density-1 * 10 <^15> cm <^-3> ). 80 In0. A GaInAs layer 130b made of 20 As is formed to have a thickness of 100 GPa. Subsequently, a cap layer 150 made of undoped GaAs having an n-type conductivity (carrier density! X10 ¹⁵ cm ^-3 ) of a carrier is formed to have a thickness of 300 mm 3 (B).

A gate station 340 is formed on the epitaxial structure of FIG. 6B. The transistor is completed by forming n ⁺ ion implantation layers (source region and drain region) 350a, 350b, and source nation 360 and drain nation 370 with respect to gate nation 340. (Fig. 6 (C)).

In this manufacturing step, even in the annealing step after ion implantation, no semiconductor containing A1 is used as the material of the channel, so that the decrease in electron mobility and saturation speed is suppressed.

In this way, it is possible to obtain a transistor having both advantages of the HEMT and the pulse-doped MESFET, which is useful as a low noise device, a high frequency device, or a high speed device. Moreover, since the epitaxial structure and the nationwide structure suitable for integration can be set, it is useful also as a transistor which comprises MMIC, for example.

The present invention is not limited to the first embodiment described above, and various modifications are possible.

For example, the variables in each layer can be for various values and can be used in various combinations.

In addition, the buffer layer 120 does not directly contribute to the operation of the transistor, but its thickness is determined while considering the thickness of the layer to be formed thereon.

The carrier density of the GaInAs layers 130a and 130b is changed by the growth apparatus to be less than 10 ¹⁶ cm ^-3 . In addition, the band gap varies with the composition of In in GaInAs, and the electron velocity increases as the amount of In increases. However, since the composition ratio of In is limited by the difference between the lattice constants of GaInAs and GaAs, it is usually 0.1 to 0.3 (that is, Ga is 0.9 to 0.7). The thickness of the GaInAs layer may be set to a critical thickness that decreases as the composition of In increases. In this embodiment, the thickness is up to 200 GPa, and the thickness of the GaInAs layer may be 50 to 200 GPa.

The carrier density of the GaAs layer 140 is also changed by the growth apparatus, and is usually less than 10 ¹⁶ cm ^-3 . The thicker this layer is, the more preferable it is, but the thicker the thickness, the lower the mutual conductance. In addition, in consideration of the balance with the layer to be formed thereon, an appropriate range may be 25 to 200 kPa. The carrier density of the cap layer 150 is less than 10 ¹⁵ cm ^-3 . In addition, it is sufficient to determine so as to obtain a desired mutual conductance (gm).

Instead of the undoped GaAs layer, the cap layer and the buffer layer may be a single layer structure composed of a compound semiconductor having a lower electronegativity than GaAs, such as AlGaAs or CaInP, or a laminated structure combining the compound semiconductor and GaAs.

Further, a plurality of delta-doped layers may be formed in the channel layer so that a transistor having a desired threshold level Vth can be manufactured.

In the above embodiment, the gate national structure is a planar structure by self-matching ion implantation, but is a recessed structure having a contact layer (for example, a Si-doped GaAs layer or a Si-doped GaInAs layer) of a compound semiconductor. ) May be used.

In addition, the GaInAs layer of the channel layer may have a structure in which the In composition in the GaInAs layer is changed continuously or stepwise. In this way, lattice arrangement defects of the crystal lattice of GaAs and GaInAs are alleviated, and the electron mobility is improved.

Regarding the chemical composition, GaInAs is a material represented by the general formula Ga _1-x In _x As (x> 0), and AlGaAs is a material represented by the general formula Al _m Ga _1-m As (m> 0). Is the general formula G _ar In _1-r P (r The substance represented by 0) can be used.

Hereinafter, a second embodiment of the present invention will be described.

As shown in FIG. 7, in the structure of the transistor, the undoped In _x Ga _1-x AS layer 130a (0 &lt; x) is formed on the buffer layer 120. 1), n-type GaAs layer 132 doped with impurities, undoped Iny Ga _1-y AS layer 130b (0 <y 1) and the cap layer 150 are sequentially stacked, and a gate station 340, a source station 360, and a drain station 370 are formed on the cap layer 150.

In the structure of the present transistor, the undoped Inx Gal-x AS layer 130a (0 <x ) And an undoped GaAs spacer layer may be added to the interface between the n-type GaAs layer 142 or the interface between the undoped In _y Ga _1-y As layer 130b (0 <y1) and the GaAs layer 142. This will be described later.

8 (A) and 8 (B) are band diagrams of the present transistor. FIG. 8 (A) is a band diagram when V _GS = OV, and FIG. 8 (B) shows a band diagram when VGS> OV. It's a band too.

According to the structure of the transistor, when the gate bias is driven to the + side (VGS> 0) to increase the drain low current, the transistor is generated at the interface with the undoped In _x Ga _1-x As layer 130a. Even if a part of the two-dimensional electrons 107 jumps to the impurity-doped GaAs layer 142 due to a real space transition, it falls to the In _y Ga _1-y As layer 130b formed directly on the impurity-doped GaAs layer 142. It is possible to prevent the drop in HEMT peculiar to gm.

A manufacturing process of the present transistor will be described with reference to FIGS. 9A to 9C.

On the semi-insulating GaAs substrate 110, the conductivity type of the carrier is P type (˜5 × 10 ¹⁵ cm ⁻³ ) by using organometallic vapor phase growth method (OMVPE method) or molecular beam epitaxial method (MBE method). The undoped GaAs buffer layer 120 was formed to a thickness of 10,000 Å. Then, on the GaAs buffer layer 120, the undoped In0.O-type having a conductivity type of n-type (˜1 × 10 ¹⁵ cm ⁻³ ). 18 Ga0. After the 72 As layer 130a is formed, a Si-doped GaAs layer 142 (4 x 10 ¹⁸ cm ^-13 ) is formed to a thickness of 100 microseconds (FIG. 9A). The undoped In0. Wherein the conductivity type of the carrier on the Si-doped GaAs layer 142 is N type (˜1 × 10 ¹⁵ cm ⁻³ ). 20 Ga0. After the 80 As layer 130b is formed to have a thickness of 100 GPa, an undoped GaAs cap layer 150 having a conductivity type of n-type (˜1 × 10 ¹⁵ cm ⁻³ ) is formed to have a thickness of 300 GPa (FIG. 9 ( B)). On this stacked epitaxial structure, a gate station 34 is formed, and n ⁺ ion implantation layers 350a and 350b are formed in self-alignment with respect to the gate station, followed by annealing for a short time, and n ^+. The source station 360 and the drain station 370 are formed on the ion implantation layers 350a and 350b. In this way, a transistor having a planar structure is completed (FIG. 9C).

In this embodiment, the variable of each layer can take various values similarly to the first embodiment, and may be used in various combinations.

In addition, in the present manufacturing process, defects in the crystal matching between the Si-doped GaAs layer 142 and the InGaAs layers 130a and 130b become a problem, but when the thickness of the layer is sufficiently thin, the lattice matching defect can be neglected. (JJ Rosenberg et al, IEEE Electron Device Letters, pp 491-492, Vo 1. EDL-6, No. 10, October 1985).

Immediately below the Si-doped GaAs layer 142. 18 Ga0. Since the two-dimensional electron gas is formed at the GaAs / InGaAs interface by inserting the 72 As layer 130a, the electrons move faster than traveling in the Si-doped GaAs layer 142 and have a high saturation speed. In0. 18 Ga0. Since the energy barrier of the conduction band is formed at the hetero interface between the 72 As layer 130a and the buffer layer 120, electrons are less likely to flow into the buffer layer 120, and even in the gate bias near (Vth), The ascent can rise sharply.

In addition, in the case where the gate bias is driven to the + side to increase the drain current, an IN _0.20 Ga _0.80 As layer immediately above the Si-doped GaAs layer is obtained even when a part of the two-dimensional electrons jumps to the Si-doped GaAs layer 142 in real space transition. By inserting 130b, it falls to the IN _0.20 Ga _0.80 As layer 130b, so that a sudden drop in gm peculiar to the conventional HEMT can be prevented.

The band structure of FIG. 8 is similarly applicable to the first embodiment described above.

The dependence of (gm) on the gate electrode in the transistor having such a structure is shown by the solid line in FIG. The rise of (gm) near (V _th ) is more rapid than that of the impurity doped MESFET, and (gm) does not have a peak profile similar to that of HEMT. Further, even when the gate bias is driven toward the + side, a gentle decrease of (gm) can be suppressed, and (gm) is higher than that of the impurity doped MESFET as a whole.

The high electron mobility transistor of the present invention exhibiting the above characteristics has very excellent characteristics.

The gate electrode is formed on the on-off GaAs cap layer 150, and the source electrode 360 and the drain electrode 370 are formed in the ion implantation region in a self-aligned manner with respect to the gate electrode 340. Because of this planar structure, the transistor is very suitable as a transistor constituting an integrated circuit. In the conventional HEMT, since the steepness of the AlGaAs / GaAs interface is required, the planar structure by self-aligned ion implantation cannot be adopted. In this annealing process, it is necessary to anneal at high temperature in order to activate the implanted Si, but in this annealing process, Al in the AlGaAs layer diffuses into the GaAs layer, and electrons receive impurity scattering, thereby greatly increasing the electron mobility and saturation rate. It is because it falls. In this embodiment, a planar structure is easily obtained by using a GaAs / InGaAs-based HEMT containing a small amount of diffusion In in the annealing process.

Hereinafter, a third embodiment of the present invention will be described. The difference from the previous embodiment of the present embodiment is that the cap layer 150 is omitted, and each nationwide 340, 360, and 370 are directly formed on the undoped In0.20 Ga0.80 As layer 130b. (Figure 11 (C)). With this structure, the gate leakage current slightly increases, but an effect almost similar to that of the previous embodiment can be obtained.

In the above embodiment, the cap layer 150 and the buffer layer 120 have a single layer structure of undoped GaAs, but may be a single layer structure of a compound semiconductor such as AlGaAs or InGaP, or a stack structure in which the compound semiconductor and GaAs are combined.

The gate national structure is also a planar structure using self-aligned ion implantation in the above embodiment. However, as shown in Figs. 11A or 9B, the source station 360 and the drain station 370 are shown. ) Is formed through an ohmic contact layer (Si-doped GaAs layer or Si-doped InGaAs layer) formed on the undoped In _y Ga _1-y As layer 130b or the cap layer 150, and the gate nationwide. The recessed structure may be formed on the undoped In _y Ga _1-y As layer 130b or the cap layer 130 exposed at the bottom of the ohmic contact layer.

The In composition in the InGaAs layers 130a and 130b above and below the pulse-doped GaAs layer 142 is changed continuously or stepwise in the direction perpendicular to the plane in the InGaAs layer to determine the GaAs layer and the InGaAs layer. The lattice mismatch of the lattice may be alleviated to improve the electron mobility.

In addition, an undoped GaAs spacer layer (corresponding to the undoped AlGaAs spacer layer 220 in FIG. 1) may be inserted into the GaAs / InGaAs interface.

According to the structure provided with a spacer layer as mentioned above, two-dimensional electron mobility can be improved by space | interval by an undoped GaAs spacer layer.

According to the present invention, a transistor having advantages of both a HEMT and an MESFET doped with impurities can be obtained, which is useful as a low noise device, a high frequency device, or a high speed device. Moreover, since it can be set as the epitaxial structure and national structure suitable for integration, it is useful as a transistor which comprises a microwave square type integrated circuit (MMIC).

It is apparent from the present invention described above that the present invention can be modified in various ways. Such modifications are not to be regarded as a departure from the spirit and scope of the invention, and are intended to include all such modifications as would be apparent to those skilled in the art within the scope of the following claims.

Claims (18)

A semiconductor device comprising a drain station, a source station, and a gate station, and controls a current flowing in a channel between the drain and the source by a voltage applied to the gate station, wherein the GaAs layer and the GaAs layer containing an n-type dopant are provided. And a buffer layer comprising an undoped GaInAs layer sandwiched between and a undoped semiconductor having a higher electronegativity than GaInAs, wherein the channel layer is formed between the buffer layer and the gate station. Semiconductor device. The semiconductor device according to claim 1, wherein the semiconductor of the fraud buffer layer has a larger band gap than GaInAs. The semiconductor device according to claim 1, further comprising an undoped cap layer made of a semiconductor electrically connected to the gate station and having a larger bandgap than GaInAs. The semiconductor device according to claim 3, wherein the carrier density of the channel layer is less than 10 ¹⁵ cm ^-3 . 2. The channel layer of claim 1, wherein the channel layer includes at least one two-dimensional layer containing an n-type dopant, an undoped GaAs layer sandwiching the two-dimensional layer, and the GaAs layer. A semiconductor device comprising an undoped GaInAs layer. 6. The buffer layer of claim 5, wherein the carrier type has a conductivity type of P and a thickness of 10,000 ,, and the GaInAs layer has a conductivity type of carrier of the channel layer, and the first layer facing the buffer layer is Ga0. . 72 In0. 18 Asr and its thickness is 80Å, and the first layer facing the gate nation is Ga0. 80 In0. A semiconductor device comprising 20 As and having a thickness of 100 Hz. The semiconductor device according to claim 6, further comprising an undoped n-type cap layer made of a semiconductor electrically connected to the gate station and having a larger bandgap than GaInAs, wherein the cap layer has a thickness of 300 GPa. 6. The semiconductor device according to claim 5, wherein the carrier density of the undoped layer sandwiching the two-dimensional layer of the GaAs layer of the channel layer is sandwiched between 10 and ¹⁵ cm ^-3 . 6. The semiconductor device according to claim 5, wherein the In composition in the undoped GaInAs layer has a continuous or step-shaped change. The method of claim 1, further comprising a drain region and a source region formed by introducing impurities near both ends of the channel layer. A semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 1, wherein a carrier density of the undoped GaInAs layer and the buffer layer is less than 10 ¹⁵ cm ^-3 . The semiconductor device according to claim 1, wherein the channel layer is composed of an undoped GaInAs layer sandwiching an n-type dopant-doped n-type GaAs layer and the GaAs layer. The semiconductor device according to claim 12, further comprising an undoped spacer layer containing GaAs formed between said undoped GaInAs layer and said n-type GaAs layer facing said buffer layer. 13. The method of claim 12, wherein the buffer layer is a carrier type P type and has a thickness of 10,000 Å. The GaInAs layer of the channel layer has a carrier type n type, and the first layer facing the buffer layer is Ga0. . 72 In0. It is made of 18 As and has a thickness of 80 kHz. The first layer facing the gate nation is Ga0. 80 In0. A semiconductor device comprising 20 As and having a thickness of 100 Hz. 15. The semiconductor device according to claim 14, further comprising an undoped n-type cap layer made of a semiconductor electrically connected to the gate station and having a larger bandgap than GaInAs, wherein the cap layer is 300 in thickness. ^{15. The} semiconductor device according to claim 14, wherein a carrier density of said n-type GaAs layer of said channel layer is 10 ¹⁸ cm ^-13 . Forming a channel layer by sequentially forming a buffer layer and an undoped GaInAs layer of undoped GaAs on the GaAs substrate, and delta-doped delta-doped GaAs layers and n-type dopants alternately grown on the GaInAs layer. Forming a GaInAs layer and an undoped GaAs layer on the channel layer, forming a gate station in a predetermined region on the undoped GaAs layer, and source regions by ion implantation into the gate station And forming a drain region and forming a source station and a drain station. Forming a buffer layer and an undoped GaInAs layer sequentially on the GaAs substrate, and continuing to grow the undoped GaAs layer and the undoped GaAs layer delta-doped n-type dopant on the GaInAs layer Forming a channel layer, forming a GaInAs layer and an undoped GaAs layer on the channel layer, forming a gate station in a predetermined region on the undoped GaAs layer, and implanting ions in a self-aligned manner with respect to the gate station. Forming a source region and a drain region, and forming a source region and a drain region.