JPH0194676A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To allow basic logic circuit elements to be manufactured for super high speed ICs with good controllability using heterojunction FETs by providing an etching stopper on a part of a carrier supplying layer or gate insulating film of a heterojunction FET by a combination of layers whose etching speeds are different. CONSTITUTION:A semiconductor device comprises a first high purity semiconductor layer 2 formed on a semi-insulating semiconductor substrate 1; a second semiconductor layer 3, whose electron affinity is smaller than that of the first semiconductor layer 2, formed on the first semiconductor layer 2; a third semiconductor layer 4 formed on the second semiconductor layer 3; a fourth semiconductor layer 5, whose etching speed is larger than that of the third semiconductor layer 4 relative to a solution containing at least one of hydrofluoric acid, hydrochloric acid, sulfuric acid, and phosphoric acid, formed on the third semiconductor layer 4; a first gate electrode 7 formed on the third semiconductor layer 4 of an aperture 6 formed on a part of the fourth semiconductor layer 5; a second gate electrode 8 formed on the fourth semiconductor layer 5; and a source/drain electrode 9 formed on the fourth semiconductor layer 5 adjacent to both ends of first and second gate electrodes 7, 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a heterojunction and a method for manufacturing the same.

[Conventional technology]

HE MT (lli
gh Electron nobility Tran
Field effect transistors (hereinafter referred to as FETs) using various heterojunctions have been proposed, including FETs.

These devices are usually configured as a set of two devices with different threshold voltages, an enhancement type FET and a depletion type FET, as shown in Figure 4.C
F L (Direct Coupled FET Lo
gic) is used in logic circuits as a circuit.

In this circuit, enhancement type F E T Q z
Switching is performed by depletion type FE.
TQ2 acts as its load. The element structure that constitutes this circuit, for example when a HEMT is used as a basic FET, is described in the Japanese Journal of Applied Physics.
edPhysics) Volume 20, No. L598, 198
Listed in 1 year.

FIG. 5 is a cross-sectional view of a semiconductor chip for explaining a conventional semiconductor device. High purity GaAs layer 2 on semi-insulating GaAs substrate 1 and n-type A10.3G a 0.7A
Three layers 3 are sequentially stacked to form an n-type A 10.
A gate electrode 7 is provided in a recess that is selectively etched deeply in the 3G a O,7A 3 layer 3, and a gate electrode 8 is provided in a recess that is selectively etched shallowly. n-type A Io, 3 GaO, 7 As on both sides of gate electrode 7.8
An ohmic contact electrode 9 is arranged on the layer 3, and the alloy layer 10 is composed of the high purity GaAs layer 2 and the n-type A 10.3 G
a 0.7 A It has reached the interface of 3 layers 3. At this time, the enhancement type and depression type F and ET constituting the DCFL circuit are differentiated depending on the depth of the recess.

[Problem that the invention seeks to solve]

In the conventional semiconductor device described above, when manufacturing the device, the etching depth of the AIo, 3Ga□, and 7As layers under the gate is changed in order to create enhancement type and depletion type FE layers. There is a problem in that it is difficult to obtain a desired threshold voltage due to poor depth controllability. Furthermore, it is difficult to obtain the same amount of etching over the entire surface of the wafer. When an integrated circuit is constructed using such a conventional method with poor controllability, there is a problem in that the controllability of the threshold voltage of each basic FET is deteriorated, resulting in a decrease in product yield.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, in which basic logic circuit elements of ultra-high-speed integrated circuits can be manufactured with good controllability using FETs using heterojunctions.

[Means for solving problems]

The semiconductor device of the first aspect of the invention includes a high purity first semiconductor layer provided on a semi-insulating semiconductor substrate, and an electron affinity smaller than that of the first semiconductor layer provided on the first semiconductor layer. a second semiconductor layer, a third semiconductor layer provided on the second semiconductor layer, and a hydrofluoric acid, hydrochloric acid , a fourth semiconductor layer having a high etching rate with respect to a solution containing at least one of sulfuric acid and phosphoric acid; and an opening formed in a part of the fourth semiconductor layer on the third semiconductor layer. a first gate electrode provided on the fourth semiconductor layer; a second gate electrode provided on the fourth semiconductor layer; and a second gate electrode provided on the fourth semiconductor layer near both ends of each of the first and second gate electrodes. A source electrode and a drain electrode are provided.

A semiconductor device according to a second aspect of the present invention includes a high-purity first semiconductor layer provided on a semi-insulating semiconductor substrate, and a band gap greater than that of the first semiconductor layer provided on the first semiconductor layer. A second semiconductor layer having a larger sum of electron affinities, a third semiconductor layer provided on the second semiconductor layer, and a third semiconductor layer provided on the third semiconductor layer. a fourth semiconductor layer having a high etching rate with respect to a solution containing at least one of hydrofluoric acid, hydrochloric acid, sulfuric acid, and phosphoric acid; a first gate electrode provided on the third semiconductor layer; a second gate electrode provided on the fourth semiconductor layer; It has source and drain electrodes provided on the fourth semiconductor layer.

A method for manufacturing a semiconductor device according to a third aspect of the invention includes providing a highly purified first semiconductor layer on a semi-insulating semiconductor substrate, and having a lower electron affinity than the first semiconductor layer on the first semiconductor layer. a step of providing a second semiconductor layer, a third semiconductor layer on the second semiconductor layer, and a layer containing at least one of hydrofluoric acid, hydrochloric acid, sulfuric acid, and phosphoric acid than the third semiconductor layer; a step of providing a fourth semiconductor layer having a high etching rate with respect to the solution, a step of selectively etching the fourth semiconductor layer with the solution to form an opening, and a step of etching the third semiconductor in the opening. selectively providing a first gate electrode on the fourth semiconductor layer; and providing the fourth gate electrode near both ends of each of the first and second gate electrodes. selectively providing source and drain electrodes on the semiconductor layer.

[Effect]

The present invention provides a solution containing A with a low etching rate for solutions containing at least one of hydrofluoric acid, hydrochloric acid, sulfuric acid, nitric acid, and phosphoric acid.
lx cral-XAs layer (however, 0≦X≦0.4) is used as the third semiconductor layer, and AI:, Ga1-yA8 layer (however, 0.4≦y<
1.0) is used as a fourth semiconductor layer to form a semiconductor device constituting a DCFL circuit, and a gate electrode of an enhancement type FET is provided on the third semiconductor layer in an opening provided in the fourth semiconductor layer. By providing the gate electrode of the depletion type FET on the semiconductor layer No. 4, each threshold voltage of the enhancement type FET and the depletion type FET can be defined by the thickness of the semiconductor layer.

According to the experiments of the present invention, when using about 50% hydrofluoric acid solution, the Al'(,,5Ga(,,5As) layer is 2
An etching rate of 0 nm/s was observed, whereas A I 0.3 Ga o, 7 A s ff
There was almost no etching with l. Similar selectivity has also been confirmed for hydrochloric acid, sulfuric acid, nitric acid, and phosphoric acid.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1A to 1C are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a first embodiment of the first and third inventions.

As shown in FIG. 1(a), a high-purity GaAs layer 2 with a thickness of 1 μm, an n-type layer 1 with a thickness of 15 nm, and
3 G a O, 7A 3 layer 3 and 5 nm thick n-type G
aAs layer 4 and n-type At with a film thickness of 8 nm. , 5G a 0
．． 5A 43 layers 5 and 5 are sequentially grown. Here, all the n-type layers are doped with Si to a carrier concentration of 2.times.10.sup.18 cm.sup.-3.

Next, as shown in FIG. 1(b), n-type AlO, 5G
a O,5A 3 layer 5 is selectively etched with hydrofluoric acid to form openings 6. At this time, n-type layer 1 o
-5G a□,5A s layer 5 is easily dissolved in hydrofluoric acid, but n-type Ga-As layer 4 is hardly soluble. Only 10.5G a O,5A 3 layer 5 is selected. removed.

Next, as shown in FIG. 1(C), Al is deposited on the surface including the opening 6 and selectively etched.
The gate electrode 7 and the n-type layer lo on the type GaAs layer 4,
5 Ga (gate electrode 8 on top of the 1,5A 8 layer 5 is selectively provided.Next, n-type A1 near each end of the gate electrodes 7 and 8), 5Ga on the 6.5As layer 5 A source and drain ohmic contact electrode 9 is formed by selectively sequentially depositing an Au-Ge layer and N1Ji, and then heat-treated at 450°C to form a high-purity GaAs layer 2 and an n-type A
l(,,3Gag,7Alloy layer 1 reaching the interface of As layer 3
form 0.

In the device obtained in this example, the enhancement type FET including the gate electrode 7 is made of n-type Al (1,3 Gao, 7A
10. The depletion type FET including the s layer 3 and the n-type GaAs layer 4 are used as electron supply layers, and the gate electrode 8 is the n-type layer.
3 GaO, 7As layer 3, n-type GaAs layer 4 and n-type layer Ig, 5 Ga (with 1,5As layer 5 as an electron supply layer,
Both have a high purity GaAs layer 2 and an n-type layer l. ,3G
a 0.7 A A two-dimensional electron gas layer is generated at the interface of the eight layers 3 to form a channel. In addition, the threshold voltages of the obtained elements are 0.02V for the enhancement type FET, -o, 44V for the depletion type FET, and E/
A D-configuration DCFL inverter is configured.

FIGS. 2(a) to 2(c) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a second embodiment of the first and third inventions.

As shown in FIG. 2(a), a high-purity G film with a thickness of 1 μm was deposited on a semi-insulating GaAs substrate 1 by molecular beam epitaxy.
aAs layer 2 and Si with a film thickness of 10 nm in a size of 2×1018 cm
-' doped n-type GaAs layer 4 with a film thickness of 5n
m high purity A I o, 3G a □, 7A 9 layers 1
1, a high purity GaAs layer 12 with a film thickness of 5 nm, and a film thickness of 18
8 layers 13 of high-purity A 1 o-1tGa O, 5A with a thickness of 10 nm are sequentially grown.

Next, as shown in FIG. 2(b), high-purity A 10.50 a 0.5As
Layer 13 is selectively etched to provide openings 6.

Next, as shown in FIG. 2(C), the high-purity G in the opening 6 is
Gate electrode 7 on aAs layer 12 and high purity A I0.
A gate electrode 8 on top of the 50 ao and 5 A s layers 13 is provided, respectively, followed by high purity A L. ,5Ga. ,5As
An ohmic contact electrode 9 on J113 and an alloy layer 10 reaching the interface between the high-purity GaA 8 layer 2 and the n-type GaAs layer 4 are formed.

The device obtained in this example is an enhancement type FE
High purity of T A 10.30 a 0.7 A 9 layers 11
and the high-purity GaAs layer 12 is a gate insulating film,
High purity A I 0.3 G of depression type FET
The ao,7As layer 11, the high-purity GaAs layer 12, and the high-purity AIO,5Ga0.5As layer 13 are gate insulating films, and each uses the n-type GaAs layer 4 as a channel. In addition, the threshold voltage is o, osv for enhancement type FET and -0,42V for depletion type FET.
This constitutes E/D Gosei's DCFL inverter.

FIGS. 3A to 3C are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the second invention.

As shown in FIG. 3 (a), a high-purity GaAs layer 2 with a thickness of 1 μm and a p-type layer 10.3 G with a thickness of 15 nm are formed on a semi-insulating GaAs substrate 1 by molecular beam epitaxy.
a 6.7 A 5 layers 14 and 5 nm thick p-type Ga
As layer 15 and p-type AlO, 5G a O with a film thickness of 8 nm
, 5A s layer 16 are sequentially grown. Here, all p-type layers are doped with Be to a carrier concentration of 2.times.10.sup.18 cm.sup.-'.

Next, as shown in FIG. 3(b), p-type AtO, 5G
The ao-5A 8 layer 16 is selectively etched with hydrofluoric acid to form the opening 6. At this time, the p-type layer l
□, 5 Ga □, 5 A The 8 layers 16 easily dissolve in hydrofluoric acid, but the p-type GaAs layer 15 hardly dissolves and serves as an etching stopper.
(,,"5 Only the As layer 16 is removed.

Next, as shown in FIG. 3(c), the gate electrode 7 on the p-type GaAs layer 15 in the opening 6 and the p-type layer to,s Ga0.5 AsN16 are formed in the same process as in the first embodiment. The upper gate electrode 8 is selectively provided, p-type AlO,
Ohmic contact electrode on 5GaO, 5As layer 16, high purity GaAsN 2 and p-type A 10.
An alloy layer 10 is formed that reaches the interface of the three 3G a O,7A layers 13 .

The obtained device is a p-type A1 enhancement type FET.
(1,3G a O, 7A 8 layer 14 and p-type GaAs
The layer 15 is a hole supply layer, and the p-type A10.3Ga(,,7As layer 14 and the p-type GaA
s115 and p-type A 10.5 GaO, 5As layer 16
is the hole supply layer, and both are the high purity GaAs layer 2 and the p
A two-dimensional hole gas layer is generated at the interface of the type A 1 g, 3 Ga □, and 7 As layers 14 to serve as a channel.

In addition, the threshold voltage of the obtained device is 0.02V for the enhancement type FET and -.
It is 0.44V and constitutes a DCFL inverter with an E/D configuration.

〔Effect of the invention〕

As explained above, the present invention provides an FE using a heterojunction.
By forming an etching stopper by combining layers with different etching rates on the T carrier supply layer or part of the gate insulating film, the film thickness for forming enhancement type and depletion type FETs can be controlled with good reproducibility, and enhancement This has the effect that the threshold voltages of the 7-ment type and depression type FETs can be controlled to predetermined values.

[Brief explanation of the drawing]

Figures 1 (a) to (C) and Figures 2 (a) to (C) are
and FIG. 3(a) is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining the first and second embodiments of the third invention.
-(C) are cross-sectional views of a semiconductor chip shown in the order of steps to explain an embodiment of the second invention, FIG. 4 is an equivalent circuit showing the configuration of a DCFL circuit, and FIG. 5 is a diagram showing a conventional semiconductor device. FIG. 2 is a cross-sectional view of a semiconductor chip for explanation. 1... Semi-insulating GaAs substrate, 2... High purity GaA
s layer, 3--n-type A 10.3 Gao, 7 As layer, 4... n-type GaAs layer, 5-n-type A Ig, 5 G
a (1,5As layer, 6...opening, 7,8...gate electrode, 9...ohmic contact electrode, 10...
・Alloy layer, 11... High purity A Io, 3 Ga017
ASFJ, 12-... High purity GaAs layer, 13...
High purity A10.50a (,5As layer, 14-p type A
1 (1,3G a 6.7A S layer, 15-p type G
aAs layer, 16-p type A 10.5 Ga 6.5
A S layer, 21...input, 22...output, 23...
・Power supply, Ql... Enhancement type FET, Q2・
...Depression type FET0

Claims (3)

[Claims] (1) A high-purity first semiconductor layer provided on a semi-insulating semiconductor substrate, and a second semiconductor layer having a lower electron affinity than the first semiconductor layer provided on the first semiconductor layer. , a third semiconductor layer provided on the second semiconductor layer, containing less hydrofluoric acid, hydrochloric acid, sulfuric acid, and phosphoric acid than the third semiconductor layer provided on the third semiconductor layer; a fourth semiconductor layer having a high etching rate with respect to a solution containing one of the above; and the third semiconductor layer in an opening provided in a part of the fourth semiconductor layer;
a first gate electrode provided on the semiconductor layer;
a second gate electrode provided on the semiconductor layer;
and source and drain electrodes provided on the fourth semiconductor layer near both ends of each second gate electrode. (2) A high-purity first semiconductor layer provided on a semi-insulating semiconductor substrate has a larger sum of forbidden band width and electron affinity than the first semiconductor layer provided on the first semiconductor layer. a second semiconductor layer, a third semiconductor layer provided on the second semiconductor layer, and a hydrofluoric acid, hydrochloric acid , a fourth semiconductor layer having a high etching rate with respect to a solution containing at least one of sulfuric acid and phosphoric acid; and an opening provided in a part of the fourth semiconductor layer on the third semiconductor layer. a first gate electrode provided on the fourth semiconductor layer, a second gate electrode provided on the fourth semiconductor layer, and a second gate electrode provided on the fourth semiconductor layer near both ends of each of the first and second gate electrodes. 1. A semiconductor device comprising source and drain electrodes. (3) providing a high-purity first semiconductor layer on a semi-insulating semiconductor substrate, and providing a second semiconductor layer having a lower electron affinity than the first semiconductor layer on the first semiconductor layer; , a third semiconductor layer on the second semiconductor layer, and a third semiconductor layer having a higher etching rate than the third semiconductor layer with respect to a solution containing at least one of hydrofluoric acid, hydrochloric acid, sulfuric acid, and phosphoric acid. a step of selectively etching the fourth semiconductor layer with the solution to form an opening; and a step of forming a first semiconductor layer on the third semiconductor layer in the opening.
selectively providing gate electrodes and providing a second gate electrode on the fourth semiconductor layer; and a step of providing a second gate electrode on the fourth semiconductor layer near both ends of each of the first and second gate electrodes. A method for manufacturing a semiconductor device, comprising the step of selectively providing source and drain electrodes.