JPH03224243A - Velocity modulation transistor - Google Patents

Abstract

PURPOSE:To increase velocity modulation effect by forming a first barrier layer, a first channel layer, a second channel layer, etc., on a semiinsulative substrate, and making the electron affinity of the second channel layer larger than that of the first channel layer. CONSTITUTION:On a semiinsulating GaAs substrate 1 the following are firstly formed; a GaAs layer 2, an N-type AlGaAs layer 3 (first barrier layer), an N-type GaAs layer 4 (first channel layer), an AlGaAs layer 5 (second barrier layer), an InGaAs layer 6 (second channel layer), etc. After an N-type AlGaAs layer 7 (third barrier layer) doped with Si and an N-type GaAs layer 8 doped with Si are formed in order, a part of the layer 8 is eliminated, thereby forming a gate, electrode (control electrode) 9 on the exposed layer 7. A source electrode (input electrode) 10 and a drain electrode (output electrode) 11 are formed on the layer 8. In addition to the film thickness control of a channel layer, the electron affinity of the layer 6 is made larger than that of the layer 4, thereby increasing velocity modulation effect at a room temperature.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a speed modulation transistor, and more particularly to a speed modulation transistor that utilizes a double quantum well structure.

(b) Conventional technology In a heterojunction transistor, a narrow heterojunction interface is formed by joining a semiconductor with a wide bandgap, which is an electron supply layer, and a semiconductor with a narrow bandgap, which allows high electron mobility. The semiconductor side of the forbidden band width is used as a channel, and switching is performed by adjusting the concentration of electrons flowing through this channel. Therefore, the time of charging and discharging electrons determines the operating speed of the heterojunction transistor.

To overcome this speed limitation, heterojunction transistors have been proposed that perform switching by adjusting the speed of electrons (H, 5akaki; Jp.
n, J., Appl, Phys, 21 (1982
) See L381).

This heterojunction transistor is called a speed modulation transistor and is equipped with two heterojunctions formed in two channel layers with different impurity concentrations and two gate wires sandwiching the two heterojunctions. It is something. The channel through which carriers flow can be changed by changing the gate bias of the gate electrode.

The change in channel conbutance (ΔG) with respect to the gate bias (ΔVg) is ΔG ” Q /l +llΔN + q NΔμ−7
given. Here, q is the charge of the carrier, 〆1. ．．
．． is the carrier mobility, ΔN is the change in carrier concentration, and ΔMele is the change in carrier mobility. One must be provided inside the speed modulation transistor.

Therefore, a speed modulation transistor that can operate in the same way as described above with one gate electrode has been proposed (Okuno et al., Vol. 5).
Proceedings of the 0th Japan Society of Applied Physics Academic Conference (1989) 106
8).

FIG. 3 is a schematic cross-sectional view of this speed modulation transistor with one gate electrode. A method of manufacturing this speed modulation transistor will be explained below.

Semi-insulating GaAs substrate 31-himGaAs layer 3
2. n-type AlGaAs layer 3; 3. n-type GaAs layer 3
4, AlGaAs layer 35, GaAs layer 36, n-type, A
IGaAs layer 37, and n-type Ga, A
The s-layer 38 is sequentially formed. Thereafter, by removing a portion of the n-type GaAs layer 38, the exposed n-type A
A gate electrode 39 is formed on the lGaAs layer 37, and a source electrode 40 and a drain electrode 41 are formed on the n-type Ga, As layer 38. A velocity modulation transistor with poles is completed. In addition, GaAs
The thickness of the layer 36 is made larger than that of the n-type GaAs layer 34.

This speed modulation transistor has two types of channel layers (Ga
As layer 34, 36) as barrier layer (, AlGaAs layer 35)
When a gate bias is not applied, the lowest quantum level (first level) in the GaAs layer 34 is lower than the lowest quantum level (second level) in the GaAs layer 36. Therefore, the electrons at the lowest quantum level in the transistor are transferred to the channel layer (G a A ) with a wide well width (film thickness).
The electrons localized in the s layer 3 (5) and having the second lowest quantum $ in the transistor are located in the channel layer (GaA
s enemy: (localized at -11. Also, in this velocity modulation transistor, the channel layer with a narrow well width (GaAs layer 3
Since Si is doped only in 4), the electron mobility in the channel layer with the narrow well width is lower than that in the channel layer with the wide well width.

So 2. By applying a negative gate bias to the gate electrode 39 on the AIGaAs layer 37, the channel through which electrons flow is changed from a channel layer with a wide well width with high electron mobility to a channel layer with a narrow well width with low electron mobility. By changing to the channel layer, switching can be performed.

That is, by applying a gate bias to a channel layer having a wide well width, switching can be performed by utilizing the fact that the first level becomes lower than the second level.

(c) Problems to be Solved by the Invention Conventionally, the forbidden band width for both channel sounds is the same t2
Both layers are G a A, s layers), so without applying gate bias:! Since the first level is higher than the second level, the thickness of the GaAs layer was appropriately controlled, but the resulting energy difference between the first level and the second level has its limits.

In other words, in the speed modulation transistor shown in Fig. 3, the energy difference between the first level and the second level (approximately 0.1e~') is small, so when no gate bias is applied at room temperature, the two There is a problem in that electrons exist in the channel layer and the velocity modulation effect is small.

The present invention has been made in view of the above problems, and is intended to provide a speed modulation transistor that has a greater speed modulation effect than conventional transistors.

(d) Means for Solving the Problems The present invention provides a first barrier layer formed on a semi-insulating substrate, a first channel layer formed on the first barrier layer, and a first barrier layer formed on the semi-insulating substrate. a second barrier layer formed on the first channel layer, a second channel layer formed on the second barrier layer, and a third barrier layer formed on the second channel layer. and an input/output pole and a control electrode formed on the third barrier layer, and the forbidden band width of the second channel layer is smaller than that of the first channel layer. This is a speed modulation transistor.

(e) Effect According to the present invention, in addition to controlling the film thickness of the channel layer, the first level can also be improved by making the forbidden band width of the second channel layer smaller than that of the first channel layer. Since the energy difference between the first channel layer and the second level can be obtained, the probability that electrons exist in the first channel layer at room temperature and without applying a gate bias is lower than in the past.

(F) Embodiment FIG. 1(a) is a schematic sectional view of a speed modulation transistor according to a first embodiment of the present invention. A method of manufacturing this speed modulation transistor will be explained below.

GaAs on a semi-insulating GaAs substrate (semi-insulating substrate)
Layer 2, Si-doped ll-type AlGaAs layer (first
barrier layer) 3, Si-doped n-type GaAs
layer (first channel layer) 4, AtGaAs layer (second barrier layer > 5, InGaAs layer (second channel layer) (In pine ratio 0.25) 6, doped with S] n-type AlGaAs layer (third barrier layer = AI composition ratio 0.3) 7
, and an n-type GaAs layer 8 doped with Sl are successively formed.

Thereafter, a gate electrode (control 1 is the pole) 9 is formed on the n-type GaAs layer 7 exposed by removing a part of the n-type GaAs layer 8, and the gate electrode 9 is formed on the n-type GaAs layer 7.
By forming a source electrode (r input electrode) 10 and a drain electrode (output electrode) 11 on layer 8, the speed modulation transistor of the first embodiment of the present invention is completed. Here, G
a A s The forbidden band width Eg of layer 4 is approximately 1.42 eV,
The forbidden band width Eg of the InGaAs layer 6 is approximately 1.08 eV. Note that the thickness of the GaAs layer 4 is 70 mm, InGaA
The film thickness of the s-layer 6 was set to 100 layers.

Without applying a bias V g to the gate electrode 9 of such a speed modulation transistor, the source electrode 10 and the drain electrode 1
The conduction band structure directly under the gate when a DC voltage is applied between 1 and 1 is as shown in FIG. 2(a). As is clear from this figure, electrons are flowing in the InGaAs layer 6, and the electron mobility is as large as 80000 m',·vs, which corresponds to the ON state of the velocity modulation transistor. Note that the numerical values in the figure are approximate values obtained by calculation.

Further, in the above state, the gate electrode 9 is biased with v
When g is applied, the conduction band structure directly under the gate becomes as shown in FIG. 2(b). As is clear from this figure, electrons are transferred from the InGa and As layers 6 to the GaA due to the t field and tunneling effect caused by the bias Vg.
Electrons move to the S layer 4 at high speed and flow through the GaAs layer 4, but since the GaAs layer 4 is doped with Sl, the electron mobility is small at 2000 cm"7VS, which is the OFF state of the velocity modulation transistor. Equivalent to.

As mentioned above, the switching time of the speed modulation transistor of the present invention is such that electrons are transferred from the InGaAs layer 6 to Ga, A
It is determined by the time taken for electrons to move to the s-layer 4, and this time is smaller than the time required for charging and discharging electrons. Also, the energy difference between the tie level and the second level is about 0.22 eV, which is about 0.1
significantly exceeds eV. However, the speed modulation transistor of the present invention has a greater speed modulation effect at room temperature than that of the prior art.

FIG. 1(b) is a schematic cross-sectional view of a speed modulation transistor according to a second embodiment of the present invention. A method of manufacturing this speed modulation transistor will be explained below.

InG on a semi-insulating InP substrate (semi-insulating substrate) 15
aAs layer 16, Si-doped n-type 1n AIAs layer (first barrier layer) 17, Si-doped n-type In
G a A 1 , A s layer (first channel layer) 1
8. InAlAs layer (second barrier layer) 19. InGaA
s layer (second channel layer) (In composition ratio 0.53) 20
．． Si-doped n-type InAIAs layer (
third barrier layer) (In composition ratio 0.32) 21, and Sl
An n-type InGaAs layer 22 doped with is sequentially formed. Thereafter, by removing a portion of the n-type InGaAs layer 22, the exposed n-type InAlAsnGa
Above As layer 21! (control electrode) 23 is formed, and an n-type I
Source 1 is placed on the n Ga AS layer 22 (input electrode)
By forming 21 and drain and in electrodes (output electrodes) 25, I) the speed modulation transistor of the second embodiment of the present invention is completed.

Here, the forbidden band width Eg of the InGaAlAs layer 18 is approximately 1
．． '1 OeV, the forbidden band width Eg of the rn Ga A 8 layer 20 is about 0.75e~'. In addition, InGaAl
Such velocity modulation is performed when the thickness of the As layer 18 is 70 mm and the thickness of the InGaAs layer 20 is 100 mm. When a DC voltage is applied between the electrodes 25, electrons are transferred to InGaAs
flows through the layer 20, the electron mobility is 11000 cm'', /v
s, which is the ON# of the speed modulation transistor,
corresponds to the state of

In addition, in the above-mentioned state, when a bias ~'g is applied to the gate electrode 23, electrons are transferred to I n Ga A due to the electric field and tunneling effect generated by the bias Vg.
The electrons move from the InGaAlAs layer 18 from the InGaAlAs layer 18 at high speed, and the electrons enter the InGaA IAs layer 8, but the I
Since the n Ga, A I A 5 layer 18 is doped with Sl, the electron mobility is 1000 cm'/~
- Small as S, which corresponds to the OFF state of the speed modulation transistor.

As mentioned above, the switching time of the speed modulation transistor of the present invention is determined by the time taken for electrons to move from the InGaAs layer 20 to the InGaAlA 5 layer 18, and this time is determined by the charging and discharging of electrons. It is small compared to the time required. Further, the energy difference between the first level and the second level is about 0.25 e~', which is larger than that of the first embodiment, and the In composition ratio of the InGaAs layer 20 is higher than that of the first embodiment. Since it is larger than the example, the electron mobility is also larger than that of the first example. Therefore, the speed modulation effect of the speed modulation transistor of the second embodiment of the present invention at room temperature is large, and moreover, it is greater than that of the first embodiment.

In the first embodiment described above, I of the InGaAs layer 6
The energy difference between the first and second standards of the speed modulation transistor (sample A) with an n composition ratio of 0.2 is 0.18
eV, and the energy difference between the first level and second level of the velocity modulation transistor (sample B) with an In composition ratio of 0.35 is about 0.29 eV.

It can be seen from 2t1 that as the In ratio of the InGaAs layer increases, that is, as the forbidden band width decreases, the energy difference between the first level and the second level increases.

Considering only the operation at room temperature, it is desirable to increase the In\composition ratio of the InGaAs layer 6.

However, when the In composition ratio of the In Ga, As layer 5 is increased, dislocations occur due to the increased lattice strain with the Al Ga, As layer 5, and the electron mobility decreases. decreases.

The electron mobility in sample A is 76 Q Ocm', /
%'-5, Sample B' is 4000cm', /v-s
], consider only the energy difference between the first and second levels.
, and increasing the In composition ratio, the electron transfer #'
J degree decreases.

Below, a speed modulation transistor that can obtain a large energy difference between the first level and the second level without reducing the electron mobility will be described.

FIG. 4 is a schematic cross-sectional view of a speed modulation transistor according to a third embodiment of the present invention, and the same parts as in the first embodiment are denoted by the same reference numerals, and their explanation will be omitted.

The difference between the third embodiment and the first embodiment is that InGa
In place of the As layer 6, a superlattice film is used in which four-molecular layers of InGaAs layers (In composition ratio 0.5) and two-molecular layers of GaAs layers are alternately laminated. In this example, the superlattice film was composed of 6 InGaAs layers and 5 GaAs layers (total thickness 95%).The In composition ratio of this superlattice film (I
n average composition ratio) is 0.35, but the superlattice film has A
It has an excellent ability to suppress the generation of dislocations due to lattice mismatch with the lGaAs layer 5, so the electron mobility is 8600.
cm”, /v, s. From now on, like Cal, I
By replacing the nGaAs layer with a superlattice film, the generation of dislocations due to lattice strain is suppressed, and a large energy difference between the first and second levels (
approximately 0.29 e'v-) can be obtained.

The structure of the conduction band immediately below the date when the bias Vg is not applied to the gate electrode 9 of such a speed modulation transistor and a DC voltage is applied between the source pole 10 and the drain electrode 11 is shown in Figure 5. It will be as shown.

In addition, as superlattice films, InGaAs, Ga, As
In addition to the combination of 1nAs and GaAs, a superlattice film may be used in place of the InGaAs layer 20 of the second embodiment without reducing the electron mobility (, The energy difference between the first level and the second level can be obtained.

In addition, in each of the above embodiments, layer 2.8.16.22
is not necessarily necessary and may be an appropriate film. Also, layer 7.21 may be non-doped.

(G) Effects of the Invention As is clear from the above description, the present invention can increase the energy difference between the first level and the second level, thereby increasing the velocity modulation effect at room temperature. I can do it.

[Brief explanation of drawings]

1(a)(b) and 4 are schematic cross-sectional views of a speed modulation transistor according to an embodiment of the present invention, and FIG. 2(a)(b)
) and FIG. 5 are diagrams showing the conduction band structure, and FIG. 3 is a schematic cross-sectional view of a conventional velocity modulation transistor. 1... Semi-insulating Ga r~S substrate, 2... GaA
s layer, 3-AIGaAs layer, 4-n type GaAs layer, 5
-=AIGaAs layer, 6 ・-I n Ga As
layer, 12. superlattice film, 15... semi-insulating InP substrate,
16...InGaAs layer, 17-InAIAs layer, 18
... n-type I n G a A l , As layer, 1
9 ・・I n A I As layer, 20 ・−1n
GaAs layer, 9.23--gate electrode, 10.
24... Source electrode, II, 25... Drain electrode.

Claims (2)

[Claims] (1) A first barrier layer formed on a semi-insulating substrate, a first channel layer formed on the first barrier layer, and a second barrier layer formed on the first channel layer. a second barrier layer formed on the second barrier layer, a third barrier layer formed on the second channel layer, and a second barrier layer formed on the third barrier layer. A speed modulation transistor comprising input/output electrodes and control electrodes, wherein the second channel layer has a band gap smaller than that of the first channel layer. (2) The speed modulation transistor according to claim 1, wherein the second channel layer is a superlattice film.