JPH0312769B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a heterojunction semiconductor device, particularly InAs/AlxGa _1-x AsySb _1-y (y=0.067x+0.09)
This invention relates to a semiconductor device using a heterojunction system.

[Background technology]

A junction between two dissimilar semiconductors (heterojunction) has the effect of forming an electron storage layer or confining carriers on the lower conductive band side of the hetero interface due to the discontinuity at the bottom of the conductive band, making it useful for high-speed devices, semiconductor lasers, etc. It's being used. The characteristics of a heterojunction differ significantly depending on the energy band structure (energy band gap, electron affinity) of the two semiconductors to be joined.

Conventionally, the typical heterojunction used for high-speed devices is GaAs/AlGaAs system, and GaAs
It provides high-speed operation than MESFET, but the operation layer
Because the carrier easily transitions from the P valley (main band) to the L valley (subband) in GaAs, valley scattering with negative differential mobility occurs, which is important for realizing varistic devices and high-mobility active devices. There was a problem.

[Disclosure of the invention]

Therefore, the object of the present invention is to
Our goal is to provide high-speed devices that solve the problems of InGaAs-based and InGaAs-based heterojunction devices.
This purpose is achieved in the present invention by combining InAs and AlxGa _1-x
The problem is solved by a semiconductor device using a heterojunction with AsySb _1-y .

The present invention uses InAs instead of GaAs. As shown in the relationship between electric field strength and electron drift velocity in Figure 1, InAs has a higher low-field mobility of electrons, a higher peak velocity, and a lower electron velocity overshoot than GaAs. It has advantages such as being large. For this reason, it is more suitable than GaAs for the active layer of an electron transport device that operates at high speed.

Now, in order to use InAs as the active layer, that is, the layer in which the carrier actually runs, the other semiconductor to be bonded to InAs must have an electron affinity smaller than InAs, but a forbidden band width larger than InAs, and a lattice match to InAs. It has to be something. Quaternary mixed crystal AlxGa _1-x AsySb _1-y (y=0.067x+
0.09) is a material that satisfies these conditions. In other words, the energy bandgap of AlxGa _1-x AsySb _1-y (y=0.067x+0.09) is as shown in Figure 2.
It is 0.75 eV to 1.6 eV (0.36 eV for InAs), and the lattice constant is 6.058 Å, which is equal to IsAs. Also, AlSb,
The electron affinity of GaAs and InAs is 3.64eV, respectively.
4.05eV, 4.03eV, 4.54eV, so AlxGa _1-x
It is thought that the electron affinity between AsySb _1-y (y=0.067x+0.09) and InAs is larger for InAs by about 0.5 eV to 0.9 eV.

Hereinafter, specific embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 3 shows a cross-sectional structure of an embodiment of a modulation doped shot gate field effect transistor according to the present invention. In Fig. 3, semi-insulating InP substrate 1
1, a 1 μm undoped In _0.53 Ga _0.47 As layer 12,
Undoped In _0.65 Ga _0.35 As layer 13 of 2000 Å each,
In. _0.77 Ga _0.23 As layer 14, In _0.88 Ga _0.12 As layer 15,
1 μm AlAs _0.16 Sb _0.84 layer 16, 1000 Å undoped InAs layer 17, 0-200 Å undoped Al _0.5
Ga _0.5 As _0.12 Sb _0.88 layer 18, thickness 500 with Si doping
~1000Å 1×10 ¹⁸ 1/cm ³ n ⁺ type Al _0.5 Ga _0.5 As _0.12
Sb _0.88 layer 19 is grown sequentially by, for example, molecular beam epitaxial method, and this n ⁺ type Al _0.5 Ga _0.5 As _0.12
It has a structure in which a shot gate electrode 20 of Al is provided on the Sb _0.88 19, and ohmic electrodes 21 and 22 of AuGeNi are provided on both sides of the gate electrode 20. As shown in FIG. 4, electrons accumulate on the InAs side of the heterointerface due to the discontinuity at the bottom of the conductive band between InAs and Al _0.5 Ga _0.5 As _0.12 Sb _0.88 . That is, since InAs has a large electron affinity, electrons supplied by donors in the n ⁺ type Al _0.5 Ga _0.5 As _0.12 Sb _0.88 layer are attracted to the InAs side, forming an electron storage layer. This electron storage layer contributes to electrical conduction between the source and drain, but since the InAs layer is not doped with impurities, ionized impurity scattering is reduced.
This effect is particularly large at low temperatures where ionized impurity scattering becomes dominant, resulting in high electron mobility. Conventional FETs based on a similar principle, that is, a doped region where carriers are generated and an undoped region where the carriers actually move, have been developed using GaAs/
A device using an AlGaAs heterojunction is known. In the present invention, instead of GaAs as the active layer,
Since InAs is used, high-speed operation is possible because the electron velocity of InAs is higher than that of GaAs, as mentioned above. Also In _0.52 Al _0.98 As／In _0.53
FETs using Ga _0.47 Al telo-interfaces have recently been proposed, but high electron mobility has not been achieved due to the influence of alloy scattering in the In _0.53 Ga _0.47 As mixed crystal. In the FET according to the present invention, InAs is used in the active layer.
Since this method uses alloy scattering, there is no problem with alloy scattering, and a high-speed operation FET can be realized. Note that the FET according to the present invention
In this case, semi-insulating InP is used as the substrate, and
Buffer layers with stepwise different compositions of InxGa _1-x As are used. This is because there is no high-quality semi-insulating substrate that can lattice match InAs.
It uses InP and buffer layers with slightly different lattice constants. This InxGa _1-x As buffer layer has a lattice mismatch of 0.8% at the interface, but the X-ray diffraction experiment shown in Figure 5 shows that the InAs layer grown on this buffer layer has a good quality crystal. This is clear from the results.

This buffer layer is not limited to the one described in this embodiment, but may be of any type as long as it connects semiconductor layers having different lattice constants without difficulty.

FIG. 6 shows a cross-sectional structure of an embodiment of a real space transition type semiconductor device according to the present invention. In Figure 6,
1 μm undoped on semi-insulating InP substrate 31
In _0.53 Ga _0.47 As layer 32, each 2000 Å undoped
In _0.65 Ga _0.35 As layer 33, In _0.77 Ga _0.23 As layer 34,
In _0.88 Ga _0.12 As layer 35, 1 μm AlAs _0.16 Sb _0.84 layer 3
6, and Al _0.5 Ga _0.5 As _0.12 Sb _0.88 layers 37 and InAs layers 38 are alternately grown thereon.
Although this embodiment has a multi-layered structure in which double heterojunctions are repeated, a single-layered structure with a single heterojunction may also be used. 39 and 40 are ohmic electrodes provided substantially perpendicular to this laminated structure. As described above, an electron storage layer is formed on the InAs side of each heterointerface. When an electric field is applied between the ohmic electrodes 39 and 40, the electrons in InAs are accelerated and become hot electrons, but the upper valley (L valley) in InAs
It is scattered into the Al _0.5 Ga _0.5 As _0.12 Sb _0.88 layer before transitioning to . Since the electron mobility in Al _0.5 Ga _0.5 As _0.12 Sb _0.88 is smaller than in InAs, negative differential resistance occurs. Since the electron transition time is determined by the lateral length, it is expected to operate at higher frequencies than Gunn diodes. Conventionally, this type of semiconductor device is
A device using a GaAs-AlGaAs heterointerface is known. However, in GaAs, the energy difference △E _PL between the P valley and the L valley is relatively small at 0.31 eV, so
Hot electrons tend to transition to the L valley before being scattered into AlxGa _1-x As. Therefore, even if negative differential resistance was obtained, it was due to the Gunn effect, and it was difficult to realize the phenomenon of negative differential resistance due to pure real space transition. Compared to this, InAs/AlxGa _1-x AsySb _1-y (y=0.067x+0.09) according to the present invention
In the case of using a heterojunction, the △E _PL of InAs is
Because it is as large as 0.7eV, it is difficult for the hot electrons in InAs to transition to the L valley before being scattered in AlxGa _1-x AsySb _1-y (y = 0.067x + 0.09), making it possible to obtain pure Negative differential resistance due to real space transition is obtained. Note that the undoped InAs layer 38 and n ⁺ type Al _0.5 Ga _0.5 As _0.12 Sb _0.88 are formed using the modulation doping method.
A layer 37 may be formed to increase electron mobility in InAs.

FIG. 7 shows an embodiment of a bipolar heterojunction transistor according to the invention. In Figure 7, P ⁺
type InAs substrate (n=2×10 ¹⁸ 1/cm ³ ) on 41
0.5 μm thick P ^- type InAs collector layer (1×10 ¹⁶ 1/cm ³ )
42, 500 Å thick n ⁺ type (1×10 ¹⁹ 1/cm ³ ) InAs base layer 43, 0.2 μm thick P type (2×10 ¹⁷ 1/cm ³ )
The structure includes an Al _0.5 Ga _0.5 As _0.12 Sb _0.88 emitter layer 44 and a 0.2 μm thick P ⁺ type (1×10 ¹⁹ 1/cm ³ ) InAs cap layer 45. A transistor with this structure is
It has advantages such as large current density in the active layers of the base and collector, large gm, small fan-out dependence, and small operating amplitude. Also, if the thickness of the base layer can be reduced to sub-microns, varistic operation or electron velocity overshoot effects are possible.

Conventionally known GaAs/AlxGa _1-x As bipolar heterojunction transistors use GaAs for the base layer, so as mentioned above, the energy difference △E _PL between the P valley and the L valley is relatively small, and the band Phonon scattering is likely to occur. In comparison, the transistor according to the present invention uses InAs as the active layer and has a large ΔE _PL , so that interband phonon scattering does not occur in the base region and varistic operation or electron velocity overshoot operation is likely to occur. This makes it possible to create ultra-high-speed transistors.

[Industrial applicability]

As described above, InAs/AlxGa _1-x according to the present invention
Various devices using AsySb _1-y (y=0.067x+0.09) heterojunctions have higher operating speeds than conventional devices, so FETs, IC Gunn diodes, etc. are currently used. It can be used in all fields, and its industrial value is extremely high, especially in fields that require high-speed processing, such as computers.
It is expected to be used for CPU, memory, image processing, etc.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the electric field strength dependence of electron velocity in GaAs and InAs. FIG. 2 is a diagram showing the relationship between the energy band gap and lattice constant of a -V group compound semiconductor. Figure 3 shows InAs/AlxGa _1-x AsySb _1-y (y=0.067x+0.09) according to the present invention.
FIG. 2 is a cross-sectional view of a modulation doped field effect transistor using an interface of FIG. Figure 4 shows InAs/Al _0.5 Ga _0.5
It is an energy band diagram at the As _0.12 Sb _0.88 hetero interface. FIG. 5 is an X-ray rocking curve of InAs grown on an InP substrate via an InxGa _1-x As multilayer buffer layer. Figure 6 shows InAs/AlxGa _1-x AsySb _1-y (y=0.067x+0.09) according to the present invention.
FIG. 2 is a cross-sectional structural diagram of a real space transition type semiconductor device using a heterointerface. Figure 7 shows InAs in the base layer.
AlxGa _1-x AsySb _1-y (y=0.067x+
0.09) according to the present invention; FIG. 11, 31 are semi-insulating InP substrates, 12, 32 are semi-insulating InP substrates,
In _0.53 Ga _0.47 As layer, 13 and 33 are In _0.65 Ga _0.35 As layer,
14 and 34 are In _0.77 Ga _0.23 As layers, 15 and 35 are
In _0.88 Ga _0.12 As layer, 16 and 36 are AlAs _0.16 Sb _0.84 layer,
17 is undoped InAs layer, 18 is undoped
Al _0.5 Ga _0.5 As _0.12 Sb _0.88 layer, 19 is n ⁺ type Al _0.5 Ga _0.5
As _0.12 Sb _0.88 layer, 20 is a shot electrode, 21,
22 is an ohmic electrode, 37 is Al _0.5 Ga _0.5 As _0.12
Sb _0.88 layer, 38 is InAs layer, 39 and 40 are ohmic electrodes, 41 is P ⁺ type InAs substrate, 42 is P ^- type InAs
Collector layer, 43 is n ⁺ type InAs base layer, 44 is P type AlxGa _1-x AsySb _1-y (y = 0.067x + 0.09) layer,
45 is a P ⁺ type InAs cap layer.

Claims (1)

[Claims] 1 InAs and AlxGa _1-x AsySb _1-y (y=0.067x+
A semiconductor device characterized by using a heterojunction with 0.090). 2 Undoped In _0.53 Ga _0.47 on semi-insulating InP substrate
an As layer, an InxGa _1-x As multilayer buffer layer with a stepwise composition on the In _0.53 Ga _0.47 As layer, and an undoped AlxGa _1-x AsySb _1-y (y
=0.067x+0.09) layer, an undoped InAs layer on the AlxGa _1-x AsySb _1-y layer, and an undoped AlxGa _1-x AsySb _1-y (y=0.067x+0.09) layer on the InAs layer. , the n ⁺ type AlxGa 1- _x on the AlxGa _1-x AsySb _1-y layer
AsySb _1-y (y=0.067x+0.09), and the above n ⁺
The field effect transistor is characterized in that ohmic electrodes for the source and drain are provided in two separated regions of the type AlxGa _1-x AsySb _1-y layer, and a shot electrode for the gate is provided between these electrodes. A semiconductor device according to claim 1. 3 Undoped In _0.53 Ga _0.47 on semi-insulating InP substrate
an As layer, an InxGa _1-x As multilayer buffer layer with a stepwise composition on the In _0.53 Ga _0.47 As layer, and an undoped AlxGa _1-x AsySb _1-y (y
= 0.067x + 0.09) layer, and a single or multiple stack of InAs and AlxGa _1-x AsySb _1-y on the AlxGa _1-x AsySb _1-y layer, with ohmics on both sides of the stack. The semiconductor device according to claim 1, which is a semiconductor element provided with an electrode. 4 p - type InAs collector layer, n ⁺ on p ^type InAs substrate
type InAs base layer, p-type AlxGa _1-x on the base layer
2. The semiconductor device according to claim 1, wherein the semiconductor device is a bipolar heterojunction transistor having an AsySb _1-y (y=0.067x+0.09) emitter layer.