JP3094500B2 - Field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction field effect transistor.

[0002]

2. Description of the Related Art In _0.53 Ga lattice-matched to an InP substrate.
_0.47 As has a higher electron mobility and saturation velocity than GaAs. Is a semiconductor material suitable for field-effect transistor (FET) operating in 1GH _Z or more frequency bands, has been confirmed by the various structures of the FET.

[0003] In _0.52 Al _0.48 As is _converted to In _0.53 Ga _0.47.
Lattice matched with As, InP or In _0.53 Ga _0.47 As
It can be epitaxially grown on. Moreover, In _0.53 Ga
_{Since the} electron affinity is lower than _0.47 As, the N-type In
_0.52 Al _0.48 As and undoped In _0.53 Ga _0.47 As
Is bonded, a two-dimensional electron gas layer is formed near the bonding surface in In _0.53 Ga _0.47 As.

An FET using this two-dimensional electron gas layer as a current channel has been experimentally manufactured, and excellent performance has been confirmed. FIG. 3 shows a conventional example of a FET introduced in the Nikkei Microdevices November 1985 issue, page 61.
This will be described with reference to FIG.

An undoped In _0.52 Al is formed on a semi-insulating InP substrate 1 by molecular beam epitaxy (MBE).
_0.48 As buffer layer 2, undoped In _0.53 Ga _0.47 A
s current channel layer 3, undoped In _0.52 Al _0.48 As
Spacer layer 13, N-type Si-doped In _0.52 Al _0.48 As
A layer 14 and an undoped In _0.52 Al _0.48 As layer 15 are sequentially grown.

[0006] The InAlAs buffer layer 2 is made of semi-insulating In.
The diffusion of impurities from the P substrate 1 is prevented, and the electrical characteristics of the InGaAs current channel layer 3 are improved.

The In-doped InAlAs layer 14 is more In
The GaAs current channel layer 3 has a higher electron affinity.
Therefore, electrons move from the Si-doped InAlAs layer 14 to the InGaAs current channel layer 3 via the thin undoped InAlAs spacer layer 13 having a thickness of 20A. Thus, a two-dimensional electron gas layer 5 is formed near the heterojunction interface between the InGaAs current channel layer 3 and the InAlAs spacer layer 13.

[0008] Thin undoped InAlAs spacer layer 1
3 is for spatially separating the two-dimensional electron gas layer 5 and the ionized Si donor in the Si-doped InAlAs layer 14 to reduce electron Coulomb scattering and improve the mobility of the two-dimensional electron gas. It is.

The Schottky gate electrode 6 of Al is formed on the uppermost undoped InAlAs layer 15 and controls the current flowing between the source electrode 7 and the drain electrode 8. The transconductance g _m of the FET is 440ms / mm is obtained at room temperature, which is the ability to exceed the GaAsMESFET the same gate electrode length.

[0010]

The conventional FET is In _Y
The mixing ratio of Al _{1 -Y} As is Y = 0.52, and the Schottky barrier height of the Schottky junction with the gate electrode is 0.8 e.
V and low. When a positive gate bias is applied and the device is used in the enhancement mode, the gate leakage current becomes 10 A / c.
It is a problem that increases until m ² or more.

[0011] There Schottky barrier height than 0.8eV to solve this _{Al Z Ga 1-Z As (} 0 <Z ≦ 1)
May be used instead of InAlAs, but lattice matching cannot be performed because the lattice constant is different. Dislocation defects occur at the heterojunction interface due to the difference in lattice constant, and F
ET characteristics change and instability occur, and this is a new problem.

[0012]

SUMMARY OF THE INVENTION The feature of the present invention is that InP
And the InGaAs channel layer and the AlAs-InAs superlattice layer is lattice-matched to InP on one major surface of the substrate are sequentially formed, a gate electrode is formed on the AlAs-InAs superlattice layer, the AlAs-INAS superlattice layer Ratio t ₁ / t ₂ of thickness t _{1 of} AlAs thin film to thickness t _{2 of} InAs thin film
Field effect Trang but which gradually increases from the lower toward the upper layer
A transistor, on the AlAs-InAs superlattice layer,
N ⁺ type GaAs contact layer doped with silicon
And a source electrode on the N ⁺ -type GaAs contact layer.
In a field effect transistor in which a pole and a drain electrode are formed . Another feature of the present invention is that one main surface of the InP substrate is
InGaAs channel layer lattice-matched with InP and Al
An As-InAs superlattice layer is sequentially formed, and the AlA
A gate electrode is formed on the s-InAs superlattice layer, and Al
The as-InAs of AlAs thin superlattice layer thickness t ₁ and I
The ratio t ₁ / t ₂ with respect to the thickness t _{2 of the} nAs thin film is from the lower layer to the upper layer.
Field-effect transistors that gradually increase
As a result, a recess is formed in the AlAs-InAs superlattice layer.
Forming the gate electrode on the bottom of the recess.
In field effect transistors.

[0013]

The compound semiconductor thin layers having different lattice constants are formed by molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD). The thickness of each layer is stopped within the critical thickness at which dislocation defects begin to occur. It has been clarified that by alternately stacking the layers, epitaxial growth can be performed without generating dislocation defects.

InAs and AlA having a lattice constant difference of 7%
By limiting the thickness of each layer to 50 A or less even with a thin layer of s, it is possible to stack several thousand A without generating dislocation defects. The In composition Y of In _Y Al _1-Y As lattice-matched to In _0.53 Ga _0.47 As is Y = 0.52.
However, a compound semiconductor having the same properties as In _Y Al _1-Y As can be made of a superlattice in which thin layers of InAs and AlAs are alternately stacked.

That is, the thickness t ₁ of the thin layer of InAs and Al
The ratio t ₁ / t ₂ to the thickness t ₂ of the thin As layer is 0.52 /
0.48 ≒ 1.08. A superlattice in which these are alternately laminated becomes equivalent to In _0.52 Al _0.48 As, and the average lattice constant can be considered to be equal to the lattice constant of InP.

Therefore, when this superlattice is grown on the In _0.53 Ga _0.47 As layer serving as the current channel layer of the FET, it is possible to prevent the generation of dislocation defects due to the difference in lattice constant at the interface between these semiconductor heterojunctions.

Then, gradually, t ₁ /
Reducing t ₂ (reducing the proportion of InAs thin film) increases the average bandgap of the superlattice. Thus, the Schottky junction barrier with the metal gate electrode is changed to AlAs.
≒ 1.2 eV.

[0018]

FIG. 1A shows a technique related to the present invention.
1 and a partially enlarged cross-sectional view of FIG.

On a Fe-doped semi-insulating InP substrate 1 having a crystal plane of (100), an undoped InAlAs buffer layer 2 having a thickness of 5000 A and an undoped InGaAs current channel layer 3 having a thickness of 1000 A were sequentially grown by MBE.

InAlAs buffer layer 2 and InGa
The InAs composition ratio of the As current channel layer 3 was set to 0.52 and 0.53, respectively, and lattice matching was performed with the semi-insulating InP substrate 1 by matching the lattice constant.

The source electrode 7 and the drain electrode 8 are made of Au
A superlattice 4 composed of a Ge—Ni alloy and having a plurality of thin layers of InAs and AlAs doped with Si on an InGaAs current channel layer 3 is disposed with a spacing of InGaAs.
An electrically good ohmic contact is formed with the s current channel layer 3.

A gate electrode 6 made of Al is formed on the superlattice 4.
Is formed, and the current between the source electrode 7 and the drain electrode 8 is controlled by controlling the electron concentration of the two-dimensional electron gas layer 5 formed in the InGaAs current channel layer 3 via the superlattice 4.

As shown in FIG. 1B, the superlattice layer 4
2 × Si by MBE on nGaAs channel layer 3
10 ¹⁸ cm ^-3 doped InAs layer 9 and AlAs layer 10
And were alternately epitaxially grown.

The ratio t ₁ / t ₂ of the thickness t ₂ of the first AlAs layer 10 in contact with the InGaAs current channel layer 3 to the thickness t ₁ of the InAs layer 9 in contact with the AlAs layer 10 is I
t ₁ / t ₂ = 0.52 so that the lattice constant of the nGaAs current channel layer 3 (In composition 0.53) matches the average lattice constant of the AlAs layer 10 and the InAs layer 9.
/0.48≒1.08.

Further, the growth was controlled so that t ₁ and t ₂ were 52 A and 48 A, respectively, which were equal to or less than the critical film thickness so as not to generate dislocation defects at the respective heterojunction interfaces.

Hereinafter, the AlAs layer 10 and the InAs layer 9 are
The sum of the film thicknesses of two adjacent layers is about 100 A, and gradually decreases as t ₁ / t ₂ becomes higher, and finally t ₁ / t ₂ = 0.064 at the uppermost portion in contact with the gate electrode 5. .
Actually, the AlAs layer 10 and the InAs layer 9
Each layer is epitaxially grown, and the thickness of the superlattice 4 is set to 400
A.

In the InGaAs FET shown in FIG.
The barrier height of the Schottky gate junction between the gate electrode 6 and the superlattice layer 9 is about 1 eV. The leak current of the positively biased gate electrode was significantly reduced as compared with the case where In _0.52 Al _0.48 As was used instead of the superlattice 4.

For example, the gate leakage current when a gate bias voltage of +0.5 V is applied is about 10 ^-1 to 10 ^-2 A / cm ^2, which is 1/100 or less of that when In _0.52 Al _0.48 As is used. The noise figure in the high frequency band of the FET using the two-dimensional electron gas of InGaAs as the current channel was significantly reduced.

Since the barrier height of the Schottky junction has been increased, the reverse breakdown voltage of the gate electrode has also been improved, and it has become possible to put it to practical use as a high-output device for a high frequency band.

Next, an embodiment of the present invention will be described with reference to FIG.

In this embodiment, Si is superimposed on the superlattice layer 4 of FIG.
Was added to the N ⁺ -type GaAs contact layer 11 which was heavily doped. The contact resistance between the source electrode 7 and the drain electrode 8 and the semiconductor layer is reduced. Further, a recess 12 is formed and a gate electrode 6 is provided on the superlattice layer 4 to reduce the series resistance between the gate electrode 6 and the source electrode 7.

After the superlattice layer 4 is grown in the same manner as in FIG . 1 , the thickness 2 doped with 5 × 10 ¹⁸ cm ⁻³ of Si by MBE is applied.
A 00A N ⁺ type GaAs contact layer 11 is grown.
After that, the recess 12 is formed by photolithography.

[0033] Also in FET of this embodiment, reduced to about 1/100 leakage current of the conventional Similarly gate electrode and FIG. 1, is further reduced series resistance between the source electrode and the gate electrode, high-frequency characteristics even Improved.

[0034]

As described above, the effective lattice constant of the FET in contact with the In _0.53 Ga _0.47 As current channel layer is the same, and the Schottky junction barrier with the gate electrode becomes large. InAs and AlAs thin layers are alternately stacked. A grid was formed.

[0035] Dislocation defects do not occur at the heterojunction interface between the InGaAs current channel layer and the superlattice layer, and the leakage current of the gate electrode of the FET can be significantly reduced.

As a result, it has become possible to design and manufacture a field effect transistor exhibiting excellent electrical characteristics in a high frequency band inherent to InGaAs.

[Brief description of the drawings]

FIG. 1A is a cross-sectional view showing a technique related to the present invention. (B) is a partial sectional view showing a superlattice layer.

FIG. 2 is a sectional view showing an embodiment of the present invention.

FIG. 3 is a cross-sectional view of a conventional FET.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semi-insulating InP substrate 2 InAlAs buffer layer 3 InGaAs channel layer 4 Super lattice layer 5 Two-dimensional electron gas layer 6 Gate electrode 7 Source electrode 8 Drain electrode 9 InAs layer 10 AlAs layer 11 N ⁺ type GaAs contact layer 12 Recess 13 Undoped InAlAs spacer layer 14 N-type InAlAs layer 15 Undoped InAlAs layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/778 H01L 21/338 H01L 29/205 H01L 29/812

Claims (2)

(57) [Claims] 1. A and the InGaAs channel layer and the AlAs-InAs superlattice layer is lattice-matched to InP on one principal surface of the InP substrate are sequentially formed, a gate electrode is formed on the AlAs-InAs superlattice layer, AlAs A field effect transistor wherein the ratio t ₁ / t ₂ of the thickness t ₁ of the AlAs thin film of the InAs superlattice layer to the thickness t _{2 of the} InAs thin film gradually increases from the lower layer to the upper layer ;
N ⁺ -type Ga doped with silicon on InAs superlattice layer
An As contact layer is formed, and the N ⁺ -type GaAs capacitor is formed.
A source electrode and a drain electrode are formed on the tact layer.
Field-effect transistor. 2. An InP substrate and a lattice alignment on one main surface of an InP substrate.
Combined InGaAs channel layer and AlAs-InAs super
Lattice layers are sequentially formed, and the AlAs-InAs superlattice is formed.
A gate electrode is formed on the daughter layer, and the AlAs-InAs
Thickness t ₁ of AlAs thin film of lattice layer and thickness of InAs thin film
gradually increasing toward the upper layer ratio t ₁ / t ₂ and t ₂ from the lower layer
A field-effect transistor, wherein the AlAs-
A recess is formed in the InAs superlattice layer, and a bottom of the recess is formed.
A field-effect transistor having the gate electrode formed on a portion thereof .