JPH04343438A - Field effect transistor - Google Patents

Abstract

PURPOSE:To raise a Schottky junction barrier to a metal gate electrode by so alternately laminating an AlAs thin film and an InAs thin film that the former becomes gradually thin and the latter becomes gradually thick. CONSTITUTION:A lattice-matching InGaAs current channel layer 3 is epitaxially grown on a semi-insulating InP substrate 1. A superlattice layer 4 in which InAs thin films 9 each having a thickness t<1> and AlAs films 10 each having a thickness t2 are so alternately laminated that a thickness ratio t<1>/t<2> is reduced toward an upper layer, is grown. A Schottky junction barrier is raised, and a withstand voltage of a gate electrode 6 is improved. Since no crystalline defect is generated in a hetero junction boundary, a gate leakage current can be remarkably reduced.

Description

[Detailed description of the invention]

0001

FIELD OF THE INVENTION This invention relates to heterojunction field effect transistors.

0002

[Prior Art] In0.53 lattice-matched to an InP substrate
Ga0.47As has electron mobility and saturation velocity of G
larger than aAs. It has been confirmed by using FETs of various structures that it is a semiconductor material suitable for field effect transistors (FETs) that operate in high frequency bands of 1 GHz or higher.

In0.52Al0.48As is In0.52Al0.48As.
lattice matched with 53Ga0.47As, InP or In
It can be epitaxially grown on 0.53Ga0.47As. Moreover, since the electron affinity is smaller than that of In0.53Ga0.47As, N-type In0.52Al0.48A
When s and undoped In0.53Ga0.47As are bonded, a two-dimensional electron gas layer is formed near the bonding surface within the In0.53Ga0.47As.

An FET using this two-dimensional electron gas layer as a current channel has been prototyped and its excellent performance has been confirmed. As a conventional example, an FET introduced on page 61 of the November 1985 issue of Nikkei Microdevices will be explained with reference to FIG.

Undoped In0.52 was deposited on a semi-insulating InP substrate 1 by molecular beam epitaxial growth (MBE).
Al0.48As buffer layer 2, undoped In0.5
3Ga0.47As current channel layer 3, undoped In
A 0.52Al0.48As spacer layer 13, an N-type Si-doped In0.52Al0.48As layer 14, and an undoped In0.52Al0.48As layer 15 are sequentially grown.

The InAlAs buffer layer 2 is made of semi-insulating In
This prevents diffusion of impurities from the P substrate 1 and improves the electrical characteristics of the InGaAs current channel layer 3.

[0007] Rather than the Si-doped InAlAs layer 14,
The GaAs current channel layer 3 has a higher electron affinity. Therefore, electrons move from the Si-doped InAlAs layer 14 to the InGaAs current channel layer 3 via the thin undoped InAlAs spacer layer 13 with a thickness of 20 Å. Thus, a two-dimensional electron gas layer 5 is formed near the heterojunction interface between the InGaAs current channel layer 3 and the InAlAs spacer layer 13.

Thin undoped InAlAs spacer layer 1
3 is for spatially separating the two-dimensional electron gas layer 5 and the ionized Si donor in the Si-doped InAlAs layer 14 to reduce Coulomb scattering of electrons and improve the mobility of the two-dimensional electron gas. It is.

An Al Schottky gate electrode 6 is formed on the uppermost undoped InAlAs layer 15 and controls the current flowing between the source electrode 7 and the drain electrode 8. This FET has a transconductance gm of 440 ms/mm at room temperature, which is superior to a GaAs MESFET with the same gate electrode length.

0010

[Problem to be solved by the invention] The conventional FET is InY
The mixing ratio of Al1-YAs is Y=0.52, and the Schottky barrier height of the Schottky junction with the gate electrode is 0.
．． It is as low as 8eV. When used in enhancement mode with a positive gate bias applied, the gate leakage current is 10
An increase to A/cm2 or higher becomes a problem.

In order to solve this problem, AlZ Ga1-Z As (0<Z
≦1) in place of InAlAs, but since the lattice constants are different, lattice matching cannot be achieved. Dislocation defects occur due to the difference in lattice constants at the heterojunction interface, causing characteristic fluctuations and instability of the FET, posing a new problem.

0012

Means for Solving the Problems In the field effect transistor of the present invention, an InGaAs channel layer lattice-matched to InP and an AlAs-InAs superlattice layer are successively formed on one main surface of an InP substrate, and the AlAs-InAs A gate electrode is formed on the superlattice layer, and a source electrode and a drain electrode are formed on the InGaAs channel layer. Ratio between the thickness t1 of the AlAs thin film and the thickness t2 of the InAs thin film of the AlAs-InAs superlattice layer: t1 /t2
gradually decreases from the bottom to the top.

[0013]

[Operation] Thin layers of compound semiconductors having different lattice constants are formed by molecular beam epitaxial growth (MBE) or metal organic chemical vapor deposition (MOCVD). The thickness of each layer is kept within the critical thickness at which dislocation defects begin to occur. It has been revealed that by alternately stacking each layer, epitaxial growth can be achieved without generating dislocation defects.

[0014] InAs and AlA have a 7% difference in lattice constant.
By limiting the thickness of each layer to 50 Å or less, even if the layer is thin with s, it is possible to stack several 1000 Å without generating dislocation defects. Also In0.53Ga0.47As
The In composition Y of InY Al1-Y As is lattice matched to
is Y=0.52, but this InY Al1-Y A
InAs and AlAs are compound semiconductors with the same properties as s.
It can be made from a superlattice made of alternating thin layers of .

That is, the thickness t1 of the InAs thin layer and A
The ratio t1 /t2 to the thickness t2 of the thin layer of lAs is 0.
52/0.48≒1.08. A superlattice obtained by laminating these layers alternately is equivalent to In0.52Al0.48As, and the average lattice constant can be considered to match that of InP.

Therefore, if this superlattice is grown on the In0.53Ga0.47As layer which becomes the current channel layer of the FET, it is possible to prevent the generation of dislocation defects due to the difference in lattice constant at the interface of these semiconductor heterojunctions.

[0017] Then gradually t1 in this superlattice
By reducing /t2 (reducing the proportion of InAs thin film), the average bandgap of the superlattice increases. In this way, the Schottky junction barrier with the metal gate electrode is
It can be easily increased to around ≒1.2 eV of As.

[0018]

[Example] Regarding the first example of the present invention, FIG. 1(a)
This will be explained with reference to a cross-sectional view of FIG. 1 and a partially enlarged cross-sectional view of FIG. 1(b).

An undoped InAlAs buffer layer 2 with a thickness of 5000 Å and an undoped InGaAs current channel layer 3 with a thickness of 1000 Å were successively grown on an Fe-doped semi-insulating InP substrate 1 having a (100) crystal plane by MBE.

InAlAs buffer layer 2 and InGa
The InAs composition ratio of the As current channel layer 3 is 0.
．． 52 and 0.53, and the lattice constants were matched to the semi-insulating InP substrate 1 for lattice matching.

The source electrode 7 and the drain electrode 8 are made of Au.
It is made of a Ge/Ni alloy, and is arranged across a superlattice 4 in which a plurality of Si-doped InAs and AlAs thin layers are laminated on an InGaAs current channel layer 3.
A good electrical ohmic contact is formed with the s current channel layer 3.

A gate electrode 6 made of Al is on the superlattice 4.
is formed, and controls the electron concentration of the two-dimensional electron gas layer 5 formed in the InGaAs current channel layer 3 via the superlattice 4, thereby controlling the current between the source electrode 7 and the drain electrode 8.

As shown in FIG. 1(b), the superlattice layer 4 has an I
Si is deposited 2x on the nGaAs channel layer 3 by MBE.
InAs layers 9 doped with 1018 cm-3 and AlAs layers 10 were epitaxially grown alternately.

Thickness t2 of the first AlAs layer 10 in contact with the InGaAs current channel layer 3 and the AlAs layer 10
The ratio t1 /t2 of the thickness t1 of the InAs layer 9 in contact with
is an InGaAs current channel layer 3 (In composition 0.5
3) and the lattice constant of this AlAs layer 10 and InAs
t1 /t2 so that the average lattice constant of layer 9 matches
=0.52/0.48≒1.08 as close as possible.

Further, the growth was controlled so that t1 and t2 were 52A and 48A, respectively, below the critical film thickness so as not to generate dislocation defects at the respective heterojunction interfaces.

Hereinafter, the AlAs layer 10 and the InAs layer 9 are as follows.
The sum of the thicknesses of two adjacent layers is approximately 100A, and t1 /t2
gradually becomes smaller as it goes to the upper layer, and finally at the top where it contacts the gate electrode 5, t1 /t2 = 0.064
And so. Actually, the number of AlAs layers 10 and InAs layers 9 is 4 each.
The thickness of the superlattice 4 is 400 mm by epitaxial growth layer by layer.
I gave it an A.

In the InGaAsFET shown in FIG. 1(a), Al
The barrier height of the Schottky gate junction between the gate electrode 6 and the superlattice layer 9 is approximately 1 eV. The leakage current of the positively biased gate electrode was significantly reduced compared to the case where In0.52Al0.48As was used instead of the superlattice 4.

For example, the gate leakage current when applying a gate bias voltage of +0.5V is 10-1 to 10-2 A/cm2.
It was about 1/100 or less of that when In0.52Al0.48As was used. The noise figure in the high frequency band of an FET using InGaAs two-dimensional electron gas as a current channel has been significantly reduced.

Since the barrier height of the Schottky junction is increased, the reverse breakdown voltage of the gate electrode is also improved, making it possible to put it to practical use as a high-output device for high frequency bands.

Next, a second embodiment of the present invention will be described with reference to FIG.

In this embodiment, an N+ type GaAs contact layer 11 heavily doped with Si is added on top of the superlattice layer 4 of the first embodiment. The contact resistance between the source electrode 7 and drain electrode 8 and the semiconductor layer is reduced. Further, a recess 12 was formed and a gate electrode 6 was provided on the superlattice layer 4 to reduce the series resistance between the gate electrode 6 and the source electrode 7.

After growing the superlattice layer 4 in the same manner as in the first embodiment, an N+ type GaAs contact layer 1 doped with 5×10 18 cm −3 of Si by MBE and having a thickness of 200 Å is grown.
Grow 1. Thereafter, a recess 12 is formed by photolithography.

In the FET of this embodiment as well, the leakage current of the gate electrode is 1/100 that of the conventional one, as in the first embodiment.
Furthermore, the series resistance between the source electrode and the gate electrode was reduced, and the high frequency characteristics were further improved.

[0034]

[Effect of the invention] In0.53Ga0.47As for FET
The effective lattice constants match on the surface in contact with the current channel layer, and the Schottky junction barrier with the gate electrode increases
A superlattice was formed by laminating thin layers of nAs and AlAs alternately.

[0035] Dislocation defects are not generated at the heterojunction interface between the InGaAs current channel layer and the superlattice layer, and leakage current at the gate electrode of the FET can be significantly reduced.

As a result, it has become possible to design and manufacture a field effect transistor that exhibits the excellent electrical characteristics inherent to InGaAs in a high frequency band.

[Brief explanation of drawings]

FIG. 1(a) is a sectional view showing a first embodiment of the present invention. (b) is a partial cross-sectional view showing a superlattice layer.

FIG. 2 is a sectional view showing a second embodiment of the invention.

FIG. 3 is a cross-sectional view of a FET according to the prior art.

[Explanation of symbols]

1 Semi-insulating InP substrate 2 InAlAs buffer layer 3 InGaAs channel layer 4 Superlattice layer 5 Two-dimensional electron gas layer 6 Gate electrode 7 Source electrode 8 Drain electrode 9 InAs layer 10 AlAs layer 11 N+ type GaAs contact layer 12
Recess 13 Undoped InAlAs spacer layer 14
N-type InAlAs layer

Claims (3)

[Claims] Claim 1: An InGaAs channel layer and AlAs-InAs lattice-matched to InP are formed on one main surface of an InP substrate.
a superlattice layer, a gate electrode is formed on the AlAs-InAs superlattice layer, and a source electrode and a drain electrode are formed on the InGaAs channel layer. [Claim 2] AlA of AlAs-InAs superlattice layer
2. The field effect transistor according to claim 1, wherein the ratio t1/t2 of the thickness t1 of the InAs thin film to the thickness t2 of the InAs thin film gradually decreases from the lower layer to the upper layer. 3. The field effect transistor according to claim 1, wherein at least one of the AlAs thin film and the InAs thin film is doped with an impurity.