JPH023937A - Field effect transistor - Google Patents

Abstract

PURPOSE:To increase barrier height and improve fm and gm by using InAlGaAs having intermediate lattice constants between a barrier layer and a channel layer, as a buffer layer. CONSTITUTION:The title device is an field effect transistor having a laminated body, a gate electrode 6, a drain electrode 10 and a source electrode 9 formed on the laminated body. The laminated body is constituted by epitaxially growing the following in order; a buffer layer 2, a channel layer 3 and a barrier layer 4 (or carrier supplying layer). The buffer layer 2 is composed of undoped or P-type impurity doped InxAlyGa1-x-yAs (0<y<1-x), and sufficiently thickly stacked until lattice deformation is relieved. The channel layer 3 is composed of undoped or N-type impurity doped InzGa1-zAs (0<z<=1), and is so thin that miss-fit transition does not occur. The barrier layer 4 is composed of InuAlvGa1-u-vAs (0<u+v<=1, 0<=u<y) which is not doped or doped partially or wholly with N-type impurity, and is so thin that miss-fit transition does not occur. A relation u<x<z is to be maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to field effect transistors, and more particularly to field effect transistors that are fast and suitable for integrated circuits.

[Prior art]

2. Description of the Related Art Field-effect transistors using AlGaAs/InGaAs/GaAs heterojunctions have been known. FIG. 4 shows a sectional view of a main part of an example, and FIG. 5 is an energy band diagram of the field effect transistor shown in FIG.

As shown in FIG. 4, the conventional field effect transistor has an undoped Ga layer formed on a semi-insulating GaAs substrate 101.
Buffer layer 102 made of As. Undoped In, 2
A channel layer 103 made of Ga,..., As, a barrier layer 104 made of undoped A1L4sGaa, 55As.
A laminated body is formed by successively epitaxially growing a cap layer 105 made of undoped GaAS. A gate electrode 106 made of a metal deposited and processed into a stripe shape is provided on the stacked body, and a highly doped n-type source region 107 formed to a depth reaching at least the channel layer 103 is provided on both sides of the gate electrode 106. A source electrode 109 and a drain electrode 1 each connected to the drain region 108.
10 are provided. Then, an MIS field effect transistor (hereinafter referred to as MIS) has a structure in which two-dimensional electron gas is induced in the channel layer by a voltage applied to the gate electrode 106.
SFET).

MI 5FET using this AlGaAs/InGaAs/GaAs heterojunction is
It has several advantages over MISFETs using As heterojunctions.

The first is that the conduction band discontinuity of the AlGaAs/InGaAs heterojunction is larger than that of AlGaAs/GaAs, so that the gate league current through which electrons flow from the channel layer 103 to the gate electrode 106 can be reduced.

The second is InGaAs, which has a faster electron velocity than GaAs.
By using this in the channel, the cutoff frequency ft, mutual conductance g9, etc. can be improved.

The third reason is that the conduction band discontinuity between the buffer layer and the channel layer strengthens carrier confinement and suppresses the short channel effect.

These advantages are due to the fact that InG with larger InAs concentration
It can be further increased by using aAs in the channel [K, Maezawa et al.
Jpn Appl.

Phys, 26 (1987), L74. reference].

On the other hand, since InGaAs has a different lattice constant from GaAs, there are strict restrictions on the composition and film thickness of InGaAs in order to have good crystallinity and stack it without causing misfit dislocations [for example, T
, G. Andarsson et al., Ap.
pl, Phys, Lett.

51 (1987), 752. reference]. For example, in the above example (In, 2Ga, . . . As channel), the film thickness needs to be approximately 150 Å or less;
In order to increase the As concentration, the film thickness must be further reduced.

[Problem to be solved by the invention]

However, in the conventional technique, as the film thickness is reduced, the quantum effect becomes stronger.

The energy of the ground level increases, substantially canceling out the effect of increasing the InAsfi degree, and the characteristics of the field effect transistor (FET) deteriorate. In other words, the prior art had a problem in that it was not possible to use InAs at a very high concentration in the channel, which limited its effectiveness.

Here, MISFETs with undoped Al and GaAs barrier layers have been explained, but n-type AlG
The so-called HEM T (High
E 1ectron Mob, tHty engineering ransi
The problem is almost the same in the stor) structure.

The present invention has been made to solve the above problems.

The object of the present invention is to obtain AlGaAs/InGaAs/GaA
In s-structure world-effect transistors, large InG
The object of the present invention is to enable the use of an aAs channel layer and provide a field effect transistor with higher performance.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

In order to achieve the above object, the present invention provides undoped or p-type impurity-doped In,
AI Gai, -x-yAs (0<y< I
), stacked sufficiently thickly until the lattice strain is relaxed, and undoped or n-type impurity-doped InzGa, -tAs (0 < z < = 1
), with a channel layer thin enough to prevent misfit dislocations, and InLIAlvGa, -u-yA, which is undoped or partially or entirely doped with n-type impurities.
s (0<= u +v (= 1, O<=
u < y ), and a field effect transistor has a stacked structure in which barrier layers (or carrier supply layers) thin enough to prevent misfit dislocations are sequentially grown epitaxially, and a gate, drain, and source electrode on the stacked structure. The most important feature is that u < x < z.

Moreover, InxAl is formed between the buffer layer and the channel layer.
yGaltGax-54As (0(= t <= 1
[Operation] According to the above-mentioned means, AlGaAs /InGaAs/
In a GaAs structure field effect transistor, a large InGaAs channel layer can be used by using a semiconductor having a lattice constant between the lattice constant of the channel layer semiconductor and the barrier layer semiconductor as the buffer layer. This makes it possible to provide a field effect transistor suitable for higher performance integrated circuits such as high speed.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

Note that throughout the description of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Example ■]

FIG. 1 shows an example of the summer AlGaAs/InGa according to the present invention.
FIG. 1 is a cross-sectional view of a main part for explaining a schematic configuration of an As/GaAs structure field effect transistor.

AlGaAs/InGaAs/GaAs of this example
As shown in Figure 1, the structural field effect transistor has the following structure:
Undoped InLiGa is deposited on a semi-insulating GaAs substrate 1.
2. Buffer layer made of t, As. Undoped In, 4
0a, channel layer 3 made of sAs, undoped A1□
Barrier layer 4 made of 5 Gaasjs, undoped Ins
, *Gas, , As, for example, M
B E (Molecular BeamE pita)
Stacked body I grown epitaxially by the xy) method
is provided. A gate electrode 6 made of metal (for example, WSix) is deposited and processed into a stripe shape on this stacked body I.

Source regions 7 made of highly doped n-type regions are formed on both sides of the gate electrode 6 to a depth reaching at least the channel layer 3 (for example, by Si ion implantation and annealing).
and a drain region 8 are formed, and a source electrode 9 and a drain electrode 10 made of ohmic electrodes are further provided thereon.

Here, although the buffer layer 2 has a different lattice constant from the semi-insulating GaAs substrate 1, it is laminated sufficiently thickly (for example, 1 μm) until the lattice strain is relaxed. At this time, misfit dislocations 11 occur near the interface between the buffer layer 2 and the semi-insulating GaAs substrate 1, but this interface does not directly affect the FET operation.

By the way, in this embodiment, Int4G is used in the channel layer 3.
As and aAs are used, but the difference in lattice constant from GaAs is about 3%, so in the conventional technology using GaAs as the buffer layer 2, misfit dislocations will occur unless the film thickness is set to 50 Å or less.

Therefore, the effect of using InGaAs with a high InAs concentration for the channel does not appear, and the FET characteristics do not improve.

On the other hand, in this embodiment, the buffer layer 2 is made of In.
, 2Ga, , As, the difference in lattice constant is about 1.5%, and the thickness of the channel layer 3 can be made sufficiently thick to, for example, 150 layers.

At this time, the channel layer 3 is distorted so that its in-plane lattice constant matches that of the buffer layer 2. Therefore, the difference in lattice constant between the barrier layer 4, the channel layer 3, and the buffer layer 2 is about -1.5%, and the thickness can also be about 150 layers.

Furthermore, if this embodiment is used, large InA
Since InGaAs with a concentration of
The effects such as increasing t g y) and suppressing the short channel effect are significant.

9 In this embodiment, InL2Ga is used as the cap layer 5.
,,,Although an example in which As is provided has been described, it may be omitted.Also, when GaAs is used for the cap layer 5, the combined thickness of the cap layer 5 and barrier layer 4 is the thickness at which misfit dislocation occurs. It has to be thinner than it is. In this example, metal is used for the gate electrode 6, but if a suitable semiconductor is used, the threshold value can be set to a desired value.

[Example ■]

FIG. 2 shows AlGaAs/InGa of Example ① of the present invention.
FIG. 1 is a cross-sectional view of a main part for explaining a schematic configuration of an As/GaAs structure field effect transistor.

The difference between the AlGaAs/InGaAs/GaAs structure field effect transistor of this embodiment (2) and that of the above-mentioned embodiment I is that it is undoped ^1. ,4. The barrier layer 4 made of Ga□, As is replaced with undoped Al@, 3Ga@, aGas.
Spacer layer 12 made of 7A8, n-Alm, 3Ga
The electron (carrier) supply layer 13 is made of @, 7As, and has a so-called HEMT structure. Also,
The cap layer 14 also has n
-In, . . . Ga, . . . As.

15 is a gate electrode.

In this case as well, since the conduction band discontinuity of AlGaAs/InGaAs can be made larger by about 0.2 eV than in the conventional technology,
The concentration of two-dimensional electron gas can be increased and excellent FET performance can be obtained. Of course, the electron velocity in the channel layer also increases, and fur grn also increases. This also applies to a structure in which an electron supply layer is provided between a buffer layer and a channel layer.

In addition, in this embodiment (2), the n
The source region 7 and drain region 8 of the region may be omitted.

[Example ■]

FIG. 3 shows AlGaAs/InGa of Example ① of the present invention.
FIG. 1 is a cross-sectional view of a main part for explaining a schematic configuration of an As/GaAs structure field effect transistor.

The AlGaAs/InGaAs/GaAs structure field effect transistor of Example 2 is composed of the buffer layer 2 made of undoped In, Ga, . . . As of Example I shown in FIG. a A
between the channel layer 3 consisting of n-Al1,3Gas
, 7AS is provided.

By adopting such a structure, the parasitic resistance of the source electrode 9 and the drain electrode 10 can be reduced and the threshold voltage can be adjusted. In this case, the n region formed by ion implantation in the source region 7 and drain region 8 of the source and drain may be omitted.

[Example ■]

The AlGaAs/InGaAs/GaAs structure field effect transistor of this embodiment (2) has a buffer layer 2 made of undoped In, zGas, and As of the embodiment (2) shown in FIG. 2, and undoped In@, +Ga@, @A'. Between the channel layers 3 consisting of
. Electron (carrier) supply layer 16 made of Ga, ..., As
It has been established.

By adopting such a structure, it is possible to obtain an effect similar to that of the above-mentioned Example ②6.Moreover, by providing an undoped spacer layer on the channel side of the electron (carrier) supply layer 16, mobility can be increased. be able to.

In the above-described embodiment, in the case of the HEMT structure, it may be necessary to make the barrier layer thicker in order to match the threshold voltage. In this case, the InAs concentration in the buffer layer is made smaller than the average value (in this case, the thickness of the channel layer is made smaller), but a mixed crystal containing a small amount of InAs may be used in the barrier layer.

The effects of the present invention are also significant in many other variations, such as a structure in which the InGaAs layer of the channel is n-type and the other is undoped.

Note that in the present invention, the buffer layer is made of InGaAs (InGaAs), which has a lattice constant closer to that of the GaAs substrate than the channel layer.
Direct InA
Compared to the case where a channel layer with a large s composition is laminated thickly.

Another advantage is that the crystallinity can be easily improved.

In addition, intermediate location, Institute of Electronics, Information and Communication Engineers technical research report vol.
87. (1987), ED87-123. p85.
As described in , when X is around 0.4, the half-width of X-rays becomes very large, and crystal growth becomes slow, such as layered growth becoming impossible, so this effect is practically outstanding. By providing a superlattice buffer layer or a compositionally graded layer near the substrate, crystallinity can be further improved by reducing dislocation density.

Further, in the above embodiment, the buffer layer is made of InGaAs.
However, if InAlGaAs is used, even with the same lattice constant, the conduction band discontinuity and band gap will become larger, so there are advantages such as the ability to further suppress the short channel effect.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

As described above, according to the present invention, the buffer layer is made of In having a lattice constant between that of the barrier layer and the channel layer.
Since AlGaAs is used, it is possible to use a channel layer and a barrier layer with significantly different lattice constants of 3 to 4%.
Remarkable effects such as an increase in barrier hydride and an improvement in fjg can be obtained.

[Brief explanation of the drawing]

FIG. 1 shows AlGaAs/InGa of Example ① of the present invention.
FIG. 2 is a sectional view of a main part for explaining the schematic structure of an As/GaAs structure field effect transistor.
FIG. 1 is a cross-sectional view of a main part for explaining a schematic configuration of an As/GaAs structure field effect transistor. FIG. 3 shows AlGaAs/InGa of Example ① of the present invention.
FIG. 4 is a cross-sectional view of a main part for explaining the schematic structure of an As/GaAs structure field effect transistor. FIG. 4 is a cross-sectional view of a main part for explaining the problems of a conventional field effect transistor. , is an energy band diagram of the field effect transistor of FIG. 4; In the figure, 1... semi-insulating GaAs substrate, 2... buffer layer, 3... channel layer, 4... barrier layer, 5...
...Cap layer, 6,15...Gate electrode, 7...
Source n゛ area. 8...Drain n' region, 9...Source electrode, 10
...Drain electrode, 11...Misfit dislocation, 1
2... Spacer layer, 13.16... Electron (carrier) supply layer, 14... Cap layer.

Claims (2)

[Claims] (1) In_xAl_yGa_1_-_x_- doped with undoped or p-type impurities on a GaAs substrate
A buffer layer made of _yAs (0<y<1-x) stacked sufficiently thickly until the lattice strain is relaxed, and In_zGa_1_-_z undoped or doped with n-type impurities.
A channel layer made of As (0<z<=1) and thin enough to prevent misfit dislocations, and In_uAl that is undoped or partially or entirely doped with n-type impurities.
_vGa_1_−_u_−_vAs(0<=u+v<=
1, 0 <= u < y), and a layered structure in which barrier layers (or carrier supply layers) thin enough to prevent misfit dislocations are sequentially grown epitaxially, and gate, drain, and source electrodes are formed on the layered structure. A field effect transistor characterized in that u<x<z. (2) In_sA between the buffer layer and the channel layer
l_tGa_1_-_s_-_tAs(0<=t<=1
-s, 0<=s<z), and includes an electron supply layer partially or entirely doped with n-type impurities. effect type transistor.