JPS61171170A - Semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit gate leakage current by a method wherein an undoped semiconductor layer is inserted between a doped semiconductor and a gate metal forming a Schottky junction. CONSTITUTION:A GaAs layer 11 not doped with impurities on purpose is grown on a semi-insulation GaAs substrate 10, and an undoped AlxGa1-xAs (x-0.35) layer 12 is grown. Further, an N-type AlyGa1-yAs (0<y<=0.25) layer 13 containing Si in donor level is grown, and an N-type AlzGa1-zAs (0<=z<=1.0) layer 14 containing Si is formed. Next, an N-type GaAs layer 15 containing Si is formed. After crystal growth, source-drain electrodes 21, 22 are formed, and the N-GaAs layer 15 is selectively etched with CCl2F2/He mixed gas, thus forming a gate electrode 20. Au/Pt/Ti is used as the gate metal, and Au/Ni/Au- Ge is used as the source-drain metal. This process can yield the good Schottky gate structure close to the MIS structure.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device having a Schottky junction gate structure, and particularly to a structure suitable for reducing gate leakage current.

[Background of the invention]

Field-effect transistors (FETs) using compound semiconductors, mainly GaAs, have an interface state of about 10"as-" at the interface between the insulator and the compound semiconductor, so
The insulated gate type FET (MISFET) had the disadvantage of not being stable. Therefore, metal (Me
G using Schottky junction of semiconductor (tal) and semiconductor
o As field effect transistor (GaAsMIES
FI! T) Or n-type A Q * G az −w
High-speed devices not found in Si devices have been realized in selectively doped heterojunction FETs (for example, see Japanese Patent Application Laid-open No. 56-94779) that utilize the heterojunction interface between +A B and undoped GaAs. However, GaAsME
From the standpoint of device design of SFETs or selectively doped heterojunction FETs, in order to further improve the performance of these devices, it is necessary to thin the active layer (6200 layers) in GaAs MESFETs, and to thin selectively doped heterojunction FEs.
In T, the channel supply layer n-type AQGaA
It is essential to make the s layer thinner (6200 people). However, simply making the film thinner will limit the threshold voltage Vtk (particularly in the DCFL type circuit, the enhancement type FE
For T, a threshold voltage of about V□~0.1V is required, and for a depletion type FET, a threshold voltage of Vtk~-0.4V~-0.8V is required), so the impurity doping level is increased by 10"Ql~1
0"(I1-"), it becomes difficult to form a good Schottky junction, and the gate leakage current becomes extremely large, causing transistor malfunction.The Schottky barrier height directly under the gate electrode φ11, n type A
The film thickness of the jlGaAs layer is d-e, and the undoped AQG a
A sMl (I) Engineering & e, n l! A 11 Ga
AgJl t'. , K′-If the impurity concentration is N, then
Multiply the threshold voltage V□. However, ΔE0 is AlGaAs
It is the energy gap at the conduction band edge of GaAs and GaAs, and is usually the difference in electron affinity. Further, ε is the dielectric constant of AlGaAs, and q is the unit charge amount. FIG. 1 shows an energy band diagram immediately below the gate electrode of a conventional enhancement type selectively doped heterojunction FET.

There are 60 undoped AΩGaAs layers called spacer layers, and the Si donor doping level is 4×10”.
n-type All, Ga1-mAs with a film thickness of 140 people
T i / P t forming a Schottky junction in the layer
A three-layer metal layer of /Au is formed. However.

When a Schottky junction is formed between n-type AQ Ga□-, As with such a high doping level and the gate metal, when a positive potential of about +0.3V is applied to the gate metal, the gate leakage current begins to increase, causing the transistor Significantly deteriorates operating characteristics.

This is mainly due to n-type AQGaAs on the source side of the gate electrode.
Leakage current due to free electrons inside, tunneling of electrons in the two-dimensional electron gas layer at the Peter interface, or n-type Alρa
This is due to leakage current through the Dx center, donor level, etc. in As.

4. The work indicated by the solid line in Fig. 1(b). ．． Gate length L1.1μ
m, gate width W, 10 μm, source-drain current flow in the saturation region 41. 4. The structure shown by the 0-dot line has a gate structure corresponding to that in FIG. 1(d). ．．
This is the current characteristic that would be expected if 4. .

(solid line), it can be seen that the transistor characteristics have significantly deteriorated. This phenomenon is not unique to selectively doped heterojunction FETs; for example, GaAs
The same applies to MESFET. That is, with one and both FETs,
Source/drain current control in the saturation current region 41. is generally I, , = K(V, -Vtb)" -
It can be approximately described as (2). However, ■ is the gate voltage. If we try to increase the K value for the same Vtk, we can make the active layer thickness smaller and increase the impurity doping level N by ~10"C11-"~lO+1 from a simple consideration.
It is necessary to increase the size to ``al-3'', making it difficult to realize a good Schottky junction gate structure.

One way to prevent gate leakage current is to use an insulator (Si
n,, S isN, ate) and MIS (Ma
tal-engineering nsulatw-5ai+1conduct
or ) structure, but as mentioned above, there are many interface states and a realistic insulator cannot be obtained.
#csofSsmicconductor Device
es John Vilay & 5ons 1
(I) p
The addition of the type layer creates a new need to accurately determine the doping level and film thickness of the p-type layer in order to control V th . (2) Problems arise such as gate leakage current through the acceptor impurity of the p-type layer or instability of the threshold voltage.

[Purpose of the invention]

The purpose of the present invention is to insert a semiconductor that does not intentionally contain impurities (undoped) between a doped semiconductor and a gate metal forming a Schottky junction, thereby achieving MIS.
The object of the present invention is to provide a good Schottky gate structure that is close to the structure.

[Summary of the invention]

The present invention provides a semiconductor layer (II) in which a doped semiconductor layer (I) is slightly doped with an impurity having good lattice matching with the semiconductor layer (I) and a small number of interface states, or a semiconductor layer (II) in which impurities are not intentionally doped. By forming a Schottky metal after forming the semiconductor layer (II), (I) it is possible to prevent gate leakage current, and (2) it is possible to form a Schottky junction without adding new problems to the controllability of the threshold voltage Vth. This realizes a gate structure.

By employing the gate structure of the present invention, in relation to the above (I), the gate voltage V can be changed over a wide range f,j! mta
=h't', JL#In[14M4:1WJl;/'=
*l m ' The amplitude of the circuit can be increased, so the circuit design margin can be increased, and the speed of the circuit can be increased by allowing a large amount of current to flow. Further, by introducing a layer containing almost no impurities, no new R problem is caused in the controllability of Vt&.

The utility of the gate structure of the present invention is illustrated in detail through the following examples.

[Embodiments of the invention]

Example 1 FIG. 2 shows an example in which the gate structure of the present invention is applied to an enhancement type selectively doped heterojunction FET.

On a semi-insulating GaAs substrate 10, 5,000 layers of GaAs 11 were grown using MBE (intentionally doped with molecular beam pure material (resulting in a p layer of about 5×10"cn-"), and then undoped Al Yo G"t -m A s(x"
0.35) Layer 13 grew by 60 people. This is to ensure that the energy difference AE0 at the conduction band edge is 0.25 eV or more. Furthermore, Si was added to the donor level at I x 10"am-
”Including n-type An, Ga, -, A8 (0<y≦0.25
)13 grew by 100 people. AQ mixed crystal ratio is A11
Dx centers in GaAs are used to the extent that they are not formed by doping with Si.

Since Dx centers cause vtk fluctuations, it is important to select an AJ crystal ratio in a range where there are no Dx centers.
Next, an n-type layer Q containing Si about 10"as-",
Ga, -, As (0≦2≦1.0) 14 to 10
0 people formed. The Al mixed crystal ratio of 2 is designed to form a Schottky junction with the gate metal and increase the barrier height. Furthermore, Si may be used without being doped. this is,
It is particularly useful for MOCVD methods.

Next, in order to improve the ohmic contact between the source and drain electrodes, Si contains n containing approximately I x 101''G-3.
The molded GaAs layer 15 was formed by 200 people.

After crystal growth, source/drain electrodes 21 and 22 are formed using normal lithography, and CCII, F, /He
The n-GaAs layer 15 was selectively etched using a mixed gas to form a gate electrode 20. Au/Pt/Ti is used as the gate metal, and Au/Ni/Au-Ge is used as the source/drain metal.
was used.

In the gate structure formed in this way, since the n-type semiconductor layer 13 having a high impurity concentration and the gate metal 20 are not in direct contact with each other, a good F is obtained as shown by the dotted line in FIG. 1(b).
It showed ET characteristics. That is, when the gate voltage V was up to 1.4V, the gate leakage current was negligible.

Furthermore, as shown in FIG. 2(d), the n-type GaAs layer 15 is not necessarily necessary, and the structure shown in FIG. 2(b) may be used, that is, the structure shown in FIG. Type G a As layer 1
5 was not formed, but when forming the source/drain electrodes, the n-AllGaAs layer 14 was removed and an ohmic electrode was deposited.

In addition, GaAs is used between the source (drain) and gate electrodes.
(A11GaAs) For the purpose of protecting the layer, the insulator 23
is formed. Al1N is used as an insulator.

5i3N4t sio, etc. are used, but G a A
The interfacial potential φ with s(A Q GaAs) is generally equal to the barrier height φ1 of the Schottky junction. 0.15 compared to
~0.4 V is also low, and a two-dimensional electron gas layer is formed at the heterointerface in the gap between the source (drain) and gate electrodes.

In the selectively doped heterojunction FET having the structure of the present invention, the donor level of the n-type AaGaAs layer is doped to a very high concentration.

Donor concentrations present at the donor level can be created with great reproducibility. Therefore, the threshold voltage vt shown in equation (I)
Th can now be controlled with extremely high precision.

Example 2 An example of the process for forming enhancement type and depletion type selectively doped heterojunction FETs on the same substrate is shown in FIGS. 3(a), (b), (c), and (d).

Semi-insulating 0°" substrate 10 J"L:1. , MOCV
After forming 5,000 undoped GaAs layers 11 using the D method (organic J metal pyrolysis method), a structure with the same film thickness and doping level as in Example 1 (Fig. 3(a)
)) to form.

After forming 810223 as a protective film, the source/drain electrodes 21, 25, and 22 are formed in the 0th order.

The n-type GaAs layer 15 is selectively etched and removed to form gate gold l1t20 (FIG. 3(c)).

Next, a gate metal 24 is formed directly on the n-type GaAs layer to form a depletion type FET. Enhancement type F
For interlayer separation between the ET and the depletion type FET, the epitaxially grown layers 11, 12, 13°14.15 are removed by etching, or 0.15° is removed by etching. It is formed by implanting ions such as.

If it is desired to reduce the gate leakage current of the depletion type FET, an n-type AQGaAs layer may be formed as 15 in FIG. 3(a), and an undoped AfiGaAs layer may be formed on top of the n-type AQGaAs layer.

Example 3 An example in which the gate structure of the present invention is applied to a p-channel selectively doped heterojunction FET is shown in FIGS.
Shown in b).

After forming 5000 undoped Ge layers on the undoped Ge substrate 50 using the MBE method, undoped A 11
m G am -m A s (0-0≦X≦1.0
) 12 was formed by 60 people. Ge and A n * Gal
-m A s (0≦X≦1.0) has good lattice matching over a wide range of X, and the interface level at the hetero interface is 10” (Im
−” and small zero-order Be to acceptor level 10”0
p-type A 41 y Ga1-, As
(0, 0≦y≦0.35) 52 was formed by 100 people, and then a non-doped Al, Ga1-, As layer 14 was formed by 100 people. Furthermore, 200 people formed the p-type GaAs layer 53. The final p-type GaAs layer has a doping level of 10”am
In order to improve ohmic contact, the gate metal 60 was formed by vapor deposition.
Alloyed with Zn (99:1) by 1500 people.

These are source/drain metals 61, 62. The electrodes were formed by binding them together.

Example 4 A semi-insulating GaAs substrate 1 is shown in FIG. 5, in which the present invention is applied to a p-channel GaAs MESFET.
An undoped GaAs layer 11 is formed on 0 using the MBE method.
After forming 000 people, p-type G containing 1×10°1″1 Be
Form 100 aA s layers 32, and further undope G.
100 people formed the aAs layer 33. To form source/drain electrodes, the undoped GaAs layer 33 is removed and the P-type G
Ohmic contact was made to the aAs layer 32.

Since the gate metal 60 is in direct contact with the undoped G a A a layer 33, the gate leakage current is small and (
2) As the values expressed in the formula, W = 10 μm, gate length 1 μm, source-gate distance 0.7 μm, and 0.
A value of 5 mA/V'' was obtained. This value is a very large value when the mobility of the second layer 33 is 200 ali/v-8.

In the example, the active layer was an n-channel, but an n-channel FE using an n-type GaAs layer instead of the 33 layer was used.
It goes without saying that this method can also be implemented in T.

In addition, although the example shows the case of GaAs, Si
The present invention is also effective when forming an S i MESFET. That is, as the doping level of the active layer increases, the gate leakage current of the Schottky junction increases, making the present invention effective.

〔Effect of the invention〕

As is clear from the detailed description above, according to the present invention, a semiconductor layer that does not intentionally contain impurities (that is, undoped) is formed between the doped semiconductor and the gate metal forming the Schottky junction. By inserting
A good Schottky gate structure similar to the MIS structure can be provided.

Furthermore, according to the present invention, the impurity concentration directly under the gate electrode is reduced.

(I) The gate leakage current is suppressed, and (2) the logic amplitude of the FET can be increased.

When applied to a selectively doped heterojunction FET, in addition to the above (I) and (2), impurity F-1? □、2
．． KA, WORK, □Y2. □,. Since the value is close to the upper limit of J, there is an effect that threshold control becomes extremely easy.

[Brief explanation of drawings]

Figure 1 is a diagram showing a conventional gate structure and its current characteristics, Figures 2 and 3 are process diagrams when the gate structure of the present invention is applied to a selectively doped heterojunction FET, and Figure 4 is a diagram showing the gate structure of the present invention. A process diagram when applied to an n-channel selectively doped heterojunction FET, FIG. 5 shows a p-channel GaAs MESF.
It is an implementation diagram when the present invention is applied to ET. 10...Semi-insulating GaAs substrate, 11...Undoped GaAs, 12.=Undoped A Q GaA
s, 13 = n-type AQ GaAs, 14- undoped or n-type AQGaAs, 15- n-type GaAs,
21, 22. 61.62...source/drain electrode, 20.60.
...Gate electrode, 23...Interlayer insulating film, 50...G
e substrate, 51... Undoped Ge, 12... Undoped AAGaAs (or GaAs), 52-p type Afi
GaAg (or GaAs), 5s...-p type Ga A
s, 32 ・p-type GaAs, 33 ... undoped or p-type GaAs or 1st Guozui-VT

Claims (1)

[Claims] 1. A semiconductor device characterized in that in a Schottky junction between a semiconductor and a metal, the impurity doping level is low on the side near the interface with the metal, and the doping level is high on the far side. 2. After forming a semiconductor layer (II) that is not intentionally doped with impurities or a very weakly doped semiconductor layer (II) on the impurity-doped semiconductor layer (I), a Schottky junction is formed with the semiconductor layer (II). 1. A semiconductor device comprising a gate metal (III) having a gate metal (III). 3. In a heterojunction with good lattice matching between a semiconductor that has a high electron affinity and does not intentionally contain impurities and an n-type doped semiconductor that has a low electron affinity, impurities are not intentionally added to the n-type semiconductor layer. A semiconductor containing no or weakly doped with impurities is formed, further comprising a gate metal having a Schottky junction, and at least one pair of electrodes electronically connected to a two-dimensional carrier formed at the heterojunction interface. A semiconductor device comprising: 4. The sum of electron affinity and energy gap is small,
In a heterojunction that has a good lattice match between a semiconductor that does not intentionally contain impurities and a p-type doped semiconductor that has a large sum of electron affinity and energy gap, impurities are intentionally added to the p-type semiconductor layer. A semiconductor containing no or weakly doped with impurities is formed, and further has a gate metal having a Schottky junction, and at least a pair of gate metals electronically connected to a two-dimensional carrier formed at the heterojunction interface. A semiconductor device characterized by having an electrode. 5. After forming a semiconductor layer (II) that is not intentionally doped with impurities or a weakly doped semiconductor layer (II) on the impurity-doped semiconductor layer (I), a Schottky junction is formed with the semiconductor layer (II). A semiconductor device comprising at least one pair of electrodes formed with a gate metal (III) and electronically connected to a semiconductor layer (II) doped with impurities.