JP2658898B2 - field effect transistor - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to the structure of field effect transistors.

[0002]

2. Description of the Related Art A compound semiconductor field effect transistor (FET) using gallium arsenide or the like is characterized by high electron mobility compared to silicon, low power consumption and high speed I/O.
It has been applied to C and microwave devices. The high performance of such compound semiconductor field effect transistors is due to molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOC).
This is largely due to improvements in crystal technology such as the VD) method.

It is known that the epitaxial layer/semi-insulating substrate regrowth interface is often contaminated with impurities such as oxygen and carbon and is difficult to clean. Among these impurities, oxygen or the like forms a deep level in the semiconductor and causes device parasitic effects such as frequency dispersion of drain conductance and drain lag.
Conventionally, as one means of suppressing such a phenomenon, a technique of providing a p-type buffer layer (assuming an n-channel) under the channel layer has been used.

FIG. 5 is a crystal structure diagram of a conventional heterojunction field effect transistor (HJFET) with a p-type buffer layer. In FIG. 5, 51 is a semi-insulating GaAs substrate, 53 is a p-type GaAs layer forming a buffer layer, 54 is an undoped GaAs layer forming a carrier travel layer, and 55 is an n ⁺ -Al _0.2 Ga _0.8 As layer forming a carrier supply layer. is. A gate electrode 59 is formed in contact with 55 .

[0005]

SUMMARY OF THE INVENTION When introducing a p-type buffer layer, generally,
Impurity concentration and thickness are determined. This is because the presence of the neutral p-region increases the parasitic capacitance, degrading the inherent operating speed of the device. In other words, there are restrictions on the impurity concentration and thickness of the p-type buffer layer, and
Simply introducing a p-type layer into the buffer region does not work effectively to suppress the interface trap effect.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a field effect transistor having a structure in which a p-type layer is introduced in the most efficient region with an efficient impurity concentration and thickness for suppressing the interface trap effect. be.

[0007]

SUMMARY OF THE INVENTION The present invention provides a field effect transistor epitaxially grown on a semi-insulating compound semiconductor substrate, wherein a region of the epitaxial layer in contact with the semi-insulating substrate has conductivity opposite to that of the active layer. The surface concentration of impurities in that region is
is the interface between the semi-insulating substrate and the epitaxial layer
Higher than the area density of the wrap and the area is completely depleted
It is characterized by a thickness that typical interface
For the lap value (5×10 ¹¹ cm ⁻² ), the area
The impurity concentration should be 1×10 ¹⁷ cm ⁻³ or higher.

[0008] Incidentally, the above-mentioned conventional example is an n-channel FE.
T, and the following description also assumes an n-channel FET. However, in the case of a p-channel FET, the same argument can be made only by inverting the sign of the charge.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view showing one embodiment of the field effect transistor of the present invention. Semi-insulating GaAs substrate 1
1, p-type GaAs layer 13, undoped GaAs layer 14,
An n ⁺ -Al _0.2 Ga _0.8 As layer 15 and an n ⁺ -GaAs layer 16 are sequentially formed.

For example, it has the following structure.

Composition Impurity (cm ^-3 ) Thickness (nm) 16 GaAs 3e18(n) 80 15 Al _0.2 Ga _0.8 As 2e18(n) 65 14 GaAs Undoped 500 13 GaAs 1e18(p) 10 11 Semi-insulating GaAs substrate 13 is the p-type layer introduced by the present invention.

On this semiconductor substrate, a source electrode 17 and a drain electrode 18 are formed using, for example, gold germanium/nickel/gold, and a gate electrode 19 is formed using, for example, tungsten silicide. ing.

In this embodiment, AlGaAs/GaAs
Although it is an s-based HJFET, the present invention is also applicable to GaAs MESFETs fabricated by epitaxial growth.

The operation of this embodiment will now be described.

FIG. 2 is an energy band diagram of this embodiment, and FIG. 3 is a diagram showing the range of impurity concentration and thickness of the p-type layer of this embodiment. In FIG. 2, by providing the p-type layer 23 in the region in contact with the semi-insulating substrate 21, the Fermi level pinned to the interface trap is separated from the interface level, and the interface trap is always depleted. . At this time, the interface traps can be considered as simple fixed charges, and device parasitic effects such as frequency dispersion do not occur. The concentration and thickness of the p-type layer are determined from the condition that the areal density of the interface traps is higher and the p-type layer is completely depleted. The shaded area shown in FIG. 3 indicates the effect of a deep level where the surface density of interface traps is ⁵ ×10 ¹¹ cm ⁻² or less and the energy depth of the interface traps is deeper than 0.4 eV from the conduction band. It is a region of impurity concentration and thickness of the p-type layer to be eliminated. These are typical interface ^{trap values} , and from FIG. can be removed.

FIG. 4 is a diagram showing the effect of the present embodiment by comparing the conventional example and the present embodiment. FIG. 4 compares the transient response of the drain current when the drain voltage is changed stepwise. In the conventional example, a large fluctuation in the drain current is observed, which is thought to be due to the response of the interface traps. However, in this example, the interface trap response disappears and only a slight fluctuation due to the substrate trap remains.

[0018]

INDUSTRIAL APPLICABILITY As described above, according to the present invention, the region of the epitaxial layer in contact with the semi-insulating substrate is provided with a non-uniformity in that region.
The plane concentrations of pure substances are the semi-insulating substrate and the epitaxial
is higher than the areal density of interface traps with the layer, and the area is
By introducing a layer whose thickness is fully depleted ,
It has the effect of suppressing device parasitic effects caused by traps at the interface between the epitaxial layer and the semi-insulating substrate.

[Brief description of the drawing]

1 is a cross-sectional view showing an embodiment of a heterojunction field effect transistor of the present invention; FIG.

FIG. 2 is an energy band diagram of this embodiment;

FIG. 3 is a diagram showing ranges of impurity concentration and thickness of a p-type layer in this embodiment;

4A and 4B are diagrams for explaining the effect of the present embodiment on the interface trap effect; FIG.

FIG. 5 is a cross-sectional view of a conventional heterojunction field effect transistor;

[Description of symbols]

11, 21, 51 semi-insulating GaAs substrates 13, 23, 53 p-type GaAs buffer layer 52 undoped GaAs buffer layers 14, 24, 54 undoped GaAs electron transit layers 15, 25, 55 n ⁺ -Al _0.2 Ga _0.8 As electron supply layers 16, 56 n ⁺ -GaAs cap layers 17, 57 source electrodes 18, 58 drain electrodes 19, 59 gate electrodes

Claims (4)

(57) [Claims] 1. A field effect transistor formed by epitaxial growth on a semi-insulating compound semiconductor substrate, wherein a region of the epitaxial layer in contact with the semi-insulating substrate is formed of a semiconductor layer of conductivity type opposite to that of the active layer. and the surface concentration of the impurity in that region is the same as that of the semi-insulating substrate.
higher than the areal density of interface traps with the epitaxial layer
a field effect transistor characterized in that the region is of a fully depleted thickness . 2. A heterojunction field effect transistor formed by epitaxial growth on a semi-insulating compound semiconductor substrate, wherein a region of the epitaxial layer in contact with the semi-insulating substrate is a semiconductor layer of conductivity type opposite to that of the active layer. The surface concentration of impurities in that region is equal to that of the semi-insulating group.
than the areal density of interface traps between the plate and the epitaxial layer
and the thickness of the region is such that it is fully depleted.
A heterojunction field effect transistor characterized by: 3. A GaAs Schottky gate field effect transistor epitaxially grown on a semi-insulating compound semiconductor substrate, wherein a region of the epitaxial layer in contact with the semi-insulating substrate is a semiconductor layer of a conductivity type opposite to that of the active layer. is formed, and the surface concentration of impurities in that region is
an interfacial stress between the semi-insulating substrate and the epitaxial layer;
higher than the areal density of the chip and the area is fully depleted
A GaAs Schottky gate field effect transistor characterized by a thickness of 4. The epitaxial layer in contact with the semi-insulating substrate.
The areal density of impurities in the region where ¹¹ cm ^-2 That's it
Claim 1 or claim 2 or claim characterized by
Item 4. The field effect transistor according to item 3.