GB2069754A - Field effect transistor - Google Patents
Field effect transistor Download PDFInfo
- Publication number
- GB2069754A GB2069754A GB8004999A GB8004999A GB2069754A GB 2069754 A GB2069754 A GB 2069754A GB 8004999 A GB8004999 A GB 8004999A GB 8004999 A GB8004999 A GB 8004999A GB 2069754 A GB2069754 A GB 2069754A
- Authority
- GB
- United Kingdom
- Prior art keywords
- substrate
- field effect
- effect transistor
- gate
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 12
- 239000000463 material Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims abstract description 6
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052733 gallium Inorganic materials 0.000 claims abstract description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/432—Heterojunction gate for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/802—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
A heterojunction gate inversion field effect transistor includes a semiconductor substrate on which a gate layer (12) of a semiconductor material having a wider band gap and a lower electron affinity than the substrate material is deposited. Typically the substrate comprises gallium arsenide and the gate material comprises gallium aluminium arsenide. The device may be formed by epitaxially depositing gallium aluminium arsenide on a gallium arsenide substrate, forming windows through the epitaxial layer, diffusing or implanting to form source and drain regions 17, 18 in the windows and applying contacts 21. <IMAGE>
Description
SPECIFICATION
Field effect transistor
This invention relates to field effect transistors (FET's), and in particular to FET's of the heterojunction gate inversion type. The invention also relates to methods of fabricating such transistors.
Semiconductor logic and switching devices are at present constructed from silicon as the semiconductor material. Silicon has the advantage that it is relatively cheap and the processes involved in device fabrication are well understood. Whilst such devices have wide application problems arise where very high switching speeds are required. To some extent these problems can be reduced by suitable design of the active device, but this does not overcome the fundamental problem which is inherent in the material itself. Thus the switching speed is limited ultimately by the mobility of current carriers through the semiconductor.
For this reason other semiconductors of higher carrier mobility, for example, gallium arsenide, have been investigated. However, severe problems have arisen in the production of conventional inversion
MISFET's from these materials. This arises from the lack of a suitable semiconductor-insulator interface structure in materials other than silicon.
The object of the invention is to minimise or to overcome these disadvantages.
According to one aspect of the invention there is provided a heterojunction gate inversion field effect transistor, including a semiconductor substrate, and a semiconductor gate material layer disposed on a major surface of the substrate, and in which said gate material has a wider band gap and a lower electron affinity than the substrate material.
According to another aspect of the invention there is provided a method of fabricating a heterojunction gate inversion field effect transistor, including growing on a semiconductor substrate an epitaxial layer of a material of wider band gap and lower electron affinity than the substrate, forming windows in the layer, diffusing or implanting source and drain regions in the underlying substrate via the windows, and applying contacts to the layer and to the source and drain regions.
An embodiment of the invention will now be described with reference to the accompanying drawings in which Figure 1 to 4 show the various stages in the fabrication of a heterojunction gate inversion field effect transistor.
Referring to the drawings, the semiconductor device is fabricated on a p-type semiconductor, typically gallium arsenide, substrate body 11. To form a 'gate' region a semiconductor epitaxial layer 12 is then deposited on the surface of the body 11.
Advantageously this is performed by a vapour epitaxial process.
This latter material is chosen with a wider band gap and a lower electron affinity than the substrate material and thus forms a heterojunction 13 with the substrate. Typically this epitaxial layer 12 comprises gallium aluminium arsenide.
The primary requirement in choosing the 'gate' material is the provision of a relatively large step in the conduction band at the heterojunction 13. Hence the electron affinity of the 'gate' material should be low relative to that of the substrate 11. By application of reverse bias to this junction inversion conditions may be established on the substrate side of the interface and the inversion charge (electrons) will be contained in the potential well in the conduction band. The inversion layer may then be used to connect adjacent in regions as in a conventional
MISFET. The most readily available material that meets this requirement is gallium aluminium arsenide. In addition the width of the potential barrier at the heterojunction, that is the width of the depleted region formed in the 'gate' material, must be sufficient to prevent electron flow by tunnelling.This implies that the 'gate' material is lightly doped or semi-insulating.
The requirement of crystal lattice matching is of lesser importance. Thus, whereas semiconductor lasers require a high degree of lattice matching to reduce interface strain to a minimum, FET's are not subjected to such extreme operating conditions and a higher degree of mismatch can be tolerated. For example, it is well known that considerable strain exists at the silicon/silica interface of a conventional silicon IGFET.
We have found that a suitable 'gate' material is gallium aluminium arsenide containing a relatively high proportion of aluminium. An alloy containing e.g. up to 50 atomic % aluminium may be employed.
Following deposition of the 'gate' material layer a photolithographic masking layer 14 is applied and exposed and developed to form windows 15 and 16.
The epitaxial layer is then removed from within the windows 15 and 16 whereby source and drain regions 17 and 18 respectively are doped n-type for example by ion implantation. A passivating layer 19 is then applied over the whole structure and the source and drain regions are annealed. Contact windows 20 are then cut using conventional selective processing techniques and contacts 21 are applied using a suitable metallurgical system. The device may then be contacted and packaged in the normal way.
Claims (7)
1. A heterojunction gate inversion field effect transistor, including a semiconductor substrate, and a semiconductor gate material layer disposed on a major surface of the substrate, and in which said gate material has a wider band gap and a lower electron affinity than the substrate material.
2. A field effect transistor as claimed in claim 1, and wherein the substrate is gallium arsenide.
3. A field effect transistor as claimed in claim 2, and wherein the gate material is gallium aluminium arsenide containing up to 50 atomic % aluminium.
4. A field effect transistor substantially as de- scribed herein with reference to the accompanying drawings.
5. An integrated circuit including plurality of transistors as claimed in any one of the preceding claims.
6. A method of fabricating a heterojunction gate inversion field effect transistor, including growing on a semiconductor substrate an epitaxial layer of a material of wider band gap and lower electron
affinity than the substrate, forming windows in the
layer, diffusing or implanting source and drain regions in the underlying substrate via the windows, and applying contacts to the layer and to the source and drain regions.
7. A process for fabricating a field effecttransis
tor substantially as described herein with reference
to the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8004999A GB2069754B (en) | 1980-02-14 | 1980-02-14 | Field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8004999A GB2069754B (en) | 1980-02-14 | 1980-02-14 | Field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2069754A true GB2069754A (en) | 1981-08-26 |
| GB2069754B GB2069754B (en) | 1984-01-04 |
Family
ID=10511351
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8004999A Expired GB2069754B (en) | 1980-02-14 | 1980-02-14 | Field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2069754B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3526826A1 (en) * | 1984-07-26 | 1986-02-06 | Kaoru Sendai Miyagi Motoya | STATIC INDUCTION TRANSISTOR AND SAME INTEGRATED CIRCUIT |
| DE3528562A1 (en) * | 1984-08-08 | 1986-02-13 | Motoya, Kaoru, Sendai, Miyagi | TUNNEL INJECTION TYPE STATIC INDUCTION TRANSISTOR AND COMPREHENSIVE INTEGRATED CIRCUIT |
-
1980
- 1980-02-14 GB GB8004999A patent/GB2069754B/en not_active Expired
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3526826A1 (en) * | 1984-07-26 | 1986-02-06 | Kaoru Sendai Miyagi Motoya | STATIC INDUCTION TRANSISTOR AND SAME INTEGRATED CIRCUIT |
| DE3528562A1 (en) * | 1984-08-08 | 1986-02-13 | Motoya, Kaoru, Sendai, Miyagi | TUNNEL INJECTION TYPE STATIC INDUCTION TRANSISTOR AND COMPREHENSIVE INTEGRATED CIRCUIT |
| FR2569056A1 (en) * | 1984-08-08 | 1986-02-14 | Japan Res Dev Corp | TUNNEL INJECTION TYPE STATIC INDUCTION TRANSISTOR AND INTEGRATED CIRCUIT COMPRISING SUCH A TRANSISTOR |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2069754B (en) | 1984-01-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 732 | Registration of transactions, instruments or events in the register (sect. 32/1977) | ||
| PCNP | Patent ceased through non-payment of renewal fee |