JPS6216573A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit a diffusion in the lateral direction of a P-type diffusion layer, to shorten gate length and to improve performance such as the shortening of the propagation delay time by using a means applying larger strain by the P-type diffusion layer when shaping the P-type diffusion layer. CONSTITUTION:Si is employed as an implantation seed to a semi-insulating GaAs substrate 1, and an N-type semiconductor layer 2 is shaped. An AlN film 3 is deposited on the surface, an opening section is formed, a Zn-implanted layer 4 is shaped while using the AlN film and a resist as masks, an Si3N4 film 5 is deposited on the surface, and a P-type diffusion layer 4' is formed. Only the Si3N4 film 5 is deposited on the surface of the Zn-implanted layer 4, the AlN film 3 and the Si3N4 film 5 are shaped on other surfaces, and the difference of thermal expansion coefficients with GaAs is increased only on the Si3N4 film, and strain is applied to GaAs. When strain is applied, an equivalent diffusion coefficient is augmented. Accordingly, a diffusion in the depth direction is enhanced, a diffusion in the lateral direction is inhibited, and gate length is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a junction field effect transistor.

Conventional technology Compound semiconductors such as those manufactured by G & M S have high speeds due to their high electron mobility and the ability to form semi-insulating substrates.

Used in semiconductor devices in the high frequency range. As such a semiconductor device, a Schottky barrier gate field effect transistor (hereinafter abbreviated as MKS-FICT) is commonly used. Like the MIC3-FIT, a junction field effect transistor (hereinafter abbreviated as J-FIT) is also a useful device as a semiconductor device in a high speed, high frequency region. J-
FIT is more thermally stable than MIS-FIT. Enhancement-type FIET (normally-off type FIE'l', hereinafter abbreviated as -F1.T), which is strong against surges. When configured with -FIT and used in a logic circuit, it has advantages such as large logic amplitude. . On the other hand, as a drawback,
Since lateral diffusion occurs when forming the gate region and it is difficult to shorten the gate length, J-FIT using a compound semiconductor is hardly used as a semiconductor device in a high speed, high frequency region.

FIG. 2 is a schematic diagram of the conventional J-FICT manufacturing process. Semi-insulating G in Figure 2 (&)! An n-type conductive semiconductor layer 12 is formed on the LA 511 using an ion implantation method. Second
In Figure (b), using the silicon nitride film 13 formed on the NFJL conductive semiconductor layer 12 as a mask, τ, zinc (Zn) is ion-implanted using the ion implantation method, heat-treated in an arsenic atmosphere, and a p-type diffusion layer is formed. form 14. In FIG. 1(C), ohmic electrodes are formed using Au-Ga based material and are used as a source electrode 16 and a drain electrode 17. An ohmic electrode is formed in the p-type diffusion layer using a mu-Zn system, and the gate electrode 18 is
shall be.

The problem that the invention seeks to solve In the J-FET formed in this way.

When forming a p-type diffusion layer that will become a gate region, lateral diffusion is large, making it difficult to shorten the gate length, and the maximum oscillation frequency cannot be improved in high frequency characteristics. Therefore, when used in high-speed logic circuits, etc., it becomes difficult to shorten the propagation delay time.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, an object of the present invention is to provide a method for manufacturing a junction field effect transistor in which the gate length can be easily shortened.

Means for Solving the Problems The present invention provides the following steps when forming a p-type semiconductor layer on an n-type semiconductor layer:
Diffusion is performed by applying strain to the surface of the p-type semiconductor layer from the surface of the n-type semiconductor layer.

According to the present invention, it is possible to obtain a method for manufacturing a J-FIT in which lateral diffusion is suppressed and the gate length can be easily shortened.

Embodiment FIG. 1 shows a G&M 5J-FET in an embodiment of the present invention.
FIG. 2 is a schematic diagram of the manufacturing process.

Using a selective ion implantation method into a semi-insulating GaAs substrate 1,
Using Si as the injection material, the injection amount was 3 x 1012α-2 at an accelerating voltage of 120ke, and the temperature was 820°C under the pressure of S.
A heat treatment is performed for 20 minutes to form an n-type semiconductor layer 2 that will become a channel region. (Figure 1(a)).

A 15N film 3 is formed on the surface of the n-type semiconductor layer 2 and the semi-insulating substrate 1.
was deposited, an opening was formed, and using the selective ion implantation method using the AeN film and resist as a mask, Zn was used as the implanter, and the implantation amount was 10 at an acceleration voltage of 501 cav.
A Zn implantation layer 4 is formed by ion-implanting Zn. (FIG. 1(b)) A 5i5N4 film 6 was deposited on the surface of the Zn injection layer 4 and the 5N film 30, and the film was heated to 75% in a nitrogen atmosphere.
A heat treatment is performed at 0°C for 16 minutes to form a p-type diffusion layer 4'. (Figure 1 (C)) The important thing at this time is + Zn
Since only the 5i3N4 film 5 is deposited on the surface of the injection layer 4, and the Mue11 film 3 and the Si3N4 film 6 are formed on the other surfaces, the Zn injection layer is more strained than other parts. This is a major addition. This has a coefficient of thermal expansion of G! 5.9X10''''/℃ at LAS,
6.1 × 10 layers in AeN °C.

Since Si x and N 4 are 3.2 x 10-67"C, the thermal expansion coefficient of an insulating film consisting of two layers of Si3N4 film and MueN film is almost equal to that of GaAs. In the case where the difference in thermal expansion coefficient with G & M S is large (, strain is applied to Gaps. When strain is applied, the equivalent diffusion coefficient increases. In the example, Z
Since more strain is applied to the n-injected layer than to other parts, diffusion in the depth direction is increased, diffusion in the lateral direction is suppressed, and the gate length can be shortened.

After removing the Si3N4 film 6, using a normal photolithography method,
The surface of the p-type diffusion layer 4' is exposed to form an ohmic electrode made of Mu--Zn, which serves as the gate electrode 6. (FIG. 1(d)) The n-type semiconductor layer in the regions that will become the source and drain is exposed on the MulN film 3 using a normal photolithography method.

An ohmic electrode made of Mu-Go system is formed, and a source electrode 7. A drain electrode 8 is used. (FIG. 1(e)) The voltage applied to the gate electrode 6 in the above steps increases the conductivity of the n-type semiconductor layer 2 through the p-n junction between the p-type semiconductor layer 4' and the n-type semiconductor layer 2. It is possible to obtain J-FICT that controls.

In the embodiment, Gaps was used as the substrate.

Compound semiconductors such as InP and InGaAg may also be used. Furthermore, although the Zn implantation layer was formed by ion implantation in the embodiment, a diffusion method or the like may also be used. Note: As a race + Zn
However, other elements such as Mg, C (1, etc.) may be used.As a method of applying strain to form a pm diffusion layer, a combination of insulating films other than those in the examples may be used, or a p-type diffusion layer may be used. An insulating film is formed only on the surface.

An insulating film may not be deposited on the other surfaces, and heat treatment may be performed in a muS pressure atmosphere.

Effects of the Invention As described above, according to the present invention, when forming the p-diffusion layer, lateral diffusion of the p-diffusion layer can be suppressed by using means that applies a larger strain to the p-diffusion layer. This makes it possible to shorten the gate length, improve the maximum oscillation frequency of J-FICT, and when used as a device for high-speed logic circuits, improve performance such as shorten propagation delay time, increasing its industrial value. is big.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the manufacturing process of a J-FIT according to an embodiment of the present invention, and FIG. 2 is a sectional view showing the manufacturing process of a conventional J-FKT. 1... Semi-insulating G & Mus, 2......n
type semiconductor layer, 3..., AeN film, 4...
Zn injection layer, 4'...p diffusion layer, 6...
...3i3N4 film, 6...gate electrode. 7...-Source electrode, 8...Drain electrode. Figure 2 c3 A

Claims (3)

[Claims] (1) When forming a semiconductor layer of one conductivity type on a semiconductor substrate and forming a region of the opposite conductivity type in a desired region of the semiconductor substrate,
A method for manufacturing a semiconductor device in which it is formed by applying strain. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is a compound semiconductor, and an insulating film is provided on the surface of the opposite conductivity type region to apply strain. (3) The method of manufacturing a semiconductor device according to claim 2, wherein the insulating film formed on the surface of the semiconductor layer of one conductivity type is different from the insulating film formed on the surface of the region of the opposite conductivity type.