JPH08264724A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PURPOSE: To fabricate FETs of different polarities on the same substrate through a simple process. CONSTITUTION: After forming a GaAs layer 2, a p-type InGaP layer 3, and a p-type GaAs layer 4 on a GaAs substrate 1, an isolation region 5 is formed thus forming a p-type HEMT structure in a p-type element forming region Ap and then n-type ions 7 are implanted into an n-type element forming region An. Subsequently, it is annealed and a junction FET comprising the p-type GaAs layer 4, the p-type InGaP layer 3, and an n-type GaAs layer 2' is formed followed by the formation of gate electrodes 8P, 8N. It is then used as a mask for forming p<+> layers 9S, 9D implanted with p<+> ions in the p-type element forming region Ap and n<+> layers 10S, 10D implanted with n<+> ions in the n-type element forming region An. Thereafter, an insulation layer 11 is formed, annealing is effected and ions are implanted for the purpose of activation. Finally, source electrodes 12, 14 and drain electrodes 13, 15 are formed thus fabricating an FET comprising p-type elements and n-type elements.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is a first invention on a compound semiconductor.
The present invention relates to a semiconductor device including a conductivity type HEMT and a second conductivity type junction FET, and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIGS. 2A to 2D are sectional views in respective steps for explaining an example of a conventional method for manufacturing a compound semiconductor complementary integrated circuit. First, as shown in FIG. 2A, MBE method or M
High purity G by epitaxial growth using OCVD method
The aAs active layer 22, the p-type AlGaAs layer 23, and the p-type GaAs layer 24 are sequentially stacked.

Next, as shown in FIG. 2B, after leaving the p-type element forming region Ap and removing the other regions by wet etching, the n-type element forming region on the semi-insulating GaAs substrate 21. An opening 26 formed by insulating film 25 on An
To form. Next, as shown in FIG.
In the same manner as described above, the high-purity GaAs active layer 27 is formed by epitaxial growth using the MBE method or the MOCVD method in the same manner as described above.
The n-type AlGaAs layer 28 and the n-type GaAs layer 29 are sequentially stacked. In this case, it is necessary to set growth conditions so that epitaxial growth does not occur on the insulating film 25.

Next, as shown in FIG. 2D, after removing the insulating film 25 on the p-type element formation region Ap, a gate electrode 30, a source electrode 31 and a drain electrode 32 of the p-type semiconductor element are formed, At the same time, the gate electrode 3 of the n-type semiconductor device
3, the source electrode 34 and the drain electrode 35 are formed to complete the p-type semiconductor element and the n-type semiconductor element. Further, both semiconductor elements are connected to each other by a wiring process to manufacture an integrated circuit.

[0005]

However, according to the above-mentioned conventional manufacturing method, it is necessary to go through an immature process such as selective regrowth which is not well established and has doubts about uniformity and reproducibility. Further, a semi-insulating GaAs substrate 21
Is removed by etching, a step difference of about 1 μm is generated in the middle of the process, and the step difference is reduced because it is filled by re-growth thereafter, but it is not perfect.

[0006] Such a step becomes a major defect in the process since a step of about 100 Å, for example, becomes a problem in the subsequent exposure step, particularly when forming a fine pattern such as gate formation. In addition, keeping the growth film thickness within the error range of about 100 Å or less for a growth of about 1 μm means that the growth rate reproducibility and uniformity are about 1%.
It is technically difficult to realize with the following accuracy,
I doubt the practicality.

Therefore, the present invention has been made to solve the above-mentioned conventional problems, and an object thereof is a semiconductor device capable of forming field effect transistors of different polarities on the same substrate by a simple process. And to provide a manufacturing method thereof.

[0008]

In order to achieve such an object, the present invention provides a first conductivity type HEMT and a second conductivity type junction FET on the same semiconductor substrate.

Further, in the method for manufacturing a semiconductor device according to the present invention, the second conductivity type impurity is injected into a part of the first conductivity type HEMT formed on the semiconductor substrate to activate the semiconductor substrate. The second conductivity type junction type FET is partially formed.

[0010]

According to the present invention, the semiconductor element having the first conductivity type HEMT and the second conductivity type junction FET having different polarities does not require selective regrowth to form a complementary integrated circuit.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1A to 1D are cross-sectional views in each process for explaining a structure according to an embodiment of a semiconductor device according to the present invention according to a manufacturing method. In FIG. 1, an example of forming an n-type junction FET on a p-type HEMT substrate will be described.
Even when the p-type junction FET is formed on the n-type HEMT substrate, the p-type and the n-type are merely opposite, and the others are the same.

First, as shown in FIG. 1A, the semi-insulating G
The high-purity GaAs layer 2 and the p-type I are formed on the aAs substrate 1 by epitaxial growth using the MBE method or the MOCVD method.
The nGaP layer 3 and the p-type GaAs layer 4 are sequentially stacked. Next, as shown in FIG. 2B, the element isolation region 5 is formed in a portion outside the element formation region. This element isolation region 5
Is formed by ion-implanting oxygen or boron at a high concentration.

Next, a resist pattern 6 having an opening 6a only in the n-type element forming region An is formed on the p-type GaAs layer 4, and n-type ions 7 such as Si are implanted through the opening 6a. At this time, the implantation energy of the n-type ions 7 needs to be selected so that the Si ions reach the high-purity GaAs layer 2 sufficiently, and the implantation amount is p-type InGaP layer 3 and p-type after the activation annealing. It is necessary to select the GaAs layer 4 so as not to be n-type.

By these steps, the n-type element forming region An is annealed and the p-type GaAs layer 4 and the p-type I are formed after the annealing.
A structure capable of forming a junction type FET in which the nGaP layer 3 and the n-type GaAs layer 2'are arranged in order is realized. Next in FIG.
As shown in (c), a refractory metal film such as WSi or WSiN is deposited on the entire surface of each p-type GaAs layer 4 in the p-type element formation region Ap and the n-type element formation region An by sputtering or plasma CVD. Then, fine processing is performed by the resist process and the ECR etching method or the RIE method to form the gate electrodes 8P and 8N, respectively. In this case, it is important that no step is formed on the semi-insulating GaAs substrate 1.

Next, as shown in FIG. 1D, the gate electrode 8
After forming P and 8N, the n-type element formation region An is covered with a resist pattern (not shown), p-type ions are implanted using the gate electrode 8P as an implantation mask, and the resist pattern is removed. The Ap is covered with a resist pattern (not shown), n-type ions are implanted using the gate electrode 8N as an implantation mask, and then the resist pattern is removed. After that, the front and back surfaces of the semi-insulating GaAs substrate 1 are covered with an insulating film (not shown), and a high temperature heat treatment is performed.

As a result, in the p-type element formation region Ap,
The p ⁺ layers 9S and 9D serving as the source region and the drain region are formed, and the n ⁺ layers 10S and 10D serving as the source region and the drain region are formed in the n-type element formation region An.

Next, an insulating film 11 such as SiO ₂ is formed on the front and back surfaces of the semi-insulating GaAs substrate 1 on which each of these layers and a plurality of electrodes are formed by a plasma CVD method and annealed to implant the implanted ions. Activate. afterwards,
The source formation region and the drain formation region of the insulating film 11 on the surface side of the semi-insulating GaAs substrate 1 are patterned by the exposure method using a resist and then removed by the RIE method, and the source electrode 12 is formed in the p-type element formation region Ap. , The source electrode 1 in the drain electrode 13 and the n-type element formation region An
4, the drain electrode 15 is formed by the lift-off method and p
The FET composed of the mold element and the n-type element is completed. After that, these two types of FETs are connected to each other so as to form a complementary circuit to form an integrated circuit.

According to this method, n-type ions 7 are implanted into the high-purity GaAs layer 2 in the semi-insulating GaAs substrate 1 having the p-type HEMT structure to form a pn junction, and the pn junction is gated. The n-type junction FET used as the region can be formed on the same semi-insulating GaAs substrate 1 by a simple process.

According to this structure, the p-type element portion has a HEMT structure, and the n-type element portion has a junction type FET, so that a complementary integrated circuit based on a different operation principle can be realized.

[0020]

As described above, according to the present invention,
A semiconductor element in which the first conductivity type HEMT and the second conductivity type junction FET have different polarities can be easily realized without going through a difficult process such as selective regrowth, and a complementary integrated circuit can be easily realized. The extremely excellent effect of becoming

[Brief description of drawings]

FIG. 1 is a cross-sectional view in each process for explaining a configuration according to an embodiment of a semiconductor device according to the present invention according to a manufacturing method.

FIG. 2 is a cross-sectional view in each process for explaining a configuration of an example of a conventional semiconductor device according to a manufacturing method.

[Explanation of symbols]

1 ... Semi-insulating GaAs substrate, 2 ... High-purity GaAs layer,
2 '... n-type GaAs layer, 3 ... p-type InGaP layer, 4 ... p
Type GaAs layer, 5 ... Element isolation region, 6 ... Resist pattern, 6a ... Opening, 7 ... N type ion, 8P, 8N ... Gate electrode, 9S, 9D ... P ⁺ layer, 10S, 10D ... N ⁺ layer,
11 ... Insulating film, 12 ... Source electrode, 13 ... Drain electrode, 14 ... Source electrode, 15 ... Drain electrode, An ... N
P-type element formation region, Ap ... p-type element formation region, 21 ... Semi-insulating GaAs substrate, 22 ... High-purity GaAs active layer, 23
... p-type AlGaAs layer, 24 ... p-type GaAs layer, 25 ...
Insulating film, 26 ... Opening, 27 ... GaAs active layer, 28 ...
n-type AlGaAs layer, 29 ... N-type GaAs layer, 30 ... Gate electrode, 31 ... Source electrode, 32 ... Drain electrode, 3
3 ... Gate electrode, 34 ... Source electrode, 35 ... Drain electrode.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/812 21/337 29/808

Claims (2)

[Claims] 1. A semiconductor device comprising a first conductivity type HEMT and a second conductivity type junction type FET provided on the same semiconductor substrate. 2. A junction of the second conductivity type is bonded to a part of the semiconductor substrate by implanting and activating an impurity of the second conductivity type into a part of the HEMT of the first conductivity type formed on the semiconductor substrate. A method of manufacturing a semiconductor device, which comprises forming a type FET.