JPH10321644A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacture method of a semiconductor device, which holds a distance among a gate layer, a source layer and a drain layer to be constant, reduces the number of masks and reduces manufacture cost. SOLUTION: Mask layers 21 and 22 are formed on a semiconductor substrate 10 and an opening part for introducing impurity for forming the gate layer and the source/drain layers is provided. The opening part for introducing impurity for forming a first resist film R3 and for forming the gate layer is protected. First conductivity type impurity is introduced to the opening part for forming the source/drain layers, and the source layer 12 and the drain layer 13 are formed. A second resist film R4 is formed by using an exposure mask for forming the first resist film and a resist material having the light reaction characteristic of the resist material for the first resist film and an inverted optical reaction characteristic. The opening part for introducing impurity for forming a second resist film R4 and for forming the source/drain layers is protected, second conduction-type impurity is introduced for the opening part for introducing impurity for forming the gate layer and the gate layer 14 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a junction field effect transistor.

[0002]

2. Description of the Related Art Field effect transistors (FETs)
Effect Transistor is a voltage-driven semiconductor device. Unlike current-driven semiconductor devices of bipolar transistors, it is a small active element with characteristics similar to a vacuum tube, and plays an important role in recent semiconductor devices. Plays.

The above-mentioned field-effect transistors are roughly divided into metal-oxide-semiconductor stacked field-effect transistors (MOSFETs; Metal-Oxide-Semiconductor FETs).
And a junction field effect transistor (J-FET; Juncti)
on-FET).

[0004] Among them, the J-FET is a semiconductor device widely used in high-frequency ICs such as MMICs. For this reason, it is very important to produce a J-FET with a constant high-frequency characteristic.

FIG. 11 is a cross-sectional view of a semiconductor device having a junction field-effect transistor manufactured by a conventional method. An n-type channel forming region 11 is provided in a semi-insulating GaAs semiconductor substrate 10 in a region separated by element isolation such as a boron implantation layer (not shown), and n ⁺ -type source layer 12 and drain layer 13 are provided at both ends. Are formed. A p ⁺ -type gate layer 14 is formed in the center of the channel formation region 11, thereby forming a junction field-effect transistor (J-FET). In FIG. 11, L _g is the gate length, L _gs is the distance between the gate layer and the source layer, L _gd
Is the distance between the gate layer and the drain layer.

A second insulating film 28 and a sidewall insulating film 29a are formed on the semiconductor substrate 10, respectively.
An opening reaching the gate layer 14, the source layer 12, and the drain layer 13 is provided, and a metal electrode 33 is formed.

A method of manufacturing a semiconductor device having the above-mentioned junction field-effect transistor by a conventional method will be described below with reference to the drawings. First, as shown in FIG. 12A, a first insulating film 27 is formed by depositing silicon nitride on a semi-insulating GaAs semiconductor substrate 10 by a CVD method.

Next, as shown in FIG. 12B, a resist film R8 is patterned and a dopant ion D7 such as silicon ion is implanted into a pattern opening as a mask, and an n ⁺ -type source The layer 12 and the drain layer 13 are formed.

Next, as shown in FIG. 12C, after removing the resist film R8, a new resist film R9 is formed and patterned, and a dopant such as silicon ions and magnesium ions is used as a mask in the pattern opening. The ions D8 are implanted to form an n-type channel formation region 11 in the semiconductor substrate.

Next, as shown in FIG. 13D, the resist film R9 is removed, and RIE (reactive ion etching) is performed.
The first insulating film 27 is removed by etching or the like. Thereafter, an annealing process is performed to activate the implanted ions.

Next, as shown in FIG.
For example, by depositing silicon nitride by CVD, a second insulating film 28 is formed, and a resist film R10
Is formed, and patterning is performed so as to open the formation region of the gate layer.

Next, as shown in FIG. 13 (f), dry etching such as RIE is performed using the resist film R10 as a mask, and the semiconductor substrate 10 An opening for exposing the surface is formed.

Next, as shown in FIG. 14 (g), the resist film R10 is removed, and silicon nitride is deposited by, for example, a CVD method to form a third insulating film 29.

Next, as shown in FIG.
The third insulating film 29 in the upper layer portion of the gate layer is removed by performing dry etching such as, for example, to expose the semiconductor substrate 10. At this time, the sidewall insulating film 29a remains in the opening of the region where the gate layer is formed in the second insulating film 28, and the opening for introducing the dopant for forming the gate layer can be narrowed.

Next, as shown in FIG. 14I, a p-type dopant D9 such as Zn is diffused from an opening for introducing a dopant for forming a gate layer to form a p ⁺ -type gate layer 14. I do.

Next, a resist film is formed, patterned, etched by RIE or the like, and an opening for exposing the surface of the source layer 12 and the drain layer 13 is formed in the second insulating film 28. After removing the film, a metal electrode 33 connected to the gate layer 14, the source layer 12, and the drain layer 13 is formed, and the semiconductor device shown in FIG. 11 is obtained.

[0017]

However, according to the method of manufacturing a semiconductor device having a junction field effect transistor according to the above-described conventional method, the gate layer 14, the source layer 12, and the drain layer 13 are formed by using different masks. Has formed. Therefore, the gate layer 14 and the source layer 12
The distance between the (L _gs) and gate layer 14 and the drain layer 1
3 (L _gd ) may be shorter than the design dimension. For example, even if L _gs = L _gd , L _gs > L _gd or L _gs due to misalignment of the mask.
_gs <L _gd . As a result, the gate layer 14 and
There is a problem that the withstand voltage characteristic between the source layer 12 and the drain layer 13 deviates from the designed value, and a predetermined characteristic cannot be obtained, resulting in a large deterioration.

In a current exposure apparatus such as a stepper, a certain degree of pattern misalignment is inevitable. If the distance between the gate layer and the source layer and the drain layer is widened and a margin for misalignment is taken, the resistance value (Ron) between the source and the drain in the J-FET becomes high, and a predetermined high-frequency characteristic is obtained. Is not obtained.

In order to solve the above-mentioned problem, Japanese Patent Laid-Open Publication No. Sho 56 discloses a technique in which a mask for forming a gate layer, a source layer and a drain layer is formed on one mask to reduce the influence of mask misalignment. No. 167322. However, according to this method, the number of masks for forming the gate layer, the source layer, and the drain layer increases, and there is a problem in manufacturing cost.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems. Accordingly, an object of the present invention is to keep the distance between the gate layer and the source layer and the distance between the gate layer and the drain layer substantially constant. An object of the present invention is to provide a method for manufacturing a semiconductor device having a junction field-effect transistor, which has a small variation in withstand voltage characteristics and does not significantly deteriorate, can further reduce the number of masks, and can reduce the manufacturing cost.

[0021]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming a mask layer on a semiconductor substrate having a first conductivity type channel forming region; Providing an opening for introducing impurities for forming a gate layer, a source layer, and a drain layer in the mask layer; and forming a first resist film for protecting the opening for introducing impurities for forming the gate layer. Forming a source layer and a drain layer by introducing the impurity of the first conductivity type into an opening for introducing impurities for forming the source layer and the drain layer; and forming the first resist film The source layer and the drain layer are formed using an exposure mask for formation and a resist material having a photoreaction characteristic that is opposite to the photoreaction characteristic of the resist material for the first resist film. Forming a second resist film for protecting the opening for introducing impurities, and forming a gate layer by introducing impurities of the second conductivity type into the openings for introducing impurities for forming the gate layer. And a process.

The method of manufacturing a semiconductor device according to the present invention is as follows.
After a mask layer is formed over a semiconductor substrate, openings for introducing impurities for forming a gate layer, a source layer, and a drain layer are provided. Next, an opening for introducing impurities for forming a gate layer by forming a first resist film is protected,
An impurity of the first conductivity type is introduced into an impurity introduction opening for forming a source layer and a drain layer to form a source layer and a drain layer. Here, the introduction of the impurity can use diffusion, ion implantation, or the like.
Next, a second resist film is formed using an exposure mask for forming the first resist film and a resist material having a photoreaction characteristic that is opposite to the photoreaction characteristic of the resist material for the first resist film, An opening for introducing impurities for forming the source layer and the drain layer is protected, and an impurity of the second conductivity type is introduced into the opening for introducing impurities for forming the gate layer to form a gate layer.

In the method of manufacturing a semiconductor device according to the present invention, an opening for introducing impurities for forming a gate layer, a source layer, and a drain layer is formed at the same time, thereby eliminating the influence of mask misalignment. The distance between the gate layer and the source layer and the distance between the gate layer and the drain layer can be kept substantially constant. The first resist film for protecting the opening for introducing impurities for forming the gate layer and the second resist film for protecting the opening for introducing impurities for forming the source and drain layers are the same. It can be formed by inverting the photoreaction characteristics of a resist material using an exposure mask. Thus, the number of masks can be reduced, and the manufacturing cost can be reduced.

The method for manufacturing a semiconductor device of the present invention described above
Preferably, the step of providing an opening for introducing impurities for forming a gate layer, a source layer, and a drain layer in the mask layer is a step of providing an opening so as not to expose the semiconductor substrate, After the step of forming the first resist film and before the step of forming the source layer and the drain layer by introducing the first conductivity type impurity, in the opening for introducing impurities for forming the source and drain layers, An exposing step for exposing the semiconductor substrate, wherein after the step of forming the second resist film, before the step of forming the gate layer by introducing the second conductivity type impurity, an impurity for forming the gate layer is formed. A step of exposing the semiconductor substrate at the introduction opening. This makes it possible to sequentially expose the semiconductor substrate in the formation region of the gate layer and the formation region of the source layer and the drain layer, and to introduce the impurities of each conductivity type to form the gate layer, the source layer, and the drain. Layers can be formed.

The method of manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, the step of forming the mask layer is a step of forming a laminate of a first mask layer and a second mask layer, and the step of forming a gate layer, a source layer, and a drain layer on the mask layer. The step of providing an opening that does not expose the semiconductor substrate for introducing impurities is a step of forming an opening that penetrates through the second mask layer and exposes the surface of the first mask layer. This facilitates providing an opening in the mask layer that does not expose the semiconductor substrate.

The method of manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, before the step of forming the mask layer, the method includes a step of introducing the first conductivity type impurity into the semiconductor substrate to form a channel formation region. Thus, a channel formation region can be formed.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first conductivity type source layer and a drain layer on a semiconductor substrate; Forming a mask layer, and etching the semiconductor substrate using the mask layer as a mask, thereby forming the source layer and the drain layer in a convex shape with respect to the semiconductor substrate,
Forming a sidewall mask layer on sidewalls of the source layer and the drain layer that are convex with respect to the semiconductor substrate; and forming a second mask using the sidewall mask layer between the source layer and the drain layer as a mask. And forming a gate layer in a self-aligned manner.

The method of manufacturing a semiconductor device according to the present invention is as follows.
After forming the source layer and the drain layer on the semiconductor substrate, a mask layer is formed on the source layer and the drain layer. Next, the semiconductor substrate is etched using the mask layer as a mask, so that the source layer and the drain layer are formed to have a convex shape with respect to the semiconductor substrate. Next, a sidewall mask layer is formed on side walls of the source layer and the drain layer that are convex with respect to the semiconductor substrate. Next, conductivity type impurities are introduced using the sidewall mask layer as a mask, and a gate layer is formed in a self-aligned manner.

In the method of manufacturing a semiconductor device according to the present invention, the position where the gate layer is formed is formed in a self-aligned manner with respect to the position where the source layer and the drain layer are formed. The distance between the source layer and the distance between the gate layer and the drain layer can be kept substantially constant. Further, since the gate layer is formed in a self-aligned manner by forming the source layer and the drain layer, a resist film for forming an opening for introducing a dopant for forming the gate layer is not required, and the number of masks can be reduced. The manufacturing cost can be reduced.

The method for manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, the step of forming the source layer and the drain layer is a step of forming a source layer and a drain layer by introducing the first conductivity type impurity using a resist film as a mask, and the step of forming the mask layer Is a step of depositing a mask material from above the resist film by a sputtering method. After the step of forming the mask layer, removing the resist film and simultaneously lifting off the mask layer deposited on the resist film. The step of removing by Accordingly, the mask layer can be formed only on the source layer and the drain layer, and the semiconductor substrate in a region other than the source layer and the drain layer can be exposed.

The method of manufacturing a semiconductor device according to the present invention described above
Preferably, after the step of forming the source layer and the drain layer in a convex shape with respect to the semiconductor substrate, and before the step of forming the sidewall mask layer, the channel formation region of the first conductivity type is formed. Or before the step of forming the source layer and the drain layer,
Forming a channel formation region of the first conductivity type. Thus, a channel formation region can be formed.

[0032]

Embodiments of a semiconductor device according to the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1 is a sectional view of a semiconductor device according to this embodiment. An n-type channel formation region 11 is provided in a semi-insulating GaAs semiconductor substrate 10 in a region separated by element isolation such as a boron ion implantation layer (not shown), and an n ⁺ -type source layer 12 and a drain layer are provided at both ends thereof. 13 are formed. A p ⁺ -type gate layer 14 is formed in the center of the channel formation region 11, thereby forming a junction field-effect transistor (J-FET).

A second insulating film 21, a third insulating film 22, and a fourth insulating film 23 are formed on the semiconductor substrate 10, respectively, and have openings reaching the gate layer 14, the source layer 12, and the drain layer 13. And a metal electrode 30 is formed.

In the semiconductor device having such a structure, the gate layer 14
Device having a junction field-effect transistor, in which the distance between the gate and source layers 12 and the distance between the gate layer 14 and the drain layer 13 are kept substantially constant, the variation in breakdown voltage characteristics is small, and there is no significant deterioration. It is.

Next, a method of manufacturing the semiconductor device of the present embodiment will be described. First, as shown in FIG. 2A, a first insulating film 20 is formed by depositing silicon nitride on a semi-insulating GaAs semiconductor substrate 10 by, for example, a CVD method.

Next, as shown in FIG. 2B, the resist film R1 is patterned and as a mask, dopant ions D1 such as silicon ions and magnesium ions are implanted into the pattern openings, and n-type impurities are introduced into the semiconductor substrate. The channel forming region 11 is formed.

Next, as shown in FIG. 2C, after removing the resist film R1, the first insulating film 20 is removed by etching such as RIE (reactive ion etching). Thereafter, an annealing process is performed to activate the ions implanted into the channel formation region 11.

Next, as shown in FIG.
20-30 n of silicon oxide is deposited thereon by, for example, CVD.
The second insulating film 21 is formed by depositing with a thickness of m, and the third insulating film 22 is formed by depositing silicon nitride thereon by, for example, a CVD method. A resist film R2 is formed on the third insulating film 22 and patterned so as to open regions where gate layers, source layers, and drain layers are formed.

Next, as shown in FIG. 3E, dry etching such as RIE is performed using the resist film R2 as a mask, and the third insulating film 22 is formed in the formation regions of the gate layer, the source layer, and the drain layer. Is formed to penetrate through and expose the surface of the second insulating film 21.

Next, as shown in FIG. 3 (f), the resist film R2 is removed, a new resist film R3 is formed, the opening of the gate layer formation region is protected, and the source layer and the drain layer are protected. Patterning is performed to expose the formation region.

Next, as shown in FIG.
The second upper layer of the source and drain layer formation regions exposed by the resist film R3 by hydrofluoric acid-based wet etching such as O-1 (18 buffered hydrofluoric acid / a mixture of hydrofluoric acid and ammonium fluoride) The insulating film 21 is selectively removed to expose the semiconductor substrate 10.

Next, as shown in FIG. 4 (h), after removing the resist film R3, an n-type dopant D2 such as Se is diffused from the openings of the source and drain layer formation regions, and n ⁺ A source layer 12 and a drain layer 13 are formed.

Next, as shown in FIG.
Silicon nitride is deposited to a thickness of 20 to 30 nm by the VD method to form a fourth insulating film 23, and a resist film R4 is formed thereon to protect the openings in the source and drain layer formation regions. Patterning is performed so as to expose the formation region of the gate layer. At this time, an exposure mask for forming the resist film R3 is used as an exposure mask for patterning the resist film R4. However, as the resist material, it is necessary to use a material in which the negative type and the positive type are reversed and the photoreaction characteristics are inverted.

Next, as shown in FIG. 5 (j), dry etching such as RIE is performed to remove the second insulating film 21 and the fourth insulating film 23 in the upper layer of the gate layer, exposing the semiconductor substrate 10. Let it. At this time, the side wall insulating film 23a is formed in the opening of the third insulating film 22 in the gate layer formation region.
And the opening for introducing the dopant for forming the gate layer can be narrowed.

Next, as shown in FIG. 5 (k), after removing the resist film R4, a p-type dopant D3 such as Zn is used.
To form a p ⁺ -type gate layer 14.

Next, a resist film is formed, patterned and etched by RIE or the like, and an opening for exposing the surface of the source layer 12 and the drain layer 13 is formed in the fourth insulating film 23. After removing the film, a metal electrode 30 connected to the gate layer 14, the source layer 12, and the drain layer 13 is formed to reach the semiconductor device shown in FIG.

According to the above-described method for manufacturing a semiconductor device, the openings for introducing the dopants for forming the gate layer 14, the source layer 12, and the drain layer 13 are formed at the same time by using one mask. The distance between the gate layer 14 and the source layer 12 and the distance between the gate layer 14 and the drain layer 13
It is possible to manufacture a semiconductor device having a junction field-effect transistor, in which the distance between them is kept substantially constant, the variation in breakdown voltage characteristics is small, and there is no significant deterioration. Further, a resist film forming an opening for introducing a dopant for forming the source layer 12 and the drain layer 13 and a resist film forming an opening for introducing a dopant for forming the gate layer 14 are formed using the same mask. Since it is formed, the cost can be reduced by reducing the number of masks.

In the semiconductor device of this embodiment, instead of forming a gate layer by introducing a dopant, a MESFET (Meta
l-Semiconductor Schottky junction field effect transistor) can be formed.

Second Embodiment FIG. 6 is a sectional view of a semiconductor device according to this embodiment. An n-type channel formation region 11 is provided in a semi-insulating GaAs semiconductor substrate 10 in a region separated by element isolation such as a boron ion implantation layer (not shown), and an n ⁺ -type source layer 12 and a drain layer are provided at both ends thereof. 13 are formed. A p ⁺ -type gate layer 14 is formed in the center of the channel formation region 11, thereby forming a junction field-effect transistor (J-FET).

On the semiconductor substrate 10, a side wall insulating film 25a and a third insulating film 26 are respectively formed, and the gate layer 14, the source layer 12, and the drain layer 1 are formed.
3 is provided and the metal electrode 31 is provided.
a, 32 are formed.

In the semiconductor device having such a structure, the gate layer 14
Device having a junction field-effect transistor, in which the distance between the gate and source layers 12 and the distance between the gate layer 14 and the drain layer 13 are kept substantially constant, the variation in breakdown voltage characteristics is small, and there is no significant deterioration. It is.

Next, a method of manufacturing the semiconductor device of the present embodiment will be described. First, as shown in FIG. 7A, a resist film R is formed on a semi-insulating GaAs semiconductor substrate 10.
5 is patterned and a mask is used to implant n-type dopant ions D4 such as silicon ions into the pattern openings to form n ⁺ -type source layers 12 and drain layers 13 in the semiconductor substrate.

Next, as shown in FIG. 7B, silicon nitride is deposited by, for example, a sputtering method, and a first insulating film 24 is formed on the pattern opening of the resist film R4 and on the resist film R4.

Next, as shown in FIG. 7C, the resist film R5 is removed, and the first insulating film 24 formed on the resist film R4 is removed by lift-off.

Next, as shown in FIG.
The source layer 12 and the drain layer 13 are formed on the substrate 10 by etching using an etchant having a selectivity between the semiconductor substrate 10 and the first insulating film 24 of silicon nitride, or by etching the surface of the semiconductor substrate 10 by ion milling or the like. It is formed in a convex shape.

Next, as shown in FIG. 8E, a resist film R6 is formed on the semiconductor substrate 10 and is patterned so as to open a portion to be a channel formation region, and the resist film R6 is used as a mask. A dopant ion D5 such as silicon ion and magnesium ion is implanted into the pattern opening, and an n-type channel formation region 11 is formed in the semiconductor substrate.

Next, as shown in FIG. 8F, after removing the resist film R6, the first insulating film 20 is removed by etching such as RIE (reactive ion etching). Thereafter, an annealing process is performed to activate the ions implanted into the channel formation region 11, the source layer 12, and the drain layer 13.

Next, as shown in FIG.
The second insulating film 25 is formed by depositing silicon nitride on the entire surface by the VD method.

Next, as shown in FIG.
Etch back is performed on the entire surface of the source layer 12 and the drain layer 13 by dry etching such as IE, leaving a sidewall shape of a portion of the source layer 12 and the drain layer 13 protruding from the surface of the semiconductor substrate, thereby forming a side wall insulating film 25a.
At this time, the distance sandwiched by the sidewall insulating films 25a between the source layer 12 and the drain layer 13 is JF.
Since the gate length of the ET is set, the etching process is controlled so as to have a desired length.

Next, as shown in FIG. 9I, a p-type dopant D 6 such as Zn is diffused over the entire surface to form a p ⁺ -type gate layer 14. At this time, p ⁺ -type regions 12 ′, 13 ′, and 14 ′ are also formed in the upper portions of the source layer 12 and the drain layer 13 which are not used as gate layers and in the semiconductor substrate. The gate layer 14 is formed in a self-aligned manner between the source layer 12 and the drain layer 13 in a region sandwiched by the side wall insulating films 25a.

Next, as shown in FIG.
Pt / Au is vapor-deposited to form a gate electrode layer 31, a resist film R7 is formed thereover and patterned into a gate electrode pattern.

Next, as shown in FIG. 10K, the gate electrode layer 31 is etched by, for example, ion milling using the resist film R7 as a mask.
a is formed. At this time, the upper portions of the source layer 12 and the drain layer 13 and the p ⁺ -type regions 12 ′, 13 ′, and 14 ′ in the semiconductor substrate, which are formed simultaneously with the formation of the gate layer 14, are simultaneously etched and removed.

Next, after removing the resist film R7, silicon nitride is deposited by, for example, a CVD method to form an interlayer insulating film 26. Next, a resist film is formed, patterned and etched by RIE or the like to form an interlayer insulating film 2.
6, an opening for exposing the surfaces of the source layer 12 and the drain layer 13 is formed, and after removing the resist film, a metal electrode 32 connected to the source layer 12 and the drain layer 13 is formed. To the device.

According to the above-described method of manufacturing a semiconductor device, the position where the gate layer 14 is formed is formed in a self-aligned manner with respect to the position where the source layer 12 and the drain layer 13 are formed. A semiconductor having a junction field-effect transistor, in which the distance between the source layer 12 and the gate layer 14 and the distance between the gate layer 14 and the drain layer 13 are kept substantially constant, the variation in breakdown voltage characteristics is small, and there is no significant deterioration. The device can be manufactured. In addition, since the gate layer is formed in a self-aligned manner by forming the source layer 12 and the drain layer 13, the gate layer 14 is formed.
This eliminates the need for a resist film for forming an opening for introducing a dopant for forming a mask, and can reduce the number of masks and cost.

In the semiconductor device of this embodiment, instead of forming a gate layer by introducing a dopant, a MESFET (Meta
l-Semiconductor Schottky junction field effect transistor) can be formed.

The semiconductor device and the method of manufacturing the same according to the present invention
It is not limited to the above embodiment. For example, in this embodiment, a semiconductor device having an n-channel junction field effect transistor structure is described, but a p-channel junction field effect transistor structure may be used. In the case of the n-channel type and the p-channel type, the n-type impurity and the p-type impurity may be exchanged. In addition, various changes can be made without departing from the gist of the present invention.

[0068]

According to the semiconductor device of the present invention, the distance between the gate layer and the source layer and the distance between the gate layer and the drain layer are kept substantially constant. In addition, a semiconductor device having a junction field effect transistor can be manufactured.
Further, the number of masks can be reduced, and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIGS. 2A and 2B are cross-sectional views illustrating a manufacturing process of a method for manufacturing a semiconductor device according to a first embodiment of the present invention, wherein FIG. 2A is a diagram up to a process of forming a first insulating film, and FIG. (C) shows up to the ion implantation step for formation and up to the annealing step.

FIG. 3 shows a step subsequent to that of FIG. 2; (d) shows a step until a step of forming a resist film for forming an opening for introducing a dopant for forming a gate layer, a source layer, and a drain layer; (E) shows up to the step of forming an opening for introducing a dopant into the gate layer, the source layer and the drain layer in the third insulating film, and (f) shows up to the step of forming a resist film for protecting the gate layer formation region.

4 shows a step subsequent to that of FIG. 3; FIG. 4 (g) shows a step until a step of removing a second insulating film in a formation region of a source layer and a drain layer; Until the step of forming the drain layer, (i) shows up to the step of forming a resist film for protecting the source and drain layer formation regions.

FIG. 5 shows a step subsequent to that of FIG. 4; (j) shows a step until a step of removing a second insulating film and a fourth insulating film in a gate layer forming region; and (k) shows a step of removing a gate layer by introducing a dopant. The steps up to the formation step are shown.

FIG. 6 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIGS. 7A and 7B are cross-sectional views illustrating a manufacturing process of a method for manufacturing a semiconductor device according to a second embodiment of the present invention. FIG. 7A illustrates a process of forming a source layer 12 and a drain layer 13 by introducing a dopant. (B) shows the process up to the step of forming the first insulating film.
(C) shows the process up to the step of removing the first insulating film in the upper layer portion of the source layer and the drain layer.

8 shows a step subsequent to that of FIG. 7; (d) shows up to an etching step of a semiconductor substrate; (e) shows up to an ion implantation step for forming a channel formation region; and (f) shows an annealing step. Up to

FIG. 9 shows a step that follows the step shown in FIG. 8;
(H) shows up to the step of forming a sidewall insulating film, and (i) shows up to the step of forming a gate layer by introducing a dopant.

10 shows a step subsequent to that of FIG. 9; (j) shows a step of forming a resist film for gate electrode patterning; and (k) shows a step of patterning the gate electrode.

FIG. 11 is a sectional view of a conventional semiconductor device.

FIGS. 12A and 12B are cross-sectional views showing a manufacturing process of a conventional method of manufacturing a semiconductor device, in which FIG. 12A shows a process until a first insulating film is formed, and FIG. 12B shows a process for forming a source layer and a drain layer. (C) shows up to the ion implantation step for forming the channel formation region.

FIG. 13 shows a step that follows the step shown in FIG. 12, and (d)
(E) to the step of forming a resist film in which an opening for introducing the dopant of the gate layer is patterned into the third insulating film, and (f) shows the step of introducing the dopant of the gate layer into the second insulating film. Up to the step of forming an opening for the purpose.

FIG. 14 shows a step that follows the step of FIG. 13, and (g)
Is a step of forming a third insulating film; (h) is a step of forming an opening exposing a semiconductor substrate for introducing a dopant of a gate layer; and (i) is a step of introducing a dopant for forming a gate layer. Up to

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 11 ... Channel formation region, 12 ... Source layer, 13 ... Drain layer, 14 ... Gate layer, 20 ... First insulating film, 21 ... Second insulating film, 22 ... Third insulating film, 23
... 4th insulating film, 23a ... sidewall insulating film, 24 ...
First insulating film, 25: second insulating film, 25a: sidewall insulating film, 26: interlayer insulating film, 27: first insulating film, 28
... second insulating film, 29 ... third insulating film, 29a ... sidewall insulating film, 30 ... metal electrode, 31 ... gate electrode layer,
31a gate electrode, 32 metal electrode, 33 metal electrode, R1 to R10 resist film, D1 to D9 dopant.

Claims (8)

[Claims] 1. A step of forming a mask layer on a semiconductor substrate having a channel formation region of a first conductivity type, and an opening for introducing impurities for forming a gate layer, a source layer, and a drain layer in the mask layer. Providing a portion, forming a first resist film that protects an opening for introducing impurities for forming the gate layer, and opening for introducing impurities for forming the source and drain layers. Forming a source layer and a drain layer by introducing the impurity of the first conductivity type into the substrate; exposing an exposure mask for forming the first resist film; and inverting the photoreaction characteristics of the resist material for the first resist film. Forming a second resist film that protects an opening for introducing impurities for forming the source layer and the drain layer by using a resist material having photoreaction characteristics to be formed; The method of manufacturing a semiconductor device and a step of introducing a second conductivity type impurity into the opening for impurity introduction for forming over coat layer to form a gate layer. 2. The step of providing an opening for introducing impurities for forming a gate layer, a source layer, and a drain layer in the mask layer is a step of providing an opening so as not to expose the semiconductor substrate. After the step of forming the first resist film and before the step of forming the source and drain layers by introducing the first conductivity type impurity, an opening for introducing impurities for forming the source and drain layers is formed. The step of exposing the semiconductor substrate in the step of forming the gate layer after the step of forming the second resist film and before the step of forming the gate layer by introducing the second conductivity type impurity. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of exposing said semiconductor substrate at an opening for introducing impurities. 3. The step of forming the mask layer is a step of forming a laminate of a first mask layer and a second mask layer, and forming a gate layer, a source layer, and a drain layer on the mask layer. 3. The step of providing an opening that does not expose the semiconductor substrate for introducing impurities according to claim 2, is a step of forming an opening that penetrates the second mask layer and exposes a surface of the first mask layer. A method for manufacturing a semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming the channel formation region by introducing the first conductivity type impurity into the semiconductor substrate before the step of forming the mask layer. 5. A step of forming a first conductivity type source layer and a drain layer on a semiconductor substrate, a step of forming a mask layer on the source layer and the drain layer, and the semiconductor substrate using the mask layer as a mask. Forming the source layer and the drain layer in a convex shape with respect to the semiconductor substrate by etching the semiconductor substrate; and forming a side surface on the side wall of the source layer and the drain layer in the convex shape with respect to the semiconductor substrate. A semiconductor comprising: a step of forming a wall mask layer; and a step of introducing a second conductivity type impurity using the sidewall mask layer between the source layer and the drain layer as a mask to form a gate layer in a self-aligned manner. Device manufacturing method. 6. The step of forming the source layer and the drain layer is a step of forming the source layer and the drain layer by introducing the first conductivity type impurity using a resist film as a mask. The step is a step of depositing a mask material from above the resist film by a sputtering method.After the step of forming the mask layer, removing the resist film and simultaneously removing the mask layer deposited on the resist film 6. The method for manufacturing a semiconductor device according to claim 5, further comprising a step of removing by lift-off. 7. The method according to claim 1, wherein after the step of forming the source layer and the drain layer in a convex shape with respect to the semiconductor substrate and before the step of forming the sidewall mask layer, the channel formation region of the first conductivity type is formed. 6. The method for manufacturing a semiconductor device according to claim 5, further comprising a step of forming. 8. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of forming said first conductivity type channel formation region before said step of forming said source layer and said drain layer.