KR19990057406A - Manufacturing Method of Top Gate Thin Film Transistor - Google Patents

Abstract

The present invention relates to a method for manufacturing a top gate thin film transistor.

The formation of LDD regions with thin junctions can reduce leakage currents.However, when forming top gate thin film transistors, the thickness of the channel is so thin that LDD regions cannot be formed with thin junctions to reduce leakage currents. There is a problem that the reliability of the device is thereby deteriorated.

In the present invention, when the oxide film spacer is formed in the portion where the LDD region is to be formed and the impurity ion implantation process is performed to form the source and drain regions of the thin film transistor, the impurity that has passed through the spacer forms the LDD region of the thin junction, thereby reducing leakage current. This reduces the reliability of the device.

Description

Manufacturing Method of Top Gate Thin Film Transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor (TFT), and more particularly, a method of manufacturing a top gate type thin film transistor capable of reducing a leakage current by forming an LDD region with a thin junction. It is about.

The formation of LDD regions with thin junctions can reduce leakage currents.However, when forming top gate thin film transistors, the thickness of the channel is so thin that LDD regions cannot be formed with thin junctions to reduce leakage currents. There is a problem that the reliability of the device is thereby deteriorated.

Accordingly, an object of the present invention is to provide a method of manufacturing a top gate type thin film transistor which can reduce the leakage current by forming an LDD region by a thin junction.

According to an aspect of the present invention, an insulating film and an amorphous silicon film are sequentially formed on a semiconductor substrate on which a plurality of substructures are formed, and the first polysilicon film is formed by crystallizing the amorphous silicon film. Patterning a silicon film to determine a channel region; sequentially forming a gate oxide film and a second polysilicon film in a selected region on the first polysilicon film; forming a gate structure; and forming a spacer on the sidewall of the gate structure. After the formation of the impurity ion implantation process, a thin junction LDD region is formed on the first polysilicon film under the spacer, and a source and a drain region are formed on the exposed first polysilicon film; Characterized in that it comprises a step of removing.

1 (a) to 1 (e) are cross-sectional views of devices for explaining a method for manufacturing a top gate type thin film transistor according to the present invention.

<Description of the symbols for the main parts of the drawings>

11 semiconductor substrate 12 insulating film

13: amorphous silicon film 14: first polysilicon film

15 gate oxide film 16 second polysilicon film

17 spacer 18 LDD region

19a: source region 19b: drain region

The present invention will be described in detail with reference to the accompanying drawings.

1 (a) to 1 (e) are cross-sectional views of devices for explaining a method of manufacturing a top gate thin film transistor according to the present invention.

Referring to FIG. 1A, an insulating film 12 is formed on a semiconductor substrate 11 on which a driving transistor, a V _SS line (not shown), and the like are formed. The insulating film 12 is formed thick with a CVD oxide film or the like. An amorphous silicon film 13 is formed on the insulating film 12 by LPCVD. The amorphous silicon film 13 is formed using SiH ₄ or Si ₂ H ₆ at a temperature of 450 to 570 ° C., and is formed to a thickness of 200 to 1000 kHz in consideration of the characteristics of the thin film transistor.

Referring to FIG. 1B, the amorphous silicon film 13 is crystallized to form a first polysilicon film 14 having a large grain size. The first polysilicon film 14 is formed by performing an annealing process on the amorphous silicon film 13 at a temperature of 600 to 800 ° C. in an N ₂ atmosphere for 4 to 10 hours. The first polysilicon film 14 is patterned to form channel portions.

In this case, when the thermal oxide film is grown on the amorphous silicon film 13, the crystallization process may be omitted, and the crystallization process is performed in consideration of the thickness loss when the amorphous silicon film 13 is oxidized to SiO ₂ . Form thickly. In this case, when the oxide is oxidized using hydrogen and oxygen gas at 900 to 1200 ° C., the gate oxide film is formed and at the same time, the channel also undergoes solid phase crystallization and polysiliconizes.

Referring to FIG. 1C, a gate oxide film 15 is formed on the first polysilicon film 14, and a second polysilicon film 16 is formed on the gate oxide film 15 by LPCVD. The gate oxide film 15 is HTO deposited at a temperature of 750 to 800 ° C. and is deposited to a thickness of 200 to 1000 Å in consideration of the characteristics of the thin film transistor. Selected regions of the second polysilicon film 16 and the gate oxide film 15 are removed to form a gate electrode.

Referring to FIG. 1 (d), a spacer 17 is formed on the sidewall of the gate structure by depositing an oxide film such as TEOS or MTO on the entire structure and etching the entire surface thereof. The spacers 17 are formed to have a thickness that allows the LDD region to be formed by a thin junction through the oxide film when performing the ion implantation process for forming the source / drain of the thin film transistor. When the PMOS thin film transistor is formed, a thin junction LDD region 18 is formed in the first polysilicon layer 14 under the spacer 17 by implanting B or BF ₂ ions and exposing the exposed first polysilicon layer ( 14 is implanted with ions as a whole to form source and drain regions 19a and 19b. In this case, the gate electrode is also doped with B ions to lower the work function to improve the characteristics of the device.

FIG. 1E is a cross-sectional view of a device in which a spacer 17 is removed by wet etching to fabricate a top gate thin film transistor.

As another embodiment of the present invention, the spacer is formed only on the sidewalls of the gate electrode on the side where the drain is to be formed, and then an ion implantation process is performed to form the LDD region with a thin junction only on the part where the drain is to be formed, and on the part where the source is to be formed. If the subsequent heat treatment process is performed without forming the LDD region, the source region may overlap and the drain region may be offset to increase the on / off ratio of the thin film transistor.

As described above, according to the present invention, the LDD region can be formed by a thin junction, thereby reducing the leakage current and improving the reliability of the device.

Claims (3)

Sequentially forming an insulating film and an amorphous silicon film on the semiconductor substrate having a plurality of substructures; Crystallizing the amorphous silicon film to form a first polysilicon film, and then patterning the first polysilicon film to determine a channel region; Forming a gate structure by sequentially forming a gate oxide film and a second polysilicon film in a selected region over the first polysilicon film; After the spacer is formed on the sidewall of the gate structure, an impurity ion implantation process is performed to form a thin junction LDD region on the first polysilicon film under the spacer, and a source and a drain region are formed on the exposed first polysilicon film. Step being made, And removing the spacers. The method of claim 1, wherein the first polysilicon film is formed by annealing the amorphous silicon film at a temperature of 600 to 800 ° C. for 4 to 10 hours in a nitrogen atmosphere. . The method of claim 1, wherein the spacer is formed of an oxide film.