JPS6317227B2 - - Google Patents
Info
- Publication number
- JPS6317227B2 JPS6317227B2 JP56062882A JP6288281A JPS6317227B2 JP S6317227 B2 JPS6317227 B2 JP S6317227B2 JP 56062882 A JP56062882 A JP 56062882A JP 6288281 A JP6288281 A JP 6288281A JP S6317227 B2 JPS6317227 B2 JP S6317227B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- layer
- isolation
- field effect
- ion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 14
- 238000002955 isolation Methods 0.000 claims description 13
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 8
- 230000005669 field effect Effects 0.000 claims 3
- 230000000873 masking effect Effects 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 150000002500 ions Chemical class 0.000 description 12
- 238000010438 heat treatment Methods 0.000 description 10
- 238000005468 ion implantation Methods 0.000 description 8
- 238000002513 implantation Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- -1 oxygen ions Chemical class 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
Description
【発明の詳細な説明】
本発明は、半導体素子の分離方法にかかり、集
積回路の集積素子間を電気的に分離する方法を提
供しようとするものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for isolating semiconductor elements, and is intended to provide a method for electrically isolating integrated elements of an integrated circuit.
集積回路を同一の基板を用いて製造する場合、
各々の能動素子あるいは受動素子を電気的に分離
する必要がある。これら集積素子を分離すること
は、直接集積回路の特性に結びつくため、より完
全な分離方法が望まれている。たとえばシリコン
基板を用いた集積回路においては、通常、ｐ−ｎ
接合による分離方法が用いられている。しかし、
ｐ−ｎ接合による分離においては、接合面に接合
容量が存在するため、これら分離された領域には
容量が存在することになる。このため、集積回路
としての動作速度は、本来の半導体装置の動作速
度に制限を与える。 When manufacturing integrated circuits using the same substrate,
It is necessary to electrically isolate each active or passive element. Since separating these integrated elements directly affects the characteristics of the integrated circuit, a more complete separation method is desired. For example, in integrated circuits using silicon substrates, p-n
A separation method by bonding is used. but,
In isolation by a pn junction, since junction capacitance exists at the junction surface, capacitance exists in these separated regions. Therefore, the operating speed of the integrated circuit imposes a limit on the operating speed of the original semiconductor device.
このようなｐ−ｎ接合による分離では、接合容
量を避けることが不可能なため、最近では、絶縁
性基板上に単結晶Si層をエピタキシヤル成長させ
るなどした、SOSと呼ばれる集積回路方式があ
る。しかし、この方式の場合には、集積素子の底
部は絶縁基板となり、縦方向の接合容量はない
が、横方向の分離はやはりｐ−ｎ接合が用いら
れ、電気的に不安定な分離方法が用いられてい
る。 Since it is impossible to avoid junction capacitance in isolation using such p-n junctions, recently there is an integrated circuit method called SOS that uses epitaxial growth of a single crystal Si layer on an insulating substrate. . However, in this method, the bottom of the integrated device is an insulating substrate, and although there is no vertical junction capacitance, a p-n junction is still used for horizontal isolation, which is an electrically unstable isolation method. It is used.
最近では、きわめて高抵抗の単結晶基板が、
GaAs結晶にCrなどの添加によつて得られ、Siに
比べて電子移動度が数倍も大きいことなどから、
高速動作の集積回路として強く期待されはじめ
た。しかし、このような半絶縁性のGaAs基板を
用いた場合、基板の抵抗が、熱処理など、高温処
理によつて低くなることが知られていて、場合に
よつては、熱処理によつて１×1016〜８×1016cm
-3のキヤリア濃度の薄い層が基板表面に生じる場
合があり、そのため素子間分離が不可能となる。 Recently, extremely high resistance single crystal substrates have been developed.
It is obtained by adding Cr etc. to GaAs crystal, and its electron mobility is several times higher than that of Si.
High expectations began to emerge as a high-speed integrated circuit. However, when such a semi-insulating GaAs substrate is used, it is known that the resistance of the substrate decreases due to high temperature treatment such as heat treatment, and in some cases, the resistance of the substrate decreases by 1× due to heat treatment. 10 16 ~ 8×10 16 cm
A thin layer with a -3 carrier concentration may be formed on the substrate surface, making isolation between devices impossible.
集積素子間の分離方法として、イオン注入を用
いる方法がある。この方法は、所定のイオンを高
エネルギーで基板に注入し、注入領域に注入損傷
を形成し、格子欠陥の生成によつて高抵抗化をは
かるか、もしくは、半導体中で深い準位を形成す
る不純物イオン種を注入し、熱処理などによつて
活性化して残留キヤリアを補償するなどによるも
のである。しかし、これらイオン注入によつて素
子分離を行う場合、処理温度に十分注意する必要
があり、格子欠陥を用いた場合には、再結晶化の
温度に制約があるため、最適な条件を決定する方
法があり、また条件が大きく限られる。 As a method for separating integrated elements, there is a method using ion implantation. This method involves implanting specific ions into the substrate at high energy, forming implantation damage in the implanted region, and increasing the resistance by creating lattice defects or forming deep levels in the semiconductor. This is done by implanting impurity ion species and activating them through heat treatment or the like to compensate for residual carriers. However, when performing element isolation using these ion implantations, it is necessary to pay close attention to the processing temperature, and when using lattice defects, there are restrictions on the recrystallization temperature, so it is necessary to determine the optimal conditions. There are many methods, and the conditions are very limited.
本発明は、集積される個々の素子を所定の形状
あるいは条件で製造し、高温処理を終えた後、イ
オン注入による分離を行い、その後の製造過程で
高抵抗層が低抵抗層に変質しないように配慮する
ことによつて、上述の問題点を解決したものであ
る。 In the present invention, individual elements to be integrated are manufactured in a predetermined shape or under predetermined conditions, and after high-temperature treatment, separation is performed by ion implantation to prevent high-resistance layers from deteriorating into low-resistance layers during the subsequent manufacturing process. The above-mentioned problems are solved by taking into consideration the following.
以下、その一実施例について、図面を用いて詳
述する。第１図は、たとえばCrドープの半絶縁
性GaAs基板１の所定の領域４を活性化し、FET
などの動作領域を形成する場合を示している。基
板１上に、Si3N4膜などの絶縁膜２を被着する。
その後、レジスト層３を成形し、図に示すように
領域４上の部分を取り除く。Siイオンあるいは
Seイオンをイオン注入などで混入し、熱処理を
行なつて、それらのイオンを活性化してｎ領域を
形成する。このとき、第２図に示すように、熱処
理後、半絶縁性である基板１の表面の抵抗が下が
り、熱変成層と呼ばれる導電層６が発生する場合
がある。これらの熱変成層６は、800℃、30分程
度の通常の熱処理においては、表面より0.3〜
0.5μｍ程度の深さで形成される。なお、第２図に
は絶縁膜２′を用いて熱処理した場合を示したが、
この絶縁膜２′によつて、熱変成層６の状態は大
きく変わる。つづいて、第３図に示すように、金
属とのオーム性接触電極を形成するために、絶縁
膜２′を選択エツチしてから、ソースおよびドレ
イン領域５をSiイオン150KeV、１×1014cm-2の
注入で形成する。なお、３′はレジスト層である。
さらに、第４図に示すように領域５の形成後、高
温の熱処理が行なわれるが、この高温処理によつ
て絶縁膜２′の厚みが増大する。そして、この処
理で熱変成層６はさらに低抵抗となる場合があ
る。しかしながら、領域４、領域５は、熱処理条
件などであらかじめ設計された構造あるいはキヤ
リア濃度分布を有する。この状態では、導電層６
のために素子間の分離が不完全となり、この状態
で金属配線を行なつても集積回路の動作、当初予
定された特性を示さない。したがつて、第５図に
示すように、形成された動作領域を、レジスト層
３″および絶縁膜２′をストツパーとして、Neイ
オン注入８を行ない、導電層６を含む領域に注入
層７を形成する。この時、注入条件は、150KeV
で、１×1016cm-2であるが、熱変成層６を含む領
域にNe飛程を合わせる。注入層７によつて、抵
抗が再び高くなり、素子間分離が完全に行なわれ
る。しかし、このような方法によつて形成した注
入層７の絶縁性は熱的に不安定である。たとえば
プロトン注入では、600℃以上で絶縁性が維持さ
れない、あるいは、酸素イオンを用いた場合に
は、約700℃以上で絶縁性が維持されない。しか
し、第５図に示される後のプロセスは、通常500
℃以下の温度で行なわれる。たとえば、オーミツ
ク電極形成の合金処理は、500℃程度で数分間で
あり、シヨツトキー電極の熱処理においても400
℃での温度で十数分で行なわれる。したがつて、
第５図に示されるイオン注入層７の絶縁性は十分
に保たれ、良好な素子間分離が可能となる。 Hereinafter, one embodiment will be described in detail with reference to the drawings. In FIG. 1, for example, a predetermined region 4 of a Cr-doped semi-insulating GaAs substrate 1 is activated and an FET is activated.
This shows the case of forming an operating area such as . An insulating film 2 such as a Si 3 N 4 film is deposited on a substrate 1 .
Thereafter, the resist layer 3 is formed and the portion on the region 4 is removed as shown in the figure. Si ion or
Se ions are mixed in by ion implantation or the like, and heat treatment is performed to activate these ions and form an n region. At this time, as shown in FIG. 2, after the heat treatment, the resistance of the surface of the semi-insulating substrate 1 decreases, and a conductive layer 6 called a thermally transformed layer may be generated. In normal heat treatment at 800°C for about 30 minutes, these thermally altered layers 6 have a thickness of 0.3 to
It is formed at a depth of about 0.5 μm. Note that although FIG. 2 shows the case of heat treatment using the insulating film 2',
This insulating film 2' greatly changes the state of the thermally altered layer 6. Subsequently, as shown in FIG. 3, in order to form an ohmic contact electrode with the metal, the insulating film 2' is selectively etched, and the source and drain regions 5 are etched with Si ions at 150 KeV and 1×10 14 cm. Formed by injection of -2 . Note that 3' is a resist layer.
Further, as shown in FIG. 4, after the formation of the region 5, a high temperature heat treatment is performed, and this high temperature treatment increases the thickness of the insulating film 2'. This treatment may further reduce the resistance of the thermally altered layer 6. However, regions 4 and 5 have structures or carrier concentration distributions designed in advance based on heat treatment conditions and the like. In this state, the conductive layer 6
Therefore, isolation between elements becomes incomplete, and even if metal wiring is performed in this state, the operation of the integrated circuit will not exhibit the originally planned characteristics. Therefore, as shown in FIG. 5, Ne ion implantation 8 is performed in the formed operating region using the resist layer 3'' and the insulating film 2' as stoppers, and an implantation layer 7 is formed in the region including the conductive layer 6. At this time, the implantation conditions are 150KeV
The Ne range is 1×10 16 cm −2 , but the Ne range is adjusted to the region including the thermally altered layer 6. The injection layer 7 increases the resistance again and completes the isolation between the devices. However, the insulation of the injection layer 7 formed by such a method is thermally unstable. For example, with proton implantation, insulation is not maintained at temperatures above 600°C, or when oxygen ions are used, insulation is not maintained at temperatures above approximately 700°C. However, the later process shown in Figure 5 typically requires 500
It is carried out at temperatures below ℃. For example, alloy treatment for forming ohmic electrodes takes several minutes at approximately 500°C, and heat treatment for shot key electrodes takes approximately 400°C.
It is carried out in a few minutes at a temperature of °C. Therefore,
The insulation of the ion-implanted layer 7 shown in FIG. 5 is sufficiently maintained, allowing good isolation between elements.
上述の実施例では、素子間分離のためのイオン
注入にNeイオンを用いたが、Neを含め、希ガス
イオンは半導体中でも電気的に活性化しないた
め、本発明の目的にかなうものである。また、希
ガスイオンに限らず、半導体中で電気的に活性化
する不純物イオンを注入しても、その活性化エネ
ルギーが半導体装置の動作領域を形成する不純物
イオンの活性化エネルギーよりも高ければ、同様
に本発明の目的にかない、素子間分離に利用する
ことができる。 In the above-described embodiment, Ne ions were used for ion implantation for isolation between elements, but rare gas ions, including Ne, are not electrically activated even in semiconductors, and thus meet the purpose of the present invention. Furthermore, even if impurity ions that are electrically activated in the semiconductor are implanted, not just rare gas ions, if the activation energy is higher than the activation energy of the impurity ions that form the operating region of the semiconductor device, Similarly, it can be used for isolation between elements, which meets the purpose of the present invention.
以上説明したように、本発明の方法は、各々の
集積素子の動作領域を形成した後、この集積素子
の動作領域を除く他の領域にイオン注入をするこ
とによつて、従来の方法では熱的安定性で問題の
あつたイオン注入法を用いて、完全な素子分離を
することができる。 As explained above, in the method of the present invention, after forming the operating area of each integrated element, ions are implanted into other areas of the integrated element other than the operating area, thereby eliminating the heat generated by conventional methods. Complete device isolation can be achieved using the ion implantation method, which has had problems with physical stability.
第１図ないし第５図は本発明の半導体素子の分
離方法の一実施例を説明するための図である。
１……半絶縁性GaAs基板、２，２′……絶縁
膜、３，３′，３″……レジスト膜、４……ｎ領
域、５……ソース、ドレイン領域、６……熱変成
層、７……注入層、８……イオン注入。
1 to 5 are diagrams for explaining one embodiment of the method for separating semiconductor elements according to the present invention. 1... Semi-insulating GaAs substrate, 2, 2'... Insulating film, 3, 3', 3''... Resist film, 4... N region, 5... Source, drain region, 6... Thermal transformation layer , 7... implanted layer, 8... ion implantation.
Claims (1)
ランジスターの集積回路を形成する場合に、前記
GaAs電界効果型トランジスターの活性領域及
び、ソースおよびドレインの低抵抗領域を形成し
た後、前記活性領域及び前記低抵抗領域を少なく
とも含む領域にマスク材を被い、Ne、Ar、Kr、
Xeの少なくとも１種類の希ガスイオンをイオン
注入することによつて、前記GaAs電界効果型ト
ランジスターの素子間分離を行うことを特徴とす
る半導体素子の分離方法。1 When forming an integrated circuit of GaAs field effect transistors on a GaAs semi-insulating substrate, the above
After forming the active region and low resistance regions of the source and drain of the GaAs field effect transistor, a masking material is applied to a region including at least the active region and the low resistance region, and Ne, Ar, Kr,
1. A method for separating semiconductor devices, comprising performing device isolation of the GaAs field effect transistor by ion-implanting at least one type of rare gas ion such as Xe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56062882A JPS57177537A (en) | 1981-04-24 | 1981-04-24 | Isolation of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56062882A JPS57177537A (en) | 1981-04-24 | 1981-04-24 | Isolation of semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57177537A JPS57177537A (en) | 1982-11-01 |
| JPS6317227B2 true JPS6317227B2 (en) | 1988-04-13 |
Family
ID=13213073
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56062882A Granted JPS57177537A (en) | 1981-04-24 | 1981-04-24 | Isolation of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57177537A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6155938A (en) * | 1984-08-27 | 1986-03-20 | Yokogawa Hokushin Electric Corp | Method for isoration of electronic element |
| US4705606A (en) * | 1985-01-31 | 1987-11-10 | Gould Inc. | Thin-film electrical connections for integrated circuits |
| JPH0810704B2 (en) * | 1986-06-18 | 1996-01-31 | 株式会社日立製作所 | Method for manufacturing semiconductor device |
| JP2551203B2 (en) * | 1990-06-05 | 1996-11-06 | 三菱電機株式会社 | Semiconductor device |
| US9171936B2 (en) * | 2006-12-06 | 2015-10-27 | Cypress Semiconductor Corporation | Barrier region underlying source/drain regions for dual-bit memory devices |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5153489A (en) * | 1974-11-06 | 1976-05-11 | Hitachi Ltd | Handotaisochino seizohoho |
-
1981
- 1981-04-24 JP JP56062882A patent/JPS57177537A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5153489A (en) * | 1974-11-06 | 1976-05-11 | Hitachi Ltd | Handotaisochino seizohoho |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57177537A (en) | 1982-11-01 |
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