JPH01211969A - Manufacture of lateral bipolar transistor - Google Patents

Abstract

PURPOSE:To enable operation at high speed as well as high-density integration by using a semi-insulating semiconductor substrate as a substrate and selectively forming an impurity introduction region on the surface of the substrate. CONSTITUTION:A semi-insulating semiconductor substrate 1 is employed, a first conductivity type impurity introducing region 4 is shaped selectively onto the substrate 1 through a method such as an ion implantation method, and a dielectric film 5 is formed onto the region 4. A window is bored to one part of the film 5, an impurity is introduced through a method such as the ion implantation method through the window, and a second conductivity type impurity introducing region 7 is shaped selectively. An electrode 9 is formed onto the region 7, and electrodes 12 are shaped onto exposed sections on the region 4 on both sides of the region 7 through a self-alignment manner. Accordingly, high density integration as well as the increase of working speed are enabled.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a lateral bipolar transistor, and in particular, to a lateral bipolar transistor that has improved high frequency characteristics and switching characteristics and that enables high-density integration. The present invention relates to a method for manufacturing a transistor.

[Conventional technology]

First, a typical conventional lateral bipolar transistor will be explained.

Figure 5 shows the IE Electron Device Letters by Krautle et al.
IEEE Electron Device Lett
FIG. 3 is a cross-sectional view showing the structure of a lateral bipolar transistor according to the following publication (1982), Vol. 3, No. 10, p. 315 (1982).

In the figure, 51 is a low resistance n''-GaAs substrate, 52 is an n-Ga1-, M, As layer, and 53 is an n-GaA
s layer, 54 is a p-type region, 55 is an emitter electrode (Ni-A
uZn), 56 is a collector electrode (Ni-AuZn),
57 is a base with 11 poles (Ni-AuGe-Ni・), 5
8 is a SiO2 film, and 59 is Be ion implanted.

To fabricate a transistor with such a structure, first,
n-a a □-x on the low resistance n''-GaAs substrate 51
AaxA, s layer 52, and n-GaAs layer 53 are crystal-grown in sequence, and then a Si○2 film 58 is deposited thereon, patterned and left selectively, and Be ion implantation 59 is applied from above. Then, a p-type region (emitter region, collector region) 54 is formed.

A pnp type lateral bipolar transistor is formed.

[Problem to be solved by the invention]

However, since this transistor uses an n + -GaAs substrate, the emitter-base and collector-base junction areas are extremely large, and the parasitic capacitance due to these junctions becomes large, making high-speed operation impossible. It is possible.

Further, a base electrode 5 is placed on a low resistance n''-GaAs substrate 51.
7, it is impossible to integrate two or more transistors. Of course, isolation between elements by ion implantation or etching is also impossible.

Furthermore, since the base region (the region between the emitter region and the collector region) is formed using a simple process of patterning a 5in2 film, it is difficult to reduce the base width shown in the figure. There was a problem that high-speed operation could not be achieved. The base width in the example from this document is approximately 1
It is 11tn. In other words, the value of the base width is closely related to the current gain and base speed time, and the shorter the base width, the larger the current gain and the faster the base speed time, so high-speed operation is possible. It becomes possible.

As is clear from the above explanation, with conventional lateral bipolar transistors, miniaturization and high-density integration are difficult, and there is no hope of increasing speed.

An object of the present invention is to solve the above-mentioned problems and provide a method for manufacturing a high-speed lateral bipolar transistor that stably realizes a base width of about 0.2 mm or less, which allows further miniaturization and high-density integration. It is in.

[Means to solve the problem]

In order to solve the above problems, the present invention uses a semi-insulating semiconductor substrate as a substrate, and includes a step of selectively forming an impurity-introduced region of a first conductivity type on this substrate by, for example, an ion implantation method or an impurity diffusion method. , a dielectric film is formed on this first conductivity type impurity introduction region, a window is formed in a part of this dielectric film, and an impurity is introduced through this window by, for example, an ion implantation method or an impurity diffusion method, a step of selectively forming a second conductivity type impurity doped region; a step of forming an electrode on the second conductivity type impurity doped region; The method is characterized in that it includes a step of forming an electrode in a self-aligned manner on the exposed portion of the impurity-introduced region of one conductivity type.

[Effect]

With such a configuration, impurity introduction regions are selectively formed using a semi-insulating semiconductor substrate, so that an element isolation process is unnecessary and a lateral bipolar transistor can be manufactured at high density and high speed.

In addition, by selectively opening a window in a part of the dielectric film and introducing impurities through this window, a second conductivity type impurity introduction region is selectively formed, and an electrode is provided by patterning. As described in the example, a base electrode with a narrow base width of about 0.1 mm and an extremely low base metal resistance is realized. In addition, since the electrode can be formed in a self-aligned manner on the impurity-introduced region of the first conductivity type, the element size can be miniaturized, and a high-density and high-speed lateral bipolar transistor can be realized.

〔Example〕

Embodiment 1 FIGS. 1(a) to 1(h) are schematic process cross-sectional views showing a method for manufacturing a lateral bipolar transistor according to a first embodiment of the present invention. Hereinafter, the steps will be explained in order using this figure.

First, a resist film 2 is formed on a semi-insulating semiconductor substrate 1 made of GaAs, InP, etc., and then the resist film 2 is patterned by a normal photoetching method. Next, using this patterned resist film 2 as a mask, Si, Se,
Ion implantation 3 of an n-type impurity such as S is performed to form an n-type impurity introduced region 4 (a).

Next, after peeling off the resist film 2, Sin, , Si,
N4. An20. A dielectric film 5 such as a film is deposited over the entire surface, and a part of the dielectric film 5 is opened. This window opening method will be explained later using FIGS. 2 and 3. Thereafter, p-type impurity implantation region 7 is formed by performing ion implantation 6 of p-type impurities such as Be, Mg, and Zn. Thereafter, annealing is performed to activate the n-type and p-type implanted impurities introduced into the n-type impurity introduction region 4 and the p-type impurity introduction region 7 (b).

Next, after forming a resist film 8 on the dielectric film 5, the resist film 8 is patterned by photolithography (C).
.

Next, in order to form an ohmic electrode for the p-type impurity-introduced region 7, an Au/Zn layer 90 is vacuum-deposited over the entire surface (d).

Next, an ohmic electrode (base electrode) 9 is formed by lift-off using a normal method (e).

Next, after performing reactive ion etching of the dielectric film 5 using the ohmic electrode 9 as a mask, a new dielectric film 1.0 is deposited on the entire surface of the sample, and reactive ion etching is performed again to remove the ohmic electrode 9. Then, a dielectric film 10 is formed on the side wall of the dielectric film 5 (f).

Next, after forming a resist film 11 on the entire surface, the resist film 11 is patterned by photolithography to form an ohmic electrode of the n-type impurity doped region 4.
A Ni/Au layer 120 is vacuum deposited over the entire surface (g).

Next, the metal layer 120 on the resist film 11 is removed by lift-off, and then the metal attached to the dielectric film 10 on the sidewall is removed by diagonal ion milling etching to form the emitter electrode and the collector electrode 12. After that, by performing heat treatment for the ohmic electrode 9 and the electrode 12,
The lateral bipolar transistor is completed (h).

Here, to explain in more detail the conditions of this example, which was prototyped this time, the semi-insulating semiconductor substrate 1 is made of Ga.
The thickness of the resist film 2°8.11 is approximately 1.5-1 and the thickness of the dielectric film 5 is approximately 0.
．． 4. , the thickness of the SiO2 film which is the dielectric film 10 is approximately 0.257a, the conditions for Si ion implantation 3 are an acceleration voltage of 200keV and the dose amount of 5X1012 am-2, and the conditions for Be ion implantation 6 are an acceleration voltage of 50keV. , dose amount I
XIO"dll-".

In this example, an npn lateral bipolar transistor was formed, but p-type impurity ions such as Be were used instead of n-type impurity ions 3 such as SL, and conversely, n-type impurity ions were used instead of p-type impurity ions 6. Of course, it is also possible to form a pnp lateral bipolar transistor by using.

Further, in the present embodiment, the n-type impurity doped region 4 and the p-type impurity doped region 7 are formed using the ion implantation method, but an impurity diffusion method or the like may be used instead. However, in this case, it is necessary to use a dielectric film instead of the resist film 2 shown in FIG. 2(a).

FIGS. 2 and 3 are diagrams for explaining in detail the process of forming a window in the dielectric 1i5 of FIG. 1(b).

In the method shown in FIGS. 2(a) to 2(c), the resist film 13 is formed by 0.3I by electron beam writing, focused ion beam writing, etc.
Direct writing is performed with a line width of about Im or less (a), the dielectric film 5 is subjected to reactive ion etching using the resist film 13 as a mask (b), and then the resist film 13 is peeled off.

In the method shown in FIGS. 3(a) to 3(e), first, the resist film 13 is patterned by light exposure (a), and then the Ni film 1
4 is obliquely deposited (b). Next, using this Ni film 14 as a mask, the dielectric film 5 is subjected to reactive ion etching (Q
). Thereafter, a dielectric film 140 is deposited over the entire surface (d).

Finally, by performing reactive ion etching on the dielectric film 140, it becomes possible to leave the dielectric film 140 only on the side walls of the dielectric film 5 (e). is about 0.1. This makes it easy to create small holes.

Embodiment 2 FIGS. 4(a) to 4(d) are schematic process cross-sectional views showing a second embodiment of the present invention. In this embodiment, since the steps up to the step shown in FIG. 1(f) are completely the same, they will be omitted, and the subsequent steps will be explained. FIG. 4(a) shows a structure formed by the completely same steps up to FIG. 1(f). Thereafter, as shown in FIG. 4(b), the resist film 15 is patterned, and the Si ion implantation 16 is performed at an acceleration voltage of 3.
00 keV and a dose of I .

Further, FIG. 4(Q) is the same process as FIG. 1(g), and is a process for forming an ohmic electrode on the region 17.

FIG. 4(d) is a completed diagram of a lateral bipolar transistor according to one embodiment. In this embodiment, since the emitter and collector electrodes are formed in the heavily doped n-type impurity region 17, electrode resistance can be reduced and even higher speed operation can be achieved.

Although the embodiments of the present invention have been described above, it goes without saying that the present invention is not limited to the above-mentioned embodiments and that various modifications may be made within the scope of the claims of the present invention.

〔Effect of the invention〕

As explained above, in the present invention, a semi-insulating semiconductor substrate is used as the substrate, and impurity-doped regions are selectively formed on the surface of the substrate, thereby eliminating the need for an isolation process between elements and dramatically reducing parasitic capacitance. Therefore, it is possible to realize a transistor that operates at high speed, and at the same time, high-density integration of the transistor can be achieved. In addition, since the base width can be narrowed and the base electrode resistance is reduced,
It becomes possible to realize a transistor that operates at high speed. Furthermore, since the emitter and collector electrodes can be formed in a self-aligned manner, the transistor dimensions can be miniaturized and high-density integration can be achieved.

[Brief explanation of the drawing]

FIGS. 1(a) to (h) are schematic process cross-sectional views showing a method for manufacturing a lateral bipolar transistor according to the first embodiment of the present invention, FIGS. 2(a) to (c), and FIG. 3(a). )～(e)
1(b) are diagrams for explaining in detail the step of forming a window in the dielectric film 5, respectively, and FIGS. 4(a) to 4(d) show a second embodiment according to the present invention. 5 is a schematic cross-sectional view of a conventional lateral bipolar transistor. 1...Semi-insulating semiconductor substrate 2...Resist film 3...N-type impurity ion implantation 4...N-type impurity introduction region 5...Dielectric film 6...P-type impurity ions Implantation 7...p-type impurity introduced region 8...resist film 9...ohmic electrode (base electrode) 90...Au
/zn layer 10...Dielectric film 11...Resist film 12...Emitter electrode, collector electrode 13...Resist film 14...Ni film 15...Resist film 16...Si ion implantation 17...High concentration n-type impurity introduced region 51...Low resistance n''-G a As substrate 52-
n-Ga1-, Aa, As layer 53-n-
G a As layer 54...p-type head region 55...emitter electrode 56...collector electrode 57...base electrode 58...Sin, film 59...Be ion implantation 120- A u G e/Ni/Au layer 140...Dielectric film patent applicant Nippon Telegraph and Telephone Corporation

Claims (1)

[Claims] 1. selectively forming a first conductivity type impurity doped region in a surface region of a semi-insulating semiconductor substrate, forming a dielectric film on the substrate, and the first conductivity type impurity doped region forming a window in a part of the above dielectric film and introducing an impurity through the window to selectively form a second conductivity type impurity introduction region; and a step of selectively forming a second conductivity type impurity introduction region; and a step of forming electrodes on exposed portions of the first conductivity type impurity doped region on both sides of the second conductivity type impurity doped region. A method for manufacturing lateral bipolar transistors.