JP3300189B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a junction field effect transistor, and more particularly to a semiconductor device having a miniaturized gate structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a conventional junction field effect transistor, for example, as shown in FIGS. 4 (a) to 4 (e), a carrier and a semiconductor layer of the opposite conductivity type are formed on the surface by a process involving ion implantation. It was produced by doing. First, FIG.
As shown in (1), an n-type ion implantation layer 22 serving as an active layer is formed on a semi-insulating GaAs substrate 21 by an ion implantation method (a step of forming an n-type layer serving as an active layer by an ion implantation method). Next, as shown in FIG. 4B, an insulating film 23 made of SiO ₂ or the like is deposited on the entire surface of the substrate, a resist (not shown) is applied, and a portion (region) serving as a gate is removed. And the insulating film 23 in the gate portion is removed.
Then, the remaining resist is also removed (step of forming an insulating film). Next, as shown in FIG.
Using the extraction pattern as a mask, p-type dopant ions are implanted to form p-type regions 24 (step of implanting p-type dopant into the gate portion). Next, as shown in FIG. 4D, the insulating film 23 is removed, an annealing film 25 is formed on the front and back surfaces of the substrate, and the entire surface, followed by annealing (heat treatment) (annealing step). Next, as shown in FIG. 4E, the gate portion of the annealing film 25 is removed by an exposure step using a resist and an RIE (reactive ion etching) method to form a gate ohmic electrode 26 for the p-type region. It is formed by a lift-off method. Further, the source / drain portions are similarly removed by the RIE method, and the source / drain ohmic electrodes 27 and 28 for the n-type region are formed by the lift-off method. When an alloying process is performed after the electrode metal is lifted off, an FET (field effect transistor) is completed (an ohmic electrode forming step). As described above, the reason why it is difficult to form a fine gate in the conventional FET manufacturing process is that forming a fine punching pattern on the insulating film 23 in the process shown in FIG.
It is very difficult compared to the formation of the remaining pattern.
In the ion implantation shown in (c), the formed p-type region 24 spreads in the horizontal direction, which also makes it difficult to miniaturize the gate. Further, in the annealing step shown in FIG. 4D, there is a concern that the gate may be spread due to thermal diffusion. The main reason is that in the step shown in FIG. 4E, the gate portion of the annealing film 25 is removed by an exposure step using a resist and an RIE (reactive ion etching) method, and the gate ohmic electrode for the p-type region is removed. When forming the gate electrode 26 by the lift-off method, it is necessary to form the gate ohmic electrode 26 on the p-type region 24 which is the ion-implanted layer by re-positioning.
This is because the size cannot be reduced except for the margin for mask alignment. For these reasons, there is a problem that it is extremely difficult to reduce the length of the p-type region 24 corresponding to the gate length. As the above-mentioned prior art, GaAsIC Symposium Technical Digest, 1989, pp. 109-112 [GaAsIC Symposium Technical Dig.
est “12GHz GaAsJFET256 / 258 Dual-modulus Prescaler
IC "(1989), pp. 109-112].

[0003]

As described above, in the prior art, in the conventional junction field effect transistor having a structure in which the gate is miniaturized, it is difficult to form a fine pattern of the gate portion in the insulating film. In order to form a p-type region by injecting a p-type dopant by a method, a lateral spread occurs. Also, thermal diffusion in an annealing process may cause a spread of a gate. When the gate portion is removed by exposure using a resist and RIE, and the gate ohmic electrode for the p-type region is formed by the lift-off method, it is necessary to form the gate ohmic electrode for the p-type region 24 by re-alignment. , The p-type region cannot be reduced except for the margin of mask alignment,
In a conventional gate structure and manufacturing method of a junction field effect transistor or the like, an FET having a miniaturized gate structure is used.
There is a problem that the realization of the semiconductor device is extremely difficult.

An object of the present invention is to provide a semiconductor device such as a junction field-effect transistor having a structure in which the manufacturing process is simplified and a gate can be easily miniaturized, which solves the problems in the prior art, and a method of manufacturing the same. It is in.

[0005]

In order to achieve the object of the present invention, basically, in a semiconductor device such as a junction field effect transistor of the present invention, a part or all of a gate region is doped with an atomic layer. A layer is provided.
Specifically, the configuration is as shown in the claims. That is, the present invention has three electrodes on one main surface on a semiconductor substrate, as described in claim 1,
Of which the current flowing between the two electrodes, Ri semiconductor device der controlled by a voltage applied to the remaining one electrode,
On the semiconductor substrate, an N-type conductive layer and a gate metal layer
Disposed two layers of P-type conductivity type layer below, met junction field-effect transistor for controlling a current flowing through the voltage applied between said two layers, said junction field effect transistor
Is an i-layer including a p-type atomic layer doping layer therein and
The gate constituted by the P-type conductive type layer is
Processed with the same pattern mask as the metal layer
The gate region has the same length as the gate,
The i-layer immediately below the doping region is longer than the gate length.
Ru der which the forming of the semiconductor device. Further, according to the present invention, as described in claim 2 , one principal surface on the semiconductor substrate has three electrodes, and a current flowing between the two electrodes is
A semiconductor device controlled by a voltage applied to the remaining one electrode, wherein an N-type conductive type layer is formed on the semiconductor substrate.
And two layers of a P-type conductivity type layer immediately below the gate metal layer ,
An i-layer including a p-type atomic layer doping layer therein while controlling a current flowing by a voltage applied between the two layers;
Said the method of manufacturing the P-type conductivity type layer and the junction field effect transistor whose gate is constituted by, for by the gate <br/> DOO metal leaving pattern mask and the same mask used for processing of forming the gate i-layer and P-type conductivity type layer
The i-layer immediately below the atomic layer doping region is larger than the gate length.
The step of processing to be long, it is an method of manufacturing a semiconductor device including at least. Further, the present invention is defined by the claims.
According to a third aspect , in the second aspect , the step of processing the semiconductor layer forming the gate is performed by a dry etching method.

[0006]

According to the junction field effect transistor of the present invention, an atomic layer doping layer is provided on a part or the whole of a semiconductor layer forming a gate, so that an impurity concentration can be reduced to a fine region. Since it can be added at an extremely high concentration, there is no lateral expansion unlike ion implantation, there is no need to provide a margin in accordance with the pattern, and there is no expansion of the ion implantation region (gate region) due to thermal diffusion. Thus, a simplified gate electrode structure is obtained. Further, since the potential profile of the energy band of the conductor electrons in the gate portion can be made steeper, it is possible to suppress the gate leak current and improve the reverse breakdown voltage, and realize a high-performance semiconductor device. be able to. Further, the semiconductor layer constituting the Gate, can be processed in the same mask pattern as the gate metal layer, atomic layer doping region in the same length as the gate, i layer immediately below atomic layer doping region gate The gate length is based on the resolution and processing limit of the lithography tool, without being limited by the margin for pattern alignment. Can be realized. Further, the present invention is defined by the claims.
As described in 2 , the semiconductor layer forming the gate is processed using the same mask as that used for processing the gate metal,
Since the step of manufacturing a junction gate is used, the atomic layer doping layer can be cut accurately in accordance with the gate length. At this stage, the processed i-type InGaP layer 3a is not necessarily required, as shown in FIG. It is not necessary to stop the processing at the interface between the n-type InGaAs layer 2 and the p-type atomic layer doping layer 3 ′ as long as it can be reliably cut.
Even if the P layer 3 remains, the element characteristics do not deteriorate, the processing margin can be sufficiently secured, and the product yield can be improved. Further, the present invention is as claimed in claim 3, the processing of a semiconductor layer constituting the gate, for example, IRE by using a dry etching method such as reactive ion etching () method, precisely quickly microfabrication It can be carried out.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in more detail with reference to the drawings. 1 (a) to 1 (d), FIG.
3 (e) to 3 (h) and FIG. 3 (i) are process diagrams showing a process of manufacturing an n-type carrier junction field effect transistor exemplified in this example. FIG. 1A shows a semi-insulating GaAs.
A state in which an n-type InGaAs layer 2, an i-type InGaP layer 3 including a p-type atomic layer doping layer 3 'therein, and a p + -type GaAs layer 4 are formed on a substrate 1 (epitaxial growth step) is shown. Next, as shown in FIG. 1B, a gate metal (WSiN) layer 5 and a SiO ₂ layer 6 serving as a mask material when processing the gate metal layer 5 are formed on the entire surface of the substrate (step of depositing the gate metal layer). ). Where p
The formation of the atomic layer doping layer 3 ′ of the type is performed by temporarily suspending the growth during the epitaxial growth, flowing only the source gas of the p-type dopant for several minutes until the p-type dopant has completely covered the crystal surface, and then performing the epitaxial growth again. Formed by initiating By doing so, an extremely thin layer of an extremely high density p-type impurity can be formed, the withstand voltage can be increased to obtain a predetermined carrier, and a steeper concentration profile can be obtained. As the crystal growth method, an MOCVD method, an MBE method, or the like can be used. In addition, a commonly used crystal growth method may be used. Next, as shown in FIG. 1C, a resist pattern 12 is formed on the SiO ₂ layer 6 by an exposure process so as to cover a portion to be a gate (a pattern such as a resist is formed on the gate metal layer). Step). Next, FIG.
As shown in FIG. 2, a gate mask pattern 6a is formed by, for example, RIE using the resist pattern 12 as a mask, and further, using the gate mask pattern 6a as a mask, the gate metal (W) is vertically formed by, for example, ECR-RIE or the like.
The SiN) layer 5 is processed to form a gate metal (WSiN) 5a (step of processing the gate metal layer). Next, FIG.
As shown in (e), after processing the gate metal layer, after processing the gate metal, the p + type GaAs layer 4 is formed using the same mask.
a, forming an i-type InGaP layer 3a (step of processing a junction gate). Next, as shown in FIG.
In the state of (e), n 'ion implantation is performed to form an n' layer 7, and an annealing film (SiON film) 8 is further formed on the entire surface (n 'ion implantation step). Next, as shown in FIG. 2 (g), the entire surface is anisotropically etched by RIE, and n + ion implantation is performed to form an n + ion implantation layer 9 while leaving the side wall (SiON layer) 8a made of an annealed film. (Step of forming n + ion implanted layer). Next, FIG.
As shown in (h), an annealing film (SiON film) 10 is formed again on the front, back, and entire surface of the substrate, and annealing (heat treatment) is performed.
(A step of forming an annealing film again and performing a heat treatment). Next, as shown in FIG. 3I, an ohmic electrode 11 serving as a source / drain is formed, and a junction type FET is formed.
Is completed (the fabrication of the FET is completed). As described above, in the junction type FET of the present invention, the resist pattern for forming the gate portion is formed by using the remaining pattern, and is not a method using a conventional fine punching pattern. Can be formed. Also, the gate p
Since the ion implantation method is not used to form the mold layer, there is no problem of lateral expansion of the p-type region, and there is no need to provide a margin according to the gate length, so that the gate length can be miniaturized.

[0008]

As described above in detail, the semiconductor device such as a junction type FET of the present invention uses a remaining pattern instead of a conventional fine pattern as a resist pattern for forming a gate portion. As a result, a fine gate portion can be formed very easily and accurately. In addition, since an atomic layer doping layer is used for the gate p-type layer and the ion implantation method is not used, there is no problem of the lateral extension of the p-type region, and there is no need to provide a margin according to the gate length. Is based on the resolution and processing limit of the exposure machine without being limited by the alignment margin, and it is possible to realize a semiconductor device with a fine gate. Further, in the formation of the gate, an impurity can be added to the fine region at an extremely high concentration by atomic layer doping, a fine and good gate p-type region can be formed, and the i-type InGaP layer is not necessarily formed at the processing stage of the junction gate. n
There is no need to stop processing at the interface with the type InGaAs layer,
It is sufficient that only the p-type atomic layer doping layer is reliably cut, and even if a small amount of the i-type InGaP layer remains, the characteristics are not deteriorated, so that a sufficient working margin can be secured.

[Brief description of the drawings]

FIG. 1 is a process chart showing a manufacturing process of a semiconductor device exemplified in an embodiment of the present invention.

FIG. 2 is a process chart showing a manufacturing process of the semiconductor device exemplified in the embodiment of the present invention.

FIG. 3 is a process chart showing a manufacturing process of the semiconductor device exemplified in the embodiment of the present invention.

FIG. 4 is a process chart showing a manufacturing process of a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semi-insulating GaAs substrate 2 ... N-type InGaAs layer 3 ... i-type InGaP layer 3a ... Processed i-type InGaP layer 3 '... Atomic layer doping layer (p-type layer) 4 ... p + type GaAs layer 4a ... processed p + -type GaAs layer 5 ... gate metal (WSiN) layer 5a ... processed gate metal (WSiN) 6 ... SiO ₂ layer (mask material) 6a ... gate mask pattern 7 ... n 'ion implantation layer (n' layer) 8 ... SiON layer 8a ... side wall (SiON layer) 9 ... n + ion implantation layer (n + layer) 10 ... anneal film (SiON film) 11 ... source / drain ohmic electrode 12 ... resist pattern 21 ... semi-insulating GaAs substrate 22 ... n-type ion implantation layer 23: insulating film (SiO ₂ layer) 24 ... p-type region 25 ... annealed film 26 ... gate ohmic electrodes 27 source and drain ohmic electrode 28 ... Io Injection (p-type dopant)

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-274371 (JP, A) JP-A-54-21283 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/338 H01L 29/812

Claims (3)

(57) [Claims] 1. A semiconductor device having three electrodes on one main surface on a semiconductor substrate, wherein a current flowing between two electrodes is controlled by a voltage applied to the remaining one electrode. Ah
And an N-type conductive layer and a gate metal on the semiconductor substrate.
Disposed two layers of P-type conductivity type layer immediately below the layer, met junction field-effect transistor for controlling a current flowing through the voltage applied between said two layers, said junction field effect transient
The star has an i-layer including a p-type atomic layer doping layer therein.
The gate constituted by the P-type conductive type layer is
Processed with the same pattern mask as the gate metal layer,
The layer doping region has the same length as the gate and
The i-layer immediately below the sub-layer doping region is longer than the gate length.
A semiconductor device characterized by being formed . 2. A semiconductor device having three electrodes on one main surface on a semiconductor substrate, wherein a current flowing between two electrodes is controlled by a voltage applied to the remaining one electrode. And an N-type conductive layer and a gate metal on the semiconductor substrate.
Two layers of a P-type conductivity type layer immediately below the metal layer are provided, and a current flowing by a voltage applied between the two layers is controlled .
An i-layer including a p-type atomic layer doping layer therein and the p-type
In the manufacturing method of the conductive layer and the junction field effect transistor whose gate is constituted by, by leaving the pattern mask and the same mask used for processing of the gate metal layer, the i layer and the P-type conductivity that constitute the gate Layer with the above atoms
I-layer directly under layer doping region is longer than gate length
A method of manufacturing a semiconductor device, comprising at least a step of processing as follows. 3. The method according to claim 2 , wherein the step of processing the semiconductor layer forming the gate is performed by a dry etching method.