JP3194921B1 - Method of manufacturing raised strap structure MOS transistor - Google Patents

Abstract

Abstract: PROBLEM TO BE SOLVED: To reduce a parasitic capacitance and a parasitic resistance relating to a source / drain of a MOS transistor. SOLUTION: In a MOS transistor having a raised strap structure, a source region (92) and a drain region (91) are substantially insulated from a transistor substrate (51) and connect the straps (94, 95). Thus, it is connected to the transistor substrate (51). Gate oxide layer (67) and gate electrode (93)
Is formed on the substrate (51) between the two straps.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a process for manufacturing a MOS semiconductor device. In particular, the present invention provides a high speed, high density M
It relates to reducing parasitic resistance and capacitance in OS transistors.

[0002]

BACKGROUND OF THE INVENTION A significant problem associated with the fabrication of transistors with very shallow junctions is the presence of parasitic resistance and capacitance. FIG. 1 shows a diagram illustrating such a unique parasitic element. The symbols R _d and R _s indicate the parasitic resistances of the drain and source regions, respectively, where R _d and R _s each consist of the resistance components from the lightly doped region _RL and the heavily doped region _RH . The resistance of the lightly doped region is not significantly reduced. This is because the resistance is used as a gradient to set a high breakdown voltage.

[0003] There is also parasitic capacitance associated with each of the source and drain regions. This capacitance is proportional to the surface area of the junction between the doped region and the substrate. The parasitic capacitance of the drain shown in C _d, shows the parasitic capacitance of the source in C _s.

[0004]

A disadvantage caused by the presence of parasitic resistances and capacitances is that they combine to form a time constant τ. This time constant τ is τ = C
_s, is defined as _{d (R d + R s)} , significantly disturb the operation speed of the transistor. Therefore, it is desirable to increase the operating frequency of a transistor by minimizing both parasitic resistance and parasitic capacitance.

The problem caused by the time constant τ is:
This is exacerbated by industrial trends to further reduce component size. This is because reducing the width and depth of the component increases the parasitic resistance of the doped region therein.

Accordingly, it is an object of the present invention to minimize parasitic resistance in a MOS transistor.

Another object of the present invention is to minimize the parasitic capacitance in a MOS transistor.

Yet another object of the present invention is to minimize parasitic resistance and capacitance in MOS transistors that provide doped source and drain regions sized to sufficiently overcome the metallization problem.

[0009]

SUMMARY OF THE INVENTION According to the present invention, a method of manufacturing a raised strap MOS transistor includes the steps of forming first, second and third oxide layer segments separated from each other on a semiconductor substrate. Forming a gate electrode on the second oxide layer segment; and forming a source region and a part of a drain region on the first and third oxide layer segments. After each step of forming a material and each of the above steps, an oxide layer is formed over the entire surface, and a part of the source region;
Removing a part of the oxide layer so that a part of the drain region and a surface of each of the gate electrodes are exposed; and a step of removing a part of the source region and the gate electrode. Removing a portion of the oxide layer, and a portion of the oxide layer between a portion of the drain region and the gate electrode so that the surface of the semiconductor substrate is exposed, Forming a source region and a drain region by selectively growing a semiconductor from the surface of the semiconductor substrate and selectively growing a semiconductor from part of the source region and part of the drain region. And the above-mentioned object is achieved.

[0010] The above object and related objects can be achieved by using the transistor disclosed in this specification and a method for manufacturing the transistor. The transistor and the method of manufacturing the same according to the present invention have raised source and drain regions strapped to a conductive channel region, thereby producing a transistor having many desired characteristics.

The source and drain configurations of the strap structure improve the source and drain junction depth, thereby providing good protection against unwanted short channel effects.

In addition, by using a strap shape having a small cross-sectional area, the source and drain junction regions are also reduced. Since the junction capacitance is proportional to the junction area, minimizing the junction area also reduces the junction capacitance.

Further, since the source and drain regions are mainly formed on the field oxide layer, the formation of the metal wiring on the source and drain regions prevents the metal from penetrating into the substrate through the source and drain regions. It can be done without doing.

The present invention can be realized in any of an NMOS device and a PMOS device. The realization of a raised strap MOS transistor will be better understood upon consideration of the following detailed description and the accompanying drawings.

[0015]

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a raised strap MOS transistor which solves the problems associated with the prior art. To facilitate a better understanding of how such a raised strap MOS transistor is implemented, in the following description, the completed transistor 100 will be described first, followed by the transistor The process used to fabricate is described.

FIG. 12 shows a completed MOS transistor 100 with a raised strap structure. The transistor is formed over a substrate 51 made of a semiconductor material. The semiconductor material of the substrate 51 is typically a silicon crystal and is lightly doped with electron donor or acceptor impurities depending on whether the transistor 100 will be used as an n-channel (NMOS) device or a p-channel (PMOS) device in the future. Doped. The electron donor impurity is PM
Used for substrate doping in OS devices, electron acceptor impurities are used in NMOS devices. Drain 91 and source 92 are separated from substrate 51 by oxide layer regions 66 and 68, respectively. The designation of the names of the drain 91 and the source 92 is arbitrary, and the designation of those names can be reversed.

A strap 94 is formed as part of the drain region 91 and serves to physically couple a major portion of the drain region to the substrate. A similar strap 95 is provided to physically couple a major portion of the source region to the substrate. Both the drain and source straps 94, 95 have a small cross-sectional area. This minimizes parasitic capacitance at the junction. The strap is also formed long enough to prevent metal diffusion from the wiring to the junction that degrades the junction characteristics.

Known electrical properties, which typically characterize the drain and source regions from a semiconductor physics point of view, are realized primarily in regions 94 and 95, respectively. Thus, for regions 94 and 95, the term "strap" is used by configuration, but the essential electrical properties of the drain and source regions are realized in those regions. To some extent, the remaining main portions of the drain region 91 and the source region 92 serve as wiring.

Lightly doped regions 82 and 85 can be formed adjacent straps 94 and 95, respectively, to increase the breakdown voltage (breakdown voltage) as needed. Gate region 93 is separated from substrate 51 by gate oxide layer 67. The drain 91 and the source 92 are connected to metal wirings 96 and 97, respectively.
6 and 97 are oxide layer side walls 80 and 81
(FIG. 9) is separated by an insulator such as an oxide layer 79 formed in contact with (FIG. 9). The gate 93 is similarly connected to the metal wiring 98, and the metal wirings 96 to 98 for the drain, source and gate are respectively connected to the contact pads 99.
a to 99c.

When a predetermined voltage is applied to the gate 93 and the gate voltage exceeds the threshold voltage, inversion occurs in the substrate 51. This inversion causes the drain strap 94
A conductive channel 50 is formed between the semiconductor device and the source strap 95.

Other advantages of transistor 100 include the advantage that drain region 91 and source region 92 are large enough to improve alignment tolerances for metal wiring. By forming the drain region 91 and the source region 92 with polysilicon, the contact resistance at the metal wirings 96 and 97 is reduced, respectively. In addition, a drain 91 and a source 92 are created on the field oxide layer regions 66 and 68, respectively, so that the isolation provided by the oxide layer does not cause metallization problems associated with conventional transistors such as junction spikes and shorts. Enable wiring connection.

Having described the overall structure and some advantages of transistor 100, a method of fabricating the transistor will now be described with reference to FIGS.

FIG. 2 shows a silicon substrate 51 having a raised active region. Preferably, the substrate is made of single crystal silicon and lightly doped with a dopant impurity of a desired background polarity. The active regions are separated from one another by processes known in the art. For example, the active region of the substrate 51 is raised using a trench isolation technique and contacts the oxide layer on both sides.

A threshold voltage adjustment is performed for each of the active regions. As a result, the active region can include n-channel or p-channel devices. These elements can operate in enhancement mode or depletion mode depending on the desired application. The respective threshold voltage adjustments in these cases are known in the art.

A layer 52 of a gate oxide layer is grown or deposited on substrate 51. The thickness of this layer will vary depending on the desired application, but in a preferred embodiment the thickness is about 40-200 Angstroms.

In the next step, a layer 53 of a semiconductor material such as polycrystalline silicon (hereinafter "polysilicon") is deposited on the gate oxide layer 52, as shown in FIG. In the preferred embodiment, the thickness of this polysilicon layer is 2
It is 00 to 300 nm. Next, the polysilicon layer is heavily doped with donor or acceptor impurities to set the conductivity type and doping concentration of the gate electrode 55 (FIG. 5).
The choice of conductivity type will depend in part on whether an N-channel device or a P-channel device is to be manufactured and whether the operation is in enhancement mode or depletion mode. Relevant considerations are known in the art. In a preferred embodiment,
The gate is doped with an electron donor impurity.

In FIG. 4, the extended gate region (55)
A layer of photoresist 54 is formed on the doped polysilicon 53 to define The length of the resist 54 is approximately L + 2d, where L is the channel length and d is the alignment tolerance. In the next step, FIG.
As shown in FIG. 7B, the plasma etching of the polysilicon 53 is performed until all of the polysilicon 53 except the part (55) of the polysilicon 53 covered with the extended gate resist 54 reaches the oxide layer 52. Removed.

The photoresist 54 has been removed and another polysilicon layer 59 has been removed, as shown in FIG.
5) is formed on top. In a preferred embodiment, 50
Deposit a ~ 100 nm polysilicon layer to form layer 59. Next, as shown in FIG.
Are formed on the polysilicon layer 56 to define gate, drain and source regions, respectively. Next, plasma etching is started, and a part of the polysilicon layer 59 and a part of the oxide layer 52 are removed as shown by a dotted line in FIG. The result of this plasma etch is shown in FIG.

In FIG. 7, a portion of the drain region 70 and a portion of the source region 71 are created, and a substantial portion of the gate 72 is also created. A portion of the oxide layer has also been removed by the plasma etch of FIG. 6 to define drain, gate and source oxide layer segments 66-68, respectively, separated by two gaps 74-75. It is also conceivable that a small portion of the substrate 51 could be removed at the gaps 74 and 75 during this etch. Such overetch does not affect device performance. In the next step, the dotted line 78
An oxide layer, indicated by, is formed over the entire device of FIG. This oxide layer can be formed by either growth or deposition, but in a preferred embodiment is performed by thermal oxidation to a thickness of about 10-15 nm.

In FIG. 8, a new oxide layer 78 is formed with oxide layer segments 66-68 to form a complete oxide layer 78. In the oxide layer 78, the drain, the source, and a part of the gates 70 to 72 are respectively arranged.

Referring to FIG. 9, an anisotropic plasma etch is then performed to remove portions of the oxide layer 78 on the horizontal surface. Anisotropic plasma etch is known in the art, particularly for removing oxide layers from horizontal surfaces, while leaving oxide layers formed on vertical surfaces, for materials such as oxide layers Is known. A particular advantage of the anisotropic etch is that it provides alignment tolerance. In FIG. 9, an anisotropic plasma etch is similarly used to create gate sidewalls 80 and 81.
The gate sidewalls 80 and 81 separate the gate 72 from the drain and source regions formed in a later step. The anisotropic etch is also a strap-type insulator 83
And 84 are formed. Strap-type insulators 83 and 84
Is useful in defining straps 94 and 95 described below, but is not required for proper functioning of the present invention, but rather is formed as an acceptable by-product of the anisotropic plasma etch. The drain gap 76 and the source gap 77 are similarly formed by anisotropic plasma etching. An important aspect of the drain gap 76 and the source gap 77 is that they constitute a volume that will be buried in the future to form a drain strap 94 and a source strap 95, respectively.
And the distance between them defines the channel length.

In the next step, in FIG. 10, drain and source strap layers 86 and 87 are formed from a semiconductor material. The forming process can include selective growth of silicon or polysilicon or deposition of polysilicon. If selective epitaxial silicon is used, single crystal silicon is grown on substrate 51 at gaps 76 and 77, and polysilicon 89 is deposited on polysilicon gate 72 and partial drain region 70 and partial source region 71. Then, the drain 70 and the source 71 are strapped to the substrate 51 via the gaps 76 and 77, respectively. As shown in FIG. 10, lateral growth of epitaxial silicon and polysilicon covers regions 76 and 77. Selective epitaxial growth of silicon on substrates of similar properties is known in the art. Such a structure may be particularly suitable for higher voltage applications, especially by lightly doped epitaxially grown silicon which increases the breakdown voltage of the transistor.

When selective polysilicon growth is used,
The polysilicon is exposed on the exposed silicon substrate 51 and the polysilicon drain 70 and the source 71 at the gaps 76 and 77.
And deposited on the gate 72. As in the case of selective epitaxial growth, regions 76 and 77 are covered by lateral overgrowth. The latter process is shown in FIG. The choice as to whether to use selective silicon or polysilicon can be made by those skilled in the art depending on the particular application or particular industry trends. Polysilicon is manufactured by Y. Furmura et al., J. Electrochem.
Soc. Vol. 133, No. 2, P. 379, 1986.

Drain, source and gate regions 70-7
2 are newly deposited polysilicon 86, 8 respectively.
7 and 89 are shown separately. However, this separation has been shown to illustrate the deposition process used in conjunction with FIG. 10, and in practice these regions will be drain 91, source 92 as shown in FIG.
And a gate 93.

In FIG. 11, an optional processing step known as salicidation may be applied. Salicidation or self-aligned silicidation generally refers to a self-aligned process for metallizing semiconductor materials by including a known amount of a refractory metal such as titanium, cobalt or zirconium. Advantageous aspects of silicidation include improved conductivity, increased structural integrity when used as a contact barrier. The enhanced conductivity is due to a reduction in the capacitance series resistance and is particularly desirable in high speed circuits. If the application for the transistor, such as transistor 100, is not fast, then silicidation is not necessary. Since salicidation is easy to perform, it is often used for silicidation. In a preferred salicidation process, a 30-50 nm thick refractory metal is deposited on the device of FIG. The refractory metal reacts with the polysilicon to form a silicide, but does not react with the oxide layer and is thus self-aligned. Portions of the refractory metal that do not react with silicon are selectively etched. The drain and source silicidation can be partially or completely performed.

In the next step, similarly, in FIG. 11, ions are implanted into the drain region 91, the source region 92 and the gate region 93, and into the drain strap 94 and the source strap 95. It is known that dopant impurities diffuse rapidly in polysilicon, such as drain 91 and source 92, and diffuse relatively slowly in single crystal silicon, such as substrate 51. As a result, by annealing the drain region 91 and the source region 92 for uniformly distributing the dopant impurity, a small amount of the impurity enters the substrate 51 to form the lightly doped drain region 82 and the lightly doped source region 85. Thus, lightly doped drain and source regions 82 and 8
5 is formed in one less process than the masking process required in the prior art, thus increasing the potential yield of the transistor thus manufactured.

A suitable anneal to achieve uniform doping of the drain region 91 and source region 92 and the creation (if necessary) of lightly doped drain and source regions 82, 85 is at 700-900 ° C. This is achieved by a 10 second to 1 minute wafer anneal in a nitrogen or argon atmosphere.

The doping of the drain 91 and the source 92 is performed as follows. For N-channel devices, a suitable photoresist is applied to protect regions that do not receive electron donor impurities. Next, phosphorus (or arsenic) ion implantation is performed at about 10 ¹⁵ to 10 ¹⁶ ions / c.
It is performed with an ion dose of m ² and an ion energy of about 30 keV to 80 keV. In the case of a P-channel device, an appropriate photoresist is applied so as to protect a region that does not receive the electron acceptor impurity, and is applied to about 10 ¹⁵
Dosage amount of 10 to 10 ¹⁶ pieces / cm ² , about 10 keV to 50 k
Boron ion implantation is performed with ion energy of eV.

In FIG. 12, the necessary processing steps known in the art are performed to form a drain 91 and a source 92.
In addition, wirings 96 to 98 up to the respective gates 93 are formed, and these wirings are insulated using an oxide layer or another insulator 79. If necessary, contact pads 99a-9
9c is formed on the wiring, and the first transistor 1 discussed above is formed.
00 is obtained.

The transistor 100 according to the preferred embodiment described above has N ⁺ polysilicon gates in both n-channel and p-channel devices. In an alternative embodiment of the invention, the N ⁺ silicon gate is N ⁺ polycide, which is a combination of polysilicon and silicide;
P ⁺ polysilicon, P ⁺ polycide can be replaced refractory metal or refractory metal silicide. The use and implementation of one of these materials is known to those skilled in the art.

In summary, the MO of the raised strap structure is
An S-transistor 100 is disclosed and offers the advantage of a very small source and drain junction area. This minimizes parasitic capacitance and allows the source and drain junctions to be strapped to the field oxide layer, eliminating the problem of metal spikes, eliminating the need for contact barrier metal, and extending the depth of the source and drain junctions. it can. Further, there is an advantage that the mask count required for forming the lightly doped region is reduced. This produces higher potential yields and the salicide process further reduces parasitic resistance.

Although the invention has been described with respect to particular embodiments, it will be understood that other modifications are possible.
Further, this application is generally based on the principles of the present invention, and applies to developments from this disclosure or to key features described above that are within the known or customary scope in the art to which this invention pertains. And is intended to cover any variations, uses, or adaptations of the invention, including developments from this disclosure, which fall within the scope of the invention and the appended claims.

[0043]

The method of fabricating a transistor according to the present invention has raised source and drain regions strapped to a conductive channel region, thereby improving source and drain junction depths and reducing undesirable short channel effects. Good protection is provided. In addition, the use of a strap shape with a small cross-sectional area also reduces the junction capacitance by minimizing the junction area.
Further, since the source and drain regions are mainly formed on the field oxide layer, the formation of the metal wiring on the source and drain regions does not cause the metal to penetrate the substrate through the source and drain regions. Can be done.

[Brief description of the drawings]

FIG. 1 is an equivalent diagram showing parasitic capacitance and resistance in a conventional transistor.

FIG. 2 is a view showing a process step in manufacturing a MOS transistor having a raised strap structure.

FIG. 3 is a diagram showing a process step in manufacturing a MOS transistor having a raised strap structure.

FIG. 4 is a diagram showing a process step in manufacturing a MOS transistor having a raised strap structure.

FIG. 5 is a diagram showing a process step in manufacturing a MOS transistor having a raised strap structure.

FIG. 6 is a diagram showing a process step in manufacturing a raised-type strap-structure MOS transistor.

FIG. 7 is a diagram showing a process step in manufacturing a raised-type strap-structure MOS transistor.

FIG. 8 is a diagram showing a process step in manufacturing a raised-type MOS transistor having a strap structure.

FIG. 9 is a view showing a process step in manufacturing the MOS transistor having the raised strap structure.

FIG. 10 is a diagram showing a process step in manufacturing the MOS transistor having the raised strap structure.

FIG. 11 is a view showing a process step in manufacturing the MOS transistor having the raised strap structure.

FIG. 12 is a diagram showing a completed raised-strap-structure MOS transistor manufactured by the process steps shown in FIGS. 2 to 11;

[Explanation of symbols]

 Reference Signs List 51 substrate 66 drain oxide layer segment 67 gate oxide layer segment 68 source oxide layer segment 91 drain region 92 source region 93 gate region 94 drain strap 95 source strap

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-134827 (JP, A) JP-A-3-74848 (JP, A) JP-A-1-26861 (JP, A) JP-A-6-1994 21449 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 21/336

Claims (1)

(57) [Claims] A step of forming first, second and third oxide layer segments separated from each other on a semiconductor substrate; and a step of forming a gate electrode on the second oxide layer segment. Forming a semiconductor material to be a part of a source region and a drain region on the first oxide layer segment and the third oxide layer segment respectively; Forming an oxide layer, removing a part of the oxide layer, respectively, such that a part of the source region, a part of the drain region, and a surface of the gate electrode are exposed, A part of the oxide layer between the part of the source region and the gate electrode, and a part of the oxide layer between the part of the drain region and the gate electrode, Semiconductor substrate surface Removing the semiconductor substrate so as to be exposed; selectively growing a semiconductor from the exposed surface of the semiconductor substrate; and selectively growing a semiconductor from a part of the source region and a part of the drain region. And a step of forming a drain region.
A method for manufacturing an S transistor.