JP3407926B2 - Doping method, semiconductor device, resistance layer, method of manufacturing field effect transistor, method of manufacturing semiconductor circuit element, method of manufacturing electric conduction region, method of forming quantum wire, method of forming quantum box, quantum wire transistor, semiconductor integrated circuit Manufacturing method, electron wave interference device - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to GaAs, AlGaA
The present invention relates to a doping method for diffusing silicon into a III-V group compound semiconductor such as s, a semiconductor device having a doping layer formed by using this doping method, and a manufacturing method thereof.

[0002]

2. Description of the Related Art As a method for doping impurities into a semiconductor substrate, an ion implantation method and a diffusion method are well known in addition to the crystal growth method. In particular, S using Si as a substrate
For the i-device, this ion implantation method and diffusion method have been established as important techniques for doping impurities in the Si substrate.

[0003]

On the other hand, GaAs, Ga
When doping a III-V compound semiconductor substrate such as P or InP with impurities, there is an essential problem that the stoichiometric composition of the substrate crystal tends to shift when high temperature treatment is performed. It is necessary to establish a doping method suitable for each, and only some of them have not been established yet. For example, taking a GaAs substrate as an example, only an ion implantation method and a part of the diffusion method (formation of a p-type impurity layer by Zn diffusion) are established. The main reason why the diffusion method for forming the n-type impurity layer has not been established is
Since the diffusion temperature is high (800 ° C or higher), G due to dissociation of As
This is because a stoichiometric composition shift of the aAs substrate crystal is likely to occur and diffusion cannot be performed with good controllability.

It is an object of the present invention to form a laminated film of a non-doped SiO _x film and a group V atom diffusion preventing film on a group III-V compound semiconductor and then heat the silicon to form III-V. It is an object of the present invention to provide a novel doping method which can be easily diffused into a group compound semiconductor and which is completely different from the conventional method.

Another object of the present invention is to provide a semiconductor device having a doping layer formed by utilizing this novel doping method and a method of manufacturing the same.

Still another object of the present invention is to provide a concave portion in a semiconductor layer and pass a current through the side surface of the concave portion, thereby setting the resistance value and setting the resistance value without changing the occupied area of the resistive layer on the semiconductor layer. It is to provide a resistance layer capable of improving ohmic characteristics.

Still another object of the present invention is to provide a method for manufacturing a field effect transistor capable of performing doping with good in-plane uniformity in a portion where it has been difficult to dope conventionally. It is in.

Still another object of the present invention is a method of manufacturing a field effect transistor capable of manufacturing a vertical field effect transistor using a III-V group compound semiconductor substrate such as a GaAs substrate with good reproducibility. To provide.

Still another object of the present invention is to reduce the drain-source resistance without lowering the gate breakdown voltage, to lower the knee voltage and to obtain a large output power, to improve the power conversion efficiency, and to improve the transistor efficiency. It is an object of the present invention to provide a method for manufacturing a field effect transistor capable of improving the characteristics.

Still another object of the present invention is to provide a method for manufacturing a field effect transistor which can easily form a doping layer having a higher impurity concentration.

Still another object of the present invention is to provide a semiconductor circuit element capable of simultaneously forming a plurality of conductive layers having different resistance values by controlling the film thickness of the group V atom diffusion preventing film. It is to provide a manufacturing method.

Still another object of the present invention is to improve the yield by increasing the current value and the threshold voltage of a field effect transistor once manufactured by heat treatment at a low temperature. It is to provide a manufacturing method of.

Yet another object of the present invention is to provide a novel method for producing an electrically conductive region, which is completely different from the conventional one, using the above-described doping method of the present invention.

Still another object of the present invention is to form quantum wires using the doping method of the present invention and control the thickness of a diffusion layer for diffusing Si, thereby preventing crystal defects. Another object of the present invention is to provide a method for forming a quantum thin wire, which can form a quantum thin wire with a narrow channel width with high accuracy and without being restricted by the shape.

Still another object of the present invention is to provide a different kind of III-
Si is diffused into the group V compound semiconductor to form respective diffusion portions, and the difference in the depths of the diffusion portions is used as the channel width of the quantum thin line, so that the channel width can be accurately reduced without causing crystal defects. It is to provide a method of forming a quantum wire that can be formed.

Still another object of the present invention is to form a laminated structure film composed of a SiO _x film and a group V atom diffusion prevention film on a wide bandgap semiconductor layer processed into a sawtooth shape, and heat-treat the layer to form a wide bandgap. (EN) A method for forming a fine quantum wire or a quantum box under a sawtooth-shaped recess by forming a doping layer on the surface of a band semiconductor layer, and a quantum wire transistor provided with this quantum wire. .

Still another object of the present invention is the dope of the present invention.
By using the ring method, III-V compound made of a semiconductor layer to a predetermined depth, by diffusing Si at a predetermined concentration, such as modulation doped field effect transistor without using a conventional selective etching technique semiconductor It is to provide a method of manufacturing a circuit element.

Still another object of the present invention is to use the doping method of the present invention to monolithically manufacture a plurality of elements having different characteristics, for example, a low noise device and a high gain device. It is to provide a method of manufacturing a circuit.

Still another object of the present invention is to provide a high-concentration layer formed by using the doping method of the present invention as a channel layer, so that a complicated technique is not used at the time of forming the channel layer and an integrated circuit is formed. An object of the present invention is to provide an electron wave interference element that can have a structure suitable for use in the electronic device.

[0020]

The doping method according to the present invention (claim 1) is a method of doping impurities in a III-V compound semiconductor, wherein the crystal of the III-V compound semiconductor is non-doped silicon oxide. Membrane (SiOx
Film) and V constituting the crystal of the III-V compound semiconductor
Silicon (Si) in the SiOx film is diffused into the III-V group compound semiconductor by sequentially laminating a film for preventing out-diffusion of group atoms and subjecting these to at least one heat treatment. possess a step of the
The x of the SiOx film is characterized by x <2 .

A doping method according to claim 2 is the doping method according to claim 1, wherein the III-V group compound semiconductor is GaAs.
System, InP system, AlAs system, AlGaAs system, InGa
At least one selected from the group consisting of As-based and InAlAs-based
It is characterized by being selected one or more.

A doping method according to a third aspect is the doping method according to the first aspect, wherein the film for preventing outdiffusion of a group V atom is
It is characterized by being selected from the group consisting of SiN film, AlN film, WSi film and WSiN film.

[0023]

According to a fourth aspect of the present invention, in the doping method according to the first aspect, after the two films are laminated, only these two films are left in a predetermined region, or the SiOx film and a group V atom in a predetermined region are removed. The method is characterized by further including a step of leaving a film for preventing outdiffusion.

According to a fifth aspect of the present invention, in the doping method according to the first aspect, at the time of stacking the two films, the film thickness and / or film characteristics of at least one film are changed so that Si after heat treatment is changed. It is characterized by changing the diffusion profile.

A semiconductor device according to a sixth aspect is characterized by having a doping layer formed by using the doping method according to the first aspect.

A semiconductor device according to a seventh aspect is the semiconductor device according to the sixth aspect, wherein the semiconductor device is a field effect transistor,
It is an integrated circuit having at least one or more diodes and resistance layers.

A semiconductor device according to an eighth aspect is the semiconductor device according to the sixth aspect , wherein the semiconductor device uses a quantum effect element having a two-dimensional or one-dimensional electron gas layer, a zero-dimensional quantum box, and electron wave interference. It is characterized in that it is selected from the group consisting of elements.

A resistance layer according to a ninth aspect is a resistance layer formed by diffusing impurities on a surface of a semiconductor layer between electrodes,
The semiconductor layer is provided with a recess, and impurities are diffused on a side surface and a bottom surface of the recess by using the doping method according to claim 1. The recess has a distance of a current flowing between the electrodes and a portion where the current flows. It is characterized by having a side surface area such that the cross-sectional area is a predetermined value.

A method of manufacturing a field effect transistor according to a tenth aspect of the present invention comprises:
A method for manufacturing a field effect transistor having a low-concentration doping layer immediately below a gate electrode, a high-concentration doping layer in source / drain regions, and a middle-concentration doping layer between the low- and high-concentration doping layers, wherein Forming a low-concentration doping layer, forming a gate electrode in the center of the upper surface of the low-concentration doping layer, and forming a non-doped SiOx film and a group V atom diffusion preventing film on the upper surface of the low-concentration doping layer And forming a high-concentration doping layer on both ends of the low-concentration doping layer, and heat treating the Si in the SiOx film to the substrate.
And forming a medium-concentration doping layer in the low-concentration doping layer except the lower side of the gate electrode,
Possess and forming an ohmic electrode on the upper surface of the high-concentration doped layer, x of the SiOx film is a x <2
It is characterized by

A method of manufacturing a field effect transistor according to claim 11 is a method of manufacturing a field effect transistor using a III-V group compound semiconductor substrate, wherein the compound semiconductor substrate is selectively etched substantially vertically. And a step of forming a laminated film of a non-doped SiOx film and a group V atom diffusion preventing film on the side surface and the upper surface of the selectively etched compound semiconductor substrate, and heat treating the compound semiconductor substrate on which the laminated film is formed. The inside of the SiOx film
Forming a compound operation layer is diffused into the semiconductor substrate of Si, compound source electrode on the semiconductor substrate of the upper surface of the operation layer, and forming a drain electrode, a gate on the active layer side of the compound semiconductor substrate A step of forming electrodes
However , x of the SiOx film is characterized by x <2 .

According to a twelfth aspect of the present invention, there is provided a method of manufacturing a field effect transistor, wherein a compound semiconductor substrate of a III-V group has an operating layer and an impurity diffusion layer, a gate electrode is provided on the operating layer, and the impurity is included. In a method of manufacturing a field effect transistor having a source electrode and a drain electrode provided on a diffusion layer, a step of etching a III-V group compound semiconductor substrate to form a step, and a step above the step. A step of forming an operating layer, a step of forming a laminated film of a non-doped SiOx film and a group V atom diffusion prevention film on a side portion of a compound semiconductor substrate and a lower portion of the step portion, and a compound semiconductor on which the laminated film is formed the heat treatment is performed to the substrate
By diffusing Si in SiOx film on the compound semiconductor substrate possess and forming the impurity diffusion layer, the SiOx
The x of the membrane is characterized by x <2 .

A method of manufacturing a field effect transistor according to a thirteenth aspect is the method of manufacturing a field effect transistor having a plurality of doping layers having different impurity concentrations on a III-V compound semiconductor substrate. to the family compound semiconductor substrate, the SiOx the SiOx film and the group V atom diffusion preventing film doped laminating in this order, by heat treatment in the group III-V compound semiconductor substrate
A step of diffusing Si in the film to form a doping layer, a step of removing the SiOx film and the group V atom diffusion preventing film in a required region, and a heat treatment to obtain the S
a region iOx film and the Group V atom diffusion preventing film exists, have a forming a high doping layer impurity concentration than the doping layer, x of the SiOx film x
<2 .

According to a fourteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor circuit element, wherein the group III-V compound semiconductor is doped with impurities to manufacture a semiconductor circuit element having conductive layers having different resistance values. A step of forming a non-doped SiOx film and a group V atom diffusion preventive film on the compound semiconductor in this order, a step of reducing the thickness of the group V atom diffusion preventive film in a portion where a conductive layer having a high resistance value is formed,
This III-V compound semiconductor is heat treated to obtain III-V
Possess a step of diffusing Si of the SiOx the film in the family compound semiconductor, x of the SiOx film x <2 Dearuko
And are characterized.

A method for manufacturing a semiconductor circuit element according to a fifteenth aspect is a method for manufacturing a semiconductor circuit element having conductive layers having different resistance values by doping a III-V group compound semiconductor with impurities. A step of forming a heterojunction layer by forming a wide bandgap semiconductor layer on a non-doped narrow bandgap semiconductor layer which is a semiconductor; and a step of forming a non-doped SiOx film and a group V atom diffusion prevention film on the heterojunction layer. A step of sequentially forming, a step of reducing the thickness of the V-group atom diffusion preventing film in a portion where a conductive layer having a high resistance value is formed, and a heat treatment of the III-V group compound semiconductor to perform III.
The Si of the SiOx the film -V compound in semiconductor possess a step of diffusing, x of the SiOx film x <2 der
It is characterized by

A method of manufacturing a field effect transistor according to a sixteenth aspect is a method of manufacturing a field effect transistor including a doping layer formed in a III-V compound semiconductor layer as a channel layer or an electron supply layer.
A step of forming a non-doped SiOx film and a group V atom diffusion preventing film in this order on the group III-V compound semiconductor layer, and a heat treatment to form the S in the group III-V compound semiconductor layer.
a step of diffusing Si in the iOx film to form the doping layer, and further performing a heat treatment on the doping layer,
The Si doping layer by further diffused into the group III-V compound semiconductor layer have a a step of thickening the doping layer, x of the SiOx film is characterized by an x <2.

A method for producing an electrically conductive region according to a seventeenth aspect is a method for injecting an impurity into a III-V compound semiconductor to produce a one-dimensional or two-dimensional electrically conductive region, wherein the III-V group compound is used. Non-doped SiOx for semiconductor
A step of forming a film and a group V diffusion prevention film in this order, a step of removing the group V diffusion prevention film other than the portion where the electrically conductive region is to be formed, and a heat treatment for the III-V group compound semiconductor. wherein possess a step of diffusing Si in SiOx film, x of the SiOx film is x <2 in
The features.

A method for forming a quantum wire according to claim 18 is
In the method of forming a quantum wire, a step of forming a step by forming a Si diffusion preventing layer on a III-V group compound semiconductor substrate, and a non-doped SiOx film and a group V atom diffusion preventing film on the Si diffusion preventing layer. In this order, a step of removing the SiOx film and the group V atom diffusion preventing film except for the portion formed on the side wall of the step, and the substrate that has undergone these steps is heated to form the SiOx film. Membrane from above I
To II-V group compound semiconductor substrate, allowed diffusion of Si through their contact surfaces, have a forming a quantum wire,
The x of the SiOx film is x <2 .

A method for forming a quantum wire according to claim 19 is
In a method of forming a quantum wire, a plurality of different III
A step of forming a non-doped SiOx film and a group V atom diffusion preventing film in this order on the surface of the substrate on which the group V compound semiconductors both appear on the same surface, and a heat treatment is performed to form a Si film from the SiOx film. And forming a diffusion portion having a difference in the depth direction in each of the III-V group compound semiconductors, and removing the portion on the front surface side of the substrate to leave the deeper diffusion portion a one-dimensional electron gas formed at the diffusion vicinity possess a step of a quantum wire, the S
The x of the iOx film is characterized by x <2 .

A method for forming a quantum wire according to claim 20 is as follows.
In a method of forming a quantum wire in which a carrier moves in a channel layer in a one-dimensional direction, III-
A step of stacking a narrow forbidden band semiconductor layer and a wide forbidden band semiconductor layer made of a group V compound semiconductor in this order, and a step of processing the cross-sectional shape into a sawtooth shape by etching utilizing the plane orientation dependence of the wide forbidden band semiconductor layer. And a step of forming an undoped SiOx film and a group V atom diffusion preventing film in this order on the sawtooth-shaped wide bandgap semiconductor layer, and performing a heat treatment to form the SiOx film on the surface of the wide bandgap semiconductor layer. S of the inner
There is a step of diffusing i to form a doping layer, and a step of forming a channel layer only in a narrow band gap semiconductor layer located below the sawtooth-shaped recess of the doping layer to form a quantum wire.
However , x of the SiOx film is characterized by x <2 .

The method of forming a quantum box according to claim 21 is a method of forming a quantum box in which carriers in a channel layer are confined in a three-dimensional direction, wherein a narrow bandgap semiconductor made of a III-V group compound semiconductor is formed on a substrate. A layer and a wide bandgap semiconductor layer in this order, a step of processing the wide bandgap semiconductor layer into a sawtooth shape by etching utilizing the plane orientation dependency of the wide bandgap semiconductor layer, and the wide bandgap semiconductor processed into the sawtooth shape A step of forming a non-doped SiOx film on the layer, a step of further forming a group V atom diffusion preventing film at a position where a quantum box is to be formed, and a heat treatment for forming the SiOx in a required region on the surface of the wide forbidden band semiconductor layer. forming forming a doping layer is diffused Si in the film, a channel layer only in a narrow bandgap semiconductor layer of the a lower serrated are under the recess and the doping layer located Possess a step of the quantum box Te, before
The SiOx film is characterized in that x is x <2 .

A quantum wire transistor according to a twenty-second aspect of the present invention is a quantum wire transistor including a quantum wire as a channel layer below an electrode, wherein a narrow forbidden band semiconductor layer is formed on a substrate and is formed on the narrow forbidden band semiconductor layer. A wide forbidden band semiconductor layer having a sawtooth cross section, a doping layer formed on the surface of the sawtooth wide forbidden band semiconductor layer by the doping method according to claim 1, and the doping layer. It is characterized in that it comprises a quantum wire formed only under the serrated recess and an electrode formed on the wide forbidden band semiconductor layer in a direction intersecting with the serrated recess.

A method of manufacturing a semiconductor circuit element according to a twenty- third aspect is a method of manufacturing a semiconductor circuit element having a diffusion layer having portions having different impurity concentrations on a substrate and having electrodes on the diffusion layer. A step of forming a semiconductor layer made of a III-V compound thereon, a step of forming a plurality of shields having different coating widths on the semiconductor layer with a predetermined size, and a surface of the shield and the shield. A step of forming a non-doped SiOx film and a group V atom diffusion preventing film in this order on the surface of the semiconductor layer having no object, and performing heat treatment to diffuse Si in the SiOx film into the semiconductor layer to form a diffusion layer. possess a step of, x of the SiOx film is a x <2
It is characterized by

A method of manufacturing a semiconductor integrated circuit according to a twenty-fourth aspect of the present invention is a method of manufacturing a semiconductor integrated circuit by forming a plurality of elements by doping a III-V group compound semiconductor with impurities to form a III-V compound on a substrate. Forming a heterojunction layer by forming a non-doped narrow bandgap semiconductor layer and a wide bandgap semiconductor layer which are group compound semiconductors in this order, and removing the wide bandgap semiconductor layer in a required region to form a narrow bandgap semiconductor layer And a step of forming a non-doped SiOx film and a group V atom diffusion preventive film on the narrow bandgap semiconductor layer and the wide bandgap semiconductor layer in this order, and by heat treatment, III
Forming a doped layer by diffusing Si of the SiOx the film -V compound in semiconductor, possess and forming an electrode on the doping layer, x of the SiOx film
It is characterized in that x <2 .

A method for manufacturing a semiconductor integrated circuit according to a twenty-fifth aspect is a method for manufacturing a semiconductor integrated circuit by forming a plurality of elements by doping a III-V group compound semiconductor with impurities, and forming a III-V compound on a substrate. Forming a heterojunction layer by forming a non-doped narrow bandgap semiconductor layer and a wide bandgap semiconductor layer which are group compound semiconductors in this order, and partially removing the wide bandgap semiconductor layer in a required region in the thickness direction S on the wide bandgap semiconductor layer with different film thickness
The SiOx film and the group V atom diffusion preventive film are formed, and a heat treatment is performed to form the SiOx in the III-V group compound semiconductor.
A step of diffusing Si in the film to form a doping layer,
Possess and forming an electrode on the doping layer, the
The x of the SiOx film is characterized by x <2 .

An electron wave interference element according to a twenty-sixth aspect is an electron wave interference element having a plurality of electron wave paths in the vicinity of the surface of a compound semiconductor, and the paths are formed by using the doping method according to the first aspect. It is a high concentration layer.

[0047]

According to the doping method of the present invention, a non-doped SiO _x film and a group V atom diffusion preventing film are formed in this order on a group III-V compound semiconductor and then heat-treated to form Si.
Si atoms, which are the constituent atoms of the O _x film, are diffused into the III-V group compound semiconductor below. Hereinafter, Si in the present invention
The functions and doping principles of the O _x film and the group V atom diffusion prevention film will be described by taking a GaAs substrate as the III-V group compound semiconductor and a SiN film as the group V atom diffusion prevention film as an example. FIG. 1 shows GaA as a III-V group compound semiconductor.
FIG. 2 is a structural diagram of a laminated film of a SiO _x film 2 on a s substrate 1 and a SiN film 3 which is a V-group atom diffusion preventing film, and FIG. 2 is an explanatory diagram showing the Si doping principle.

Non-doped S that contacts the GaAs substrate 1
The ratio of the constituent elements of the iO _x film 2 is controlled so that the Si atoms in the SiO _x film 2 can diffuse into the GaAs substrate 1. That is, the ratio of Si to O is not 1: 2 as in the thermally oxidized SiO ₂ film on the Si substrate, but Si is larger than this ratio (Si / O> 1/2, that is, x <2 or A SiO _x film 2 having a refractive index larger than 1.46) is used. Further, the SiO _x film 2 is at least the GaAs substrate 1.
As is well known for
Diffusion of Ga atoms, which are group II atoms, into the SiO _x film 2 easily occurs, and this characteristic plays an important role in the doping method of the present invention.

Further, the presence of the SiN film 3 has an important meaning in the doping method of the present invention in that it has a characteristic of preventing the out-diffusion of As which is a group V atom in the GaAs substrate 1.

Next, the principle of doping will be explained with reference to FIG.
Reveal As shown in FIG. 1, SiO _xFilm 2 / SiN film 3
When heat treatment is applied to the GaAs substrate 1 on which the laminated film of
As the temperature rises, it is a group III element in the GaAs substrate 1.
Ga atom is SiO_xDiffuses into the film 2 to diffuse Ga atoms
Therefore, Ga vacancies are generated in the GaAs substrate 1 (FIG. 2).
(a)). Then, to the Ga hole, SiO_xMembrane 2 to Group IV element
Si atoms are diffused (FIG. 2 (b)). Ga like this
The exchange process of atoms and Si atoms is deep in the GaAs substrate 1.
Spreads in the vertical direction (Fig. 2 (c)) and extends to a specified depth from the surface
Doping is realized. And Si atoms diffuse
The formed region becomes an n-type impurity layer. Note that normal SiO
_xThe film 2 is a group V element having a high dissociation pressure in the GaAs substrate 1.
Since it cannot completely prevent the outdiffusion of As atoms,
The As atom, which is a group V element in the aAs substrate 1, is also SiO 2._xfilm
2 is diffused into the SiN film 3, but the SiN film 3 spreads outside the As atoms.
To suppress the dispersion, so SiO_xIn the film 2, As atoms
When the saturated state is reached, further out diffusion of As atoms occurs.
Therefore, the generation of As vacancies is suppressed to a certain amount. Therefore,
In the GaAs substrate 1, only Ga vacancies are promoted.
As a result, SiO_xMembrane 2 to G
The diffusion of Si atoms into the aAs substrate 1 is also promoted.

In the resistance layer of claim 9 , a concave portion is provided on the surface of the semiconductor layer through which a current flows between the electrodes, and the current flows on the side surface of the concave portion. Therefore, depending on the side area of the concave portion, the distance through which the current flows. And the cross-sectional area can be set.

In the method of manufacturing a field effect transistor according to a tenth aspect of the present invention, after the gate electrode is formed, a diffusion source having a two-layer structure composed of a SiOx film and a group V diffusion prevention film is formed on the low concentration doping layer and heat treatment is performed. As a result, Si is doped into a substrate made of a III-V group compound such as GaAs, and a medium-concentration doping layer having a higher concentration than the low-concentration doping layer is formed between the low-concentration and high-concentration doping layers.

In the method of manufacturing a field effect transistor according to the eleventh aspect , III-V selectively etched substantially vertically is used.
A SiOx film and a group V atom diffusion preventing film are formed in this order over the entire surface of the group III compound semiconductor substrate, and then heat treatment is performed. Then, Si atoms are diffused into the compound semiconductor substrate by the above process. Here, if the film quality and film thickness of the SiOx film and the group V atom diffusion prevention film and the heat treatment conditions after film formation are changed, the diffusion state of Si atoms will change. Therefore, by adjusting these parameters, An operating layer having the impurity concentration and thickness of is obtained.

According to the twelfth aspect of the method of manufacturing a field effect transistor, a SiOx film and a group V atom diffusion prevention film are provided on the side of the step portion and below the step portion of the III-V group compound semiconductor substrate having the step portion. After forming in this order, heat treatment is performed. Then, Si atoms are diffused into the compound semiconductor substrate by the process described above. The laminated film of the SiOx film and the group V atom diffusion prevention film can be easily formed on the surface of the substrate regardless of the shape of the substrate. A diffusion layer can be formed. Film quality of SiOx film and group V atom diffusion prevention film,
When the film thickness and the heat treatment conditions after film formation are changed, the diffusion state of Si atoms changes. Therefore, by adjusting these parameters, an impurity diffusion layer having a desired concentration and thickness can be obtained.

In the method of manufacturing a field effect transistor according to a thirteenth aspect , after forming a doping layer by using the above-mentioned doping method, only a region where a high-concentration doping layer is formed is formed with a SiOx film and a group V atom diffusion preventing film. By further performing a heat treatment while leaving the above, a doping layer having a higher doping concentration can be easily formed.

According to a fourteenth aspect of the present invention, in the method of manufacturing a semiconductor circuit element, the above-mentioned doping method is used to control the film thickness of the SiN film to simultaneously form conductive layers having different resistance values by one heat treatment.

In the method for manufacturing a semiconductor circuit element according to the fifteenth aspect , in addition to the effect of the fourteenth aspect , since the conductive layers having different resistance values are formed in the heterojunction layer, the required modulation doped structure can be easily formed. It

According to a sixteenth aspect of the method for manufacturing a field effect transistor, a non-doped SiOx film and a group V atom diffusion preventing film are formed in this order on a group III-V compound semiconductor layer, and heat treatment is applied to the film. By performing a heat treatment on the doped layer, the Si in the doped layer is changed to III
Further diffuse into the group-V compound semiconductor layer to increase the thickness of the doping layer. Thereby, the current value and the threshold voltage of the FET can be increased, and the yield can be improved.

According to the seventeenth aspect of the present invention, the one-dimensional or two-dimensional electric conduction region is obtained by diffusing Si into the III-V group compound semiconductor based on the above-mentioned doping method. Moreover, according to this method, since it is not necessary to perform a process such as etching on the III-V group compound semiconductor, no defect is caused and a good electric conduction region can be obtained.

In the method of forming a quantum wire according to claim 18 , I
A SiOx film is deposited on the surface of the step formed by the Si diffusion prevention layer formed on the II-V group compound semiconductor substrate, and a group V atom diffusion prevention film is deposited thereon, and a group V atom diffusion prevention film is formed on the side wall of the step. Control the thickness of. The III-V group compound semiconductor substrate on which the SiOx film and the V-group atom diffusion preventing film are formed is heated to externally diffuse the III-group atoms, and Si is diffused into the holes generated therein. As a result, Si is diffused into the III-V compound semiconductor substrate without causing crystal defects.
Further, by controlling the thickness of the group V atom diffusion prevention film, the contact surface width between the III-V compound semiconductor substrate and the SiOx film is determined, and Si is diffused from the SiOx film to the III-V compound semiconductor substrate. At the very least, the channel width of the quantum wire is formed with high precision. Furthermore, since the Si diffusion prevention layer can be formed in a desired shape, the quantum wire can be formed in an appropriate shape along the sidewall of the step provided by the Si diffusion prevention layer.

In the doping method of the present invention, the depth of Si diffusion differs depending on the type of III-V group compound semiconductor to be diffused, and also the film quality, film thickness and heating temperature of the SiOx film and the V group atom diffusion preventing film. Determined by. Claim 1
In the method of forming a quantum wire of No. 9 , since Si is diffused in different kinds of III-V group compound semiconductors to form respective diffusion parts, and the difference in depth is used as the channel width of the quantum wires, By controlling the difference in depth, the quantum wire can be accurately formed with a desired channel width.

According to the twentieth aspect of the present invention, when the doping layer is formed on the surface of the sawtooth wide forbidden band semiconductor layer, the doping layer formed in the sawtooth-shaped recess is a narrow forbidden band semiconductor layer / wide forbidden band. The distance to the semiconductor layer interface becomes shorter,
Electrons are likely to accumulate only at this position in the narrow bandgap semiconductor layer, and a quantum wire is formed. As described above, in the method for forming a quantum wire according to claim 20, a defect such as an impurity or a crystal defect does not exist in the channel layer, and it is possible to form a fine quantum wire having extremely good characteristics. it can.

In the method of forming a quantum box according to claim 21 , a SiOx film is formed on the surface of the saw-tooth wide forbidden band semiconductor layer, and linear or striped V group atom diffusion prevention is performed in a direction intersecting with the saw-tooth unevenness. By forming a film and performing heat treatment, a doping layer is formed only at the position where the group V atom diffusion preventing film exists, and under the serrated concave doping layer, the narrow forbidden band semiconductor layer / wide forbidden band semiconductor layer interface is formed. The quantum box is formed only in the area close to. As described above, according to the method of forming a quantum box of claim 21 , a fine and high-quality quantum box can be formed.

In the quantum wire of claim 22, the quantum wire obtained by the method of claim 20 is applied to a transistor, and the quantum wire transistor has extremely good characteristics.

According to the semiconductor circuit element manufacturing method of the twenty- third aspect, the diffusion layers having different Si concentration distributions are formed immediately below the shield by utilizing the difference in the diffusion degree of Si under the shield having different coating widths.

In the method of manufacturing a semiconductor integrated circuit according to the twenty-fourth aspect , after forming the heterojunction layer, only the wide forbidden band semiconductor layer in the required region is removed to expose the narrow forbidden band semiconductor layer, and the narrow forbidden band semiconductor layer is formed. Further, since the SiOx film and the group V atom diffusion preventing film are respectively formed on the wide bandgap semiconductor layer under appropriate conditions, and the heat treatment is performed to dope, the required regions of the narrow bandgap semiconductor layer and the wide bandgap semiconductor layer are provided. It is possible to form a doping layer having a required concentration distribution. If electrodes are appropriately formed on each doping layer, an element having different characteristics, such as HEMT. A MESFET, a diode, or a resistor can be arbitrarily combined to form a monolithic structure, which enables high-density integration. If appropriate patterning is performed here to form the SiOx film and the group V atom diffusion preventing film, it is not necessary to perform element isolation, and elements having good characteristics can be easily made monolithic.

In the method of manufacturing a semiconductor integrated circuit according to the twenty-fifth aspect , after forming the heterojunction layer, the wide bandgap semiconductor layer in a required region is partially removed in the thickness direction thereof, and the wide bandgap semiconductor having a different film thickness is formed. SiOx on each layer under appropriate conditions
Since the film and the group V atom diffusion preventing film are formed and heat treatment is performed to dope, a doping layer having a required concentration distribution can be formed in a required region. If electrodes are formed on each doping layer, HEMTs having different doping layers can be monolithically formed, and high density integration is possible. If appropriate patterning is performed here to form the SiOx film and the group V atom diffusion preventing film, it is not necessary to perform element isolation, and elements having good characteristics can be easily made monolithic.

In the electron wave interference element of the twenty-sixth aspect, the electron wave propagates in the plurality of high-concentration layers (channel layers) located near the surface of the compound semiconductor, and controls the application of the electrostatic potential from the gate electrode. As a result, the interference state of electron waves propagating in each channel layer is controlled.

[0069]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments thereof.

First, an example of carrying out the doping method according to the present invention will be specifically described. In the doping method of the present invention, the state of doping occurrence (concentration distribution of electrons as a dopant) changes according to the film quality and film thickness of the SiO _x film, the group V atom diffusion preventing film used, the heat treatment temperature, and the like. To do. Each embodiment will be described with a focus on the occurrence of doping when these parameters are changed. In each of the following examples, as the group V atom diffusion preventing film, S was used.
iN film is used. The laminated film of SiO _x film / SiN film is
General P-CVD (Plasma-enhanced Chemical Vapor
Deposition) method, and using S as a source gas
SiH ₄ + N ₂ O is used during the formation of the iO _x film.
SiH ₄ + NH ₃ is used when forming the film. Further, in the following first to sixth examples, a GaAs substrate is used as the III-V group compound semiconductor, and in the seventh example, an AlGaAs film is used as the III-V group compound semiconductor.

(First Example) The first example is an example showing the relationship between the film quality of the SiO _x film and the occurrence state of doping. SiO _x on the GaAs substrate with only the film quality changed
A laminated film of film / constant SiN film is formed. Then 880
Rapid thermal annealing (° C, 5 sec.)
RTA) to remove Si atoms from the SiO _x film to GaAs
Diffuse on the substrate.

The conditions for forming the SiN film are as follows:
Its refractive index is 1.8. SiN film: SiH ₄ 15sccm, NH ₃ 200sccm; power
250 W; film formation temperature 300 ° C .; film thickness 450 Å For SiO _x film, the film thickness is kept constant and only the film quality is changed by changing the gas flow rate ratio (SiH ₄ / N ₂ O flow rate ratio) during film formation. It was Other conditions for forming the SiO _x film are as follows. SiO _x film: pressure 0.3 Torr; power 150 W; film formation temperature 3
00 ℃; film formation time 12sec.

Whether or not the doping is generated is determined based on the measurement result of the electron concentration by the CV method (Capacitance-Voltage measurement), and it is determined that the doping is caused by Si diffusion. SI
It was confirmed by MS (Secondary Ion Mass Spectrometry). FIG. 3 is a graph showing the occurrence of doping with respect to the film quality of the SiO _x film.
FIG. 4 is a graph showing the measurement results of the CV method and SIMS in an example. In FIG. 3, the film quality of the SiO _x film is, here, the refractive index (horizontal axis) and buffer hydrofluoric acid (HF: NH ₄ F =
It is defined by the etching rate (vertical axis) according to 1: 6). When the occurrence of doping is confirmed, the mark ◯ is given, and when it is not confirmed, the mark x is given.

As shown in FIG. 3, doping occurs when the refractive index of the SiO _x film is 1.5 or more and the etching rate by buffered hydrofluoric acid is 1600 Å or less. Usually, when the composition ratio of the SiO _x film formed by the plasma CVD method is Si / O = 1/2 (that is, x = 2), its refractive index is 1.46, so that the refractive index at which doping occurs is 1.5 or more. The composition ratio of the SiO _x film is Si / O> 1/2 (that is, x <
2), which means that XPS (X-ray Photoele)
ctron Spectroscopy: X-ray photoelectron spectroscopy). The results shown in FIG. 3 show that the deposition temperature of the SiO _x film is 3
Although the temperature is set to 00 ° C, the same doping result can be obtained even if only the film forming temperature is lowered to 250 ° C. Also, when the film formation temperature is lowered to 200 ° C, the refractive index that indicates the boundary of the occurrence of doping does not change much, but only the etching rate tends to increase, and it is confirmed that the state of doping occurrence is slightly different. did.

Further, from FIG. 4, it is confirmed that Si is diffused in the GaAs substrate, and that the electron concentration is about one digit lower than that of the diffused Si, but a high concentration layer of about 3 × 10 ¹⁸ cm ^-3 is formed. It can be confirmed that an ideal distribution state in which the electron concentration distribution is flat near the surface and steep at the diffusion front is obtained.

By the way, it has been confirmed that doping (Si diffusion) does not occur unless a SiN film for preventing As outdiffusion is laminated on the SiO _x film. When the SiN film formed by the plasma CVD method has a refractive index of more than 1.9, no Si diffusion phenomenon is observed. If the Si concentration in the SiN film is excessively increased to increase the refractive index, A which is an essential requirement of the present invention.
It has been reported that the inhibitory effect on the out-diffusion of s decreases (Reference: Matsushita et al., Electronic Device Research Society ED89-70, Institute of Electronics, Information and Communication Engineers). Therefore, the SiN film formed by the plasma CVD method used in this embodiment must have a refractive index smaller than 1.9. ECR (Electron Cyclo)
The tron resonance (electron cyclotron resonance) method can form a denser SiN film than the plasma CVD method. Therefore, the SiN film formed by the ECR method has a refractive index of 2.
The doping method of the present invention can be applied even if it is about 0.

(Second Embodiment) The second embodiment is an example showing the correlation between the gas flow rate and the electron concentration distribution during the formation of the SiO _x film. SiH ₄ / N ₂ O when forming a SiO _x film
FIG. 5 shows the result of the electron concentration distribution when the flow rate ratio was changed. SiO _x film formation conditions and heat treatment conditions (RTA)
Is as follows. The film forming conditions for the SiN film are the same as in the first embodiment described above. SiO _x film: SiH ₄ 5 sccm, N ₂ O 25 to 75 sccm; power 150 W; film formation temperature 300 ° C .; film thickness 50 Å; refractive index 1.5
~ 1.6 RTA: Temperature 880 ℃; Time 5sec.

From the results shown in FIG. 5, the N ₂ O flow rate was 25 to 35 sccm.
In the range of, the electron concentration does not change much as the flow rate increases, but the distribution depth increases. On the other hand, when the content exceeds this range, the electron concentration and the distribution depth thereof decrease, and at the N ₂ O flow rate of 70 sccm, the occurrence of doping could not be confirmed.
From the above results, it is understood that the electron concentration distribution can be controlled by the film quality of the SiO _x film even when the heat treatment under the same conditions is performed.

(Third Embodiment) The third embodiment is an example showing the correlation between the film thickness of the SiO _x film and the electron concentration distribution. FIG. 6 shows the result of the electron concentration distribution when the thickness of the SiO _x film to be formed was changed. The conditions for forming the SiO _x film and the heat treatment conditions (RTA) are as follows. The film forming conditions for the SiN film are the same as in the first embodiment described above. SiO _x film: SiH ₄ 5sccm, N ₂ O 25sccm; power
150W; Film forming temperature 300 ℃; Film thickness 50 to 400 Å; Refractive index 1.5
2 RTA: Temperature 880 ℃; Time 5sec.

From the results shown in FIG. 6, it can be seen that the electron concentration and its distribution depth tend to decrease as the thickness of the SiO _x film increases. It is considered that this is because as the SiO _x film becomes thicker, the amount of As diffusing out increases and the amount of Ga vacancies decreases. From the above results, it is understood that the electron concentration distribution can be controlled by the film thickness of the SiO _x film even when the heat treatment under the same conditions is performed.

(Fourth Embodiment) The fourth embodiment is an example showing the correlation between the film forming temperature of the SiO _x film and the electron concentration distribution. FIG. 7 shows the result of the electron concentration distribution when the film forming temperature of the formed SiO _x film was changed. The conditions for forming the SiO _x film and the heat treatment conditions (RTA) are as follows. The film forming conditions for the SiN film are the same as in the first embodiment described above. SiO _x film: SiH ₄ 10sccm, N ₂ O 20sccm; power
150W; Film forming temperature 200-320 ℃; Film thickness 150Å; Refractive index
1.5 to 1.62 RTA: temperature 880 ° C; time 5 sec.

From the results shown in FIG. 7, it can be seen that the electron concentration and the distribution depth thereof change when the film forming temperature of the SiO _x film changes. It is considered that this is because the quality of the SiO _x film changed due to the change in the film forming temperature. From the above results, even when the heat treatment under the same conditions is performed, the Si
It can be seen that the electron concentration distribution can be controlled by the film forming temperature of the O _x film.

From the results of the first to fourth embodiments as described above, in the doping method of the present invention, the electron concentration distribution is obtained with the film quality and film thickness of the SiO _x film to be formed as parameters even if the heat treatment conditions are constant. It is understood that the control of

(Fifth Embodiment) The fifth embodiment is an example showing the correlation between the film quality of the SiN film and the electron concentration distribution. Si
FIG. 8 shows the result of the electron concentration distribution when the SiH ₄ / NH ₃ flow rate ratio at the time of forming the N film was changed. The film forming conditions and the heat treatment conditions (RTA) of the SiN film are as follows. The film forming conditions for the SiO _x film are the same as those in the third embodiment described above (however, the film thickness is 50 Å) and are constant. SiN film: SiH ₄ 15sccm, NH ₃ 150 to 200sccm; power 250W; film forming temperature 300 ° C; film thickness 450Å RTA: temperature 880 ° C; time 5 sec.

From the results shown in FIG. 8, the electron concentration does not change much as the flow rate of NH ₃ increases, but the distribution depth increases. However, when the flow rate of NH ₃ was 150 sccm, the electron concentration distribution could not be measured. From the above results, it is understood that the electron concentration distribution can be controlled by the film quality of the SiN film even when the film forming conditions of the SiO _x film are kept constant and the heat treatment is performed under the same conditions.

(Sixth Embodiment) The sixth embodiment is an example showing the correlation between the heat treatment temperature and the electron concentration distribution. SiO _x
FIG. 9 shows the result of the electron concentration distribution when only the heat treatment temperature was changed while the film forming conditions of the film and the SiN film were kept constant. S
Film forming conditions and heat treatment conditions for the iO _x film and the SiN film (RT
A) is as follows. SiO _x film: SiH ₄ 5sccm, N ₂ O 25sccm; power
150W; Film forming temperature 300 ° C; Film thickness 50 Å SiN film: SiH ₄ 15sccm, NH ₃ 200sccm; Power 2
50W; film forming temperature 300 ° C; film thickness 450Å RTA: temperature 860 to 900 ° C; time 5 sec.

From the results shown in FIG. 9, it can be seen that the electron concentration and its distribution depth tend to increase as the heat treatment temperature rises. From the above results, it can be seen that the heat treatment temperature is one of the important parameters in controlling the electron concentration distribution in the doping method of the present invention as in the conventional diffusion method.

(Seventh Embodiment) In the seventh embodiment, AlGa which is a ternary compound semiconductor is used as a III-V group compound semiconductor.
This is an example using an As film. In the seventh embodiment, as shown in FIG. 10, MB is formed on a semi-insulating GaAs (100) substrate 4.
GaAs buffer layer 5 (film thickness: 7000Å) and Al _0.22 Ga _0.78 As film 6 (film thickness: 1) formed by the E method (Molecular Beam Epitaxy)
μm) laminated wafer structure is used. After the laminated film of SiO _x film / SiN film is formed on the Al _0.22 Ga _0.78 As film 6 having such a wafer structure, heat treatment is performed. Then, Si atoms are diffused from the SiO _x film into the Al _0.22 Ga _0.78 As film 6 by the same mechanism as in the case of GaAs, and the Al _0.22 Ga _0.78 As film 6 can be doped with impurities. In this case, the SiO _x film,
The film forming conditions and the heat treatment conditions (RTA) of the SiN film are as follows. SiO _x film: SiH ₄ 5sccm, N ₂ O 25sccm; power
150W; Film forming temperature 300 ° C; Film thickness 50 Å SiN film: SiH ₄ 15sccm, NH ₃ 200sccm; Power 2
50W; film forming temperature 300 ° C; film thickness 450Å RTA: temperature 880 ° C; time 5 sec.

AlGaA as III-V compound semiconductor
Even when s was used, it was confirmed that doping was caused by Si diffusion as in the case of using GaAs. It was also found that when the film quality and film thickness of the SiO _x film and SiN film to be formed and the heat treatment temperature were changed, the electron concentration and the distribution depth thereof were changed as in the case of GaAs.

FIG. 11 is a graph showing the electron concentration distribution when doping was performed using AlGaAs under the above conditions. FIG. 11 shows the case where doping was performed using GaAs under the same conditions as this. The electron concentration distribution is also shown. From the results of FIG. 11, it is understood that the distribution depth of the electron concentration is larger in AlGaAs. The main cause of such a difference is that assuming that the amount of Ga atoms out-diffused from GaAs and AlGaAs into the SiO _x film is similar,
Ga vacancy caused by external diffusion is A compared to GaAs.
It can be inferred that the Si atoms are deeply formed in lGaAs, and as a result, Si atoms are also diffused to a deep position.

Although GaAs and AlGaAs are used as the III-V group compound semiconductor in the above-mentioned embodiment, I
The present invention can be similarly applied to a III-V group compound semiconductor such as nP, InGaAs, InAlAs, and a heterojunction substrate including a plurality of layers of such a III-V group compound semiconductor. Further, in the above-mentioned embodiment, the SiN film is used as the group V atom diffusion preventing film, but as another example, an AlN film, a WSi film, a WSiN film or the like may be used.

In the above-described Examples 1 to 7, the method of controlling Si diffusion from the SiOx / SiN laminated structure film in the doping method of the present invention was described. Example 8 below
21 to 21, semiconductor devices to which the doping method of the present invention is applied will be described.

(Embodiment 8) Embodiment 8 is an example in which the doping layer according to the present invention is used as a resistance layer, and the resistance value can be freely changed while keeping the occupied area of the resistance region small. Is an example showing.

(Example 1) FIG. 12 is a schematic perspective view of a semiconductor device in which the resistance layer of Example 1 of Example 8 is formed, and FIG. 13 is a sectional view taken along line XX of FIG. . This semiconductor device has the following structure. A SiOx / SiN laminated film 12 capable of Si diffusion is deposited on a semiconductor substrate 11, and electrodes 14 and 14 are formed on both ends of the resistance layer with a proper distance.
On the surface of the semiconductor substrate 11 between the electrodes 14, 14, a swollen recess 13a,
A plurality of electrodes 13a are provided at equal intervals in the facing direction of the electrodes 14, 14 and are arranged in two rows in a direction perpendicular to the facing direction.
One side of a, 13a ... Is formed so as to be parallel to the facing direction of the electrodes 14, 14. Electrode 1 including the surfaces of recesses 13a, 13a ...
Impurities are diffused on the surface of the semiconductor substrate 11 between the four and fourteen, the diffused portion is the resistance layer 13, and the current flows through the electrodes 14,14.
It is designed to flow in the opposite direction.

In order to form such a resistance layer 13, first, a rectangular portion in plan view, which is a position where the resistance layer is to be formed, is etched on the semiconductor substrate 11 to form a swollen recess 13a, 13a ... Are formed at equal intervals. At this time, one side of the swastika type is formed so as to be parallel to one end of the rectangular portion. Then, a SiOx / SiN laminated film 12 is deposited on the semiconductor substrate 11 and impurities are diffused into the rectangular portion including the surfaces of the recesses 13a, 13a ... And the resistance layer 13 is formed. next,
Electrodes 14 and 14 are formed at positions facing the resistance layer 13 in the longitudinal direction so as to be in contact with the resistance layer 13.

In the resistance layer 13 thus formed, as described above, a current flows in the longitudinal direction of the resistance layer 13. The recesses 13a, 13a ... Have side faces in the same direction as the current and in the vertical direction (hereinafter referred to as fractal). As a result, the resistance layer 13 has a current flow distance, that is, an effective distance, which is longer than that of a conventional resistance layer (a resistance layer having no recessed portion as in this example, hereinafter referred to as a conventional example) by the depth of the side surface. It has a portion and a portion having an effective distance similar to that of the conventional example, and it can be said that the effective distance is longer than that of the conventional example as a whole.

The cross-sectional area perpendicular to the current direction, that is, the effective cross-sectional area, has a portion larger than the conventional example by the side area and a portion having the same cross-sectional area as the conventional example, and as a whole. Can be said to have a larger effective area than the conventional example. From this, it can be said that the resistance value of the resistance layer 13 is the same as that of the conventional resistance layer having the same area in plan view, and the saturation current value increases.

FIG. 14 is a schematic plan view showing different shapes of the above-mentioned recesses 13a, 13a .... 14 (a) is a square recess, and FIG. 14 (b) is the swastika-shaped recess described above.
FIG. 14C shows a shape in which the fractal dimension is higher than that of the swastika-shaped recess, and FIG. 14D shows a shape in which the fractal dimension of the portion D in FIG. 14C is further increased. By increasing the fractal dimension, the side area of the concave portion increases, so that the effective cross-sectional area of the resistance layer 13 increases. For example, assuming that the side area in the direction perpendicular to the current direction is 1.0 for the concave portion of FIG. 14 (a), it is 1.8 for the concave portion of FIG. 14 (b), 4.0 for the concave portion of FIG. 14 (c), and FIG. In the concave part of), it becomes 10.0, and the effective area of the resistance layer increases.

FIG. 15 shows the resistance layer 13 of Example 1 as shown in FIGS.
6 is a graph showing a current-voltage relationship when the fractal concave portions 13a, 13a ... Shown in (d) are formed. As is apparent from FIG. 15, the recesses shown in FIG. 14 (d) having a higher fractal dimension have a larger effective cross-sectional area of the resistance layer 13 and a larger saturation current value.

(Example 2) FIG. 16 is a schematic perspective view of a semiconductor device in which a resistance layer of Example 2 of Example 8 is formed, and FIG. 17 is a cross-sectional view taken along line XX of FIG. . This semiconductor device has the following structure. A SiOx / SiN laminated film 12 capable of Si diffusion is deposited on a semiconductor substrate 11, and electrodes 14 and 14 are formed on both ends of the resistance layer with a proper distance.
On the surface of the semiconductor substrate 11 between the electrodes 14, 14, a rectangular recess 13b,
A plurality of the electrodes 13b ... Are provided at equal intervals in the facing direction, with one side being parallel to the facing direction of the electrodes 14 and 14 with their ends aligned. Electrodes 14, 14 including the surfaces of the recesses 13b, 13b ...
Impurities are diffused on the surface of the semiconductor substrate 11 between them, and the diffused portion is the resistance layer 13, and a current flows between the electrodes 14 and 14 in the opposing direction.

In order to form such a resistance layer 13, first, a rectangular portion in a plan view, which is a position where the resistance layer is to be formed, is etched on the semiconductor substrate 11, and the rectangular portion is formed in the longitudinal direction. Recesses 13b, 13b, ... Eroded from one end to the other end in the direction perpendicular to are formed at equal intervals in the longitudinal direction. Then, a SiOx / SiN laminated film is formed on the semiconductor substrate 11.
12 is deposited, and impurities are diffused into the rectangular portion including the surfaces of the recesses 13b, 13b ... And the resistance layer 13 is formed. Next, electrodes 14 and 14 are formed at positions facing the resistance layer 13 in the longitudinal direction so as to be in contact with the resistance layer 13.

In the resistance layer 13 thus formed, as described above, a current flows in the longitudinal direction of the resistance layer 13. Recess
Since 13b, 13b ... Have side faces in the direction perpendicular to the current, the effective distance is longer than that of the conventional example, and the effective cross-sectional area is the same as that of the conventional example. From this, it can be said that the resistance value of the resistance layer 13 of Example 2 is larger than that of the conventional example having the same area in plan view.

(Example 3) FIG. 18 is a schematic perspective view of a semiconductor device in which the resistance layer of Example 3 of Example 8 is formed.
FIG. 19 is a sectional view taken along line XX of FIG. This semiconductor device has the following structure. A Si diffusing SiOx / SiN laminated film 12 is deposited on a semiconductor substrate 11,
Electrodes 14 and 14 are formed on both ends of the resistance layer with a proper distance. On the surface of the semiconductor substrate 11 between the electrodes 14 and 14, two rectangular recesses 13c and 13c are vertically spaced apart from each other so that their longitudinal directions are parallel to the facing directions of the electrodes 14 and 14. It is provided. Impurities are diffused on the surface of the semiconductor substrate 11 between the electrodes 14, 14 including the surfaces of the recesses 13c, 13c. This diffused portion is the resistance layer 13, and the current flows through the electrodes 14, 14
It is designed to flow in the opposite direction.

In order to form such a resistance layer 13, first, a rectangular portion in a plan view, which is a position where the resistance layer is to be formed, is etched on the semiconductor substrate 11, and the rectangular portion is formed in the longitudinal direction. Recesses 13c, 13c are formed by eroding from one end to the other end in a direction perpendicular to. Then, the semiconductor substrate 11
A SiOx / SiN laminated film 12 is deposited on the upper surface of the concave portion 13c, 1
Impurities are diffused into the rectangular portion including the 3c surface to form a resistance layer.
Form 13. Next, electrodes 14 and 14 are formed at positions facing the resistance layer 13 in the longitudinal direction so as to be in contact with the resistance layer 13.

In the resistance layer 13 thus formed, as described above, a current flows in the longitudinal direction of the resistance layer 13. Recess
Since 13c and 13c have side faces in the same direction as the current, the effective distance is the same as that of the conventional example, and the effective sectional area is larger than that of the conventional example. From this, the resistance value of the resistance layer 13 of Example 3 is
It can be said that the saturation current value is larger and smaller than the conventional example having the same area in plan view.

FIG. 20 shows the current flowing through the resistance layer 13 of Examples 2 and 3.
It is a graph which showed the relationship of voltage. As a conventional example, the area occupied by the resistance layer of the semiconductor layer shows the same current-voltage relationship of the resistance layer as in Examples 2 and 3. As is clear from Figure 20,
Example 2 has the same saturation current value as the conventional example,
It can be seen that the resistance value is large. Further, it can be seen that Example 3 has a large saturation current value and a small resistance value as compared with the conventional example.

(Embodiment 9) In Embodiment 9, GaA using a refractory metal which is becoming mainstream as a gate material at present is used.
sFET (Metal-Semiconductor Field Effect Transis
tor). The resistivity of refractory metal is generally about 100 times higher than that of Au-based material, and it is disadvantageous that the gate resistance becomes large especially in a low noise FET. Therefore,
A method is adopted in which the electrode shape is T-shaped to increase the cross-sectional area and reduce the gate resistance. However, when the umbrella portion of the T-shaped gate is enlarged in order to expand the gate cross-sectional area, a doping layer having a higher concentration than the channel layer is formed in the semiconductor layer below the umbrella portion to reduce the resistance between the source and the gate. On the other hand, it is difficult to form them in a self-aligned manner.
The ninth embodiment is made in view of such circumstances.

21 and 22 are schematic cross-sectional views showing the steps of a method for manufacturing a field effect transistor (FET) according to the ninth embodiment. First, Fig. 21 (a)
As shown in FIG. ³ , the n-layer selective implantation is performed on the semi-insulating GaAs substrate 21 to form the low concentration doping layer 22 (8 × 10 ¹⁷ cm ⁻³ ). Then, WSiN / Au is deposited by the sputtering method,
After that, a T-shaped gate electrode 23 (umbrella portion (Au) width 1.5 μm, leg portion (WSiN) width 0.5 μm) is formed at the center of the upper surface of the low concentration doping layer 22 by using ion milling and reactive ion etching (FIG. 21). (b)).

Then, a diffusion source 24 having a two-layer structure composed of a SiO _x film (x <2) / SiN film is formed on the entire surface by plasma CVD, and the surface of the low concentration doping layer 22 and the T-type electrode 23 are formed. Parts other than the surface of are removed. Further, a silicon oxide (SiO ₂ ) film 25 is deposited at 700 Å on the entire surface as a protective film for subsequent heat treatment (FIG. 22).
(c)). The conditions for forming the SiO _x film and the SiN film of the diffusion source 24 are as follows. SiO _x film: SiH ₄ 5sccm N ₂ O 25sccm; power
150W; Film forming temperature 300 ° C; Film thickness 50Å SiN film: SiH ₄ 15sccm NH ₃ 200sccm; Power 2
50W; film formation temperature 300 ℃; film thickness 450 Å

Next, selective ion implantation is performed on both ends of the low-concentration doping layer 22 to form a high-concentration doping layer 26 (2.5 × 10 ¹⁸ cm ⁻³ ) for the source / drain regions (FIG. 22).
(d)).

Then, a short heat treatment at 860 ° C. for 5 seconds activates the low-concentration doping layer 22 and the high-concentration doping layer 26, and Ga of the GaAs substrate 21 and S of the SiO _x film are S.
Substituting i for doping Si into the substrate from the diffusion source 24, a thickness of 400 Å and a concentration of 2 × 10 ¹⁸ cm ^{-3 under} the umbrella portion of the T-type gate electrode 23 as shown in FIG. 22 (e). A medium concentration doping layer 27 is formed. Here, the SiN film acts as an As diffusion prevention layer in the heat treatment. Finally, the ohmic electrode 28 is formed on the upper surface of the heavily doped layer 26 (FIG. 22).
(f)).

Table 1 shows a comparison between the characteristics of the FET according to the ninth embodiment and the FET without the diffusion layer 27 shown in FIG.

[0113]

[Table 1]

From Table 1, it can be seen that the FET according to Example 9 has improved static characteristics and high frequency characteristics. Table 1 shows the average values of the FETs formed within the 3-inch surface, and each characteristic was within ± 8% of the average value, and good uniformity was obtained.

In the heat treatment, Si of the SiO _x film of the diffusion source 24 diffuses into the GaAs substrate 21 and the low-concentration doping layer 22 below the umbrella portion of the T-type gate 23 for doping. FIG. 23 shows the electron concentration distribution in the depth direction of the diffusion layer 27 obtained under the above conditions. This concentration distribution is S
It can be controlled by the film quality of the iO _x film and the SiN film, the film thickness, and the heat treatment conditions.

Although the T-type gate electrode is used in this embodiment, the shape of the gate electrode is not limited to this. Further, the substrate may be a substrate made of a III-V group compound. Further, the SiN film is used as the As diffusion prevention layer in the heat treatment, and can be substituted with another V group atom diffusion prevention layer.

(Embodiment 10) Plasma C was used for producing a SiO _x / SiN laminated structure film in the doping technique of the present invention.
Since the VD method is used, selective doping can be performed at any place on the wafer with any shape. Example 10 shows an example of manufacturing a vertical GaAs MESFET utilizing this feature.

FIG. 24 is a schematic sectional view showing a step of the method for manufacturing the FET according to the tenth embodiment. First, semi-insulating G
The aAs substrate 31 is selectively etched substantially vertically (FIG. 24).
(a)). This etching is performed by dry etching by RIE (Reactive Ion Etching) using a mixed gas of CCl ₂ F ₂ and He.
The SiO _x film 32 is formed on the upper surface and the side surface of the GaAs substrate 31 selectively etched as described above by using the P-CVD method.
After the SiN film 33, which is a group V atom diffusion preventing film, is formed in this order, heat treatment is performed. Then, as mentioned above,
Si atoms in the SiO _x film 32 replace Ga atoms in the GaAs substrate 31 and diffuse into the GaAs substrate 31 to form GaAs.
An n-type operating layer 34 is formed on the upper surface and side surfaces of the substrate 31 (FIG. 24 (b)). Here, the film forming conditions of the SiO _x film 32 and the SiN film 33 and the heat treatment conditions (RTA) are as follows. SiO _x film: SiH ₄ 5sccm, N ₂ O 25sccm; power
150W; Film forming temperature 300 ° C; Film thickness 50 Å SiN film: SiH ₄ 15sccm, NH ₃ 200sccm; Power 2
50W; film forming temperature 300 ° C; film thickness 450Å RTA: temperature 880 ° C; time 5 sec.

Next, after removing the laminated film of the SiO _x film 32 and the SiN film 33 by etching, the Au / Ni / Au + Ge film to be the ohmic electrode is formed into a G film by vacuum evaporation.
After being deposited on the operating layer 34 on the upper surface of the aAs substrate 31, this is alloyed in a hydrogen gas atmosphere at 450 ° C. to form the source electrode.
35 and the drain electrode 36 are formed (FIG. 24 (c)).

Then, by the ECR-CVD method, the source
Si on the electrode 35 and the drain electrode 36 ₃N_FourMembrane 37 (Thickness:
 0.1 μm) and then Si₃N_FourShot on membrane 37
The Al film (thickness: 0.03μm) which becomes the junction is applied to the vacuum deposition method.
Deposition and contact with the operating layer 34 on the side surface of the GaAs substrate 31
A FET is manufactured by using the Al film as the gate electrode 38.
(Fig. 24 (d)).

In the above manufacturing process, P-CVD is used.
After the laminated film of the SiO _x film 32 and the SiN film 33 is collectively formed on the GaAs substrate 31 by the method, the heat treatment is collectively performed to form the operation layer 34. Therefore, the GaAs substrate selectively etched. The operating layer 4 having a uniform impurity concentration can be easily formed also on the side surface of 31, and the reproducibility is high, and the vertical GaAs FET can be manufactured with a high yield.

Further, since the gate electrode length can be controlled by the film thickness at the time of depositing the Al film, the gate electrode 38 of 0.05 μm or less can be manufactured with good reproducibility. Incidentally, in the above embodiment, the effective gate length is 0.03 μm, which is the thickness of the Al film. Since the gate length can be shortened in this way, the frequency rises (100 GHz
Above) can be expected.

Further, the distance between the source and the gate is set to the insulating film (S
The film thickness can be controlled by the film thickness of the i ₃ N ₄ film 37). For this reason, in the above-mentioned embodiment, the film thickness of the Si ₃ N ₄ film 0.1 μm is 0.1 μm.
Distance between gates. Thus, the distance between the source and the gate can be shortened, so that the source resistance can be reduced and the mutual conductance can be increased. Further, since the area occupied by one element is smaller than that in the horizontal configuration, higher integration can be achieved.

(Embodiment 11) Embodiment 11 is an embodiment of a high output power FET devised for the purpose of lowering the knee voltage, and the drain-source resistance can be reduced without lowering the gate breakdown voltage.

Example 1 FIG. 25 is a FET of Example 1 of Example 11.
It is a cross-sectional view showing the structure of. In FIG. 25, 50 is a semiconductor
It is a semi-insulating GaAs substrate as a substrate. GaAs
The substrate 50 has a step portion, and the step portion has a mesa shape.
The surface side of the upper part of the mesa of the GaAs substrate 50 is
To the predetermined depth from the operating layer (n layer) 45 is formed.
ing. In addition, from the side of the mesa of the GaAs substrate 50 to the bottom of the mesa
On the surface side up to the
To form a source region and a drain region at a specified interval.
N ⁺Layers 44, 44 are formed. GaAs substrate 50
On the surface of the upper part of the server, the game layer (n layer) 45 is connected to the gate.
Surface of the GaAs substrate 50 below the mesa where the electrode 42 is provided.
Has n⁺Source electrode 41 connected to layers 44 and 44 respectively
And a drain electrode 43. Formed on top of mesa
The length of the front side and the inner side of the operating layer 45 are respectively
2.3 μm and 1.7 μm, and the gate length of the gate electrode 42 is
0.5 μm. Gate-source distance (in source area
Some n⁺Distance from edge of layer 44 to edge of gate electrode 42), gate
To-drain distance (drain region n⁺Layer 44 edge?
To the edge of the gate electrode 42) is 0.4 μm,
1.4 μm, using such an offset gate structure
Increase the gate-drain breakdown voltage
I am trying.

When manufacturing an FET having such a structure, first, a resist is formed in a region other than the upper portion of the mesa, and then an accelerating voltage of 70 k is applied to the upper portion of the mesa using an ion implantation technique.
A dopant is implanted at eV and a dose amount of 2.5 × 10 ¹² cm ^-2 to form an operating layer 45 on the surface side of the GaAs substrate 50 above the mesa. Next, after removing the resist, another resist is patterned on the upper portion of the mesa, and an accelerating voltage 10 is applied to the surface of the GaAs substrate 50 including the mesa inclined surface by using an ion implantation technique.
Dopants are implanted at 0 keV and a dose of 5 × 10 ¹³ cm ^-2 to form n ⁺ layers 44, 44 on the surface side of the GaAs substrate 50 extending from the side of the mesa to the bottom of the mesa. Finally, the gate electrode 42, the source electrode 41, and the drain electrode 43 are separately formed by the metal deposition / lift-off method.

In the FET of Example 1, since the dopant is injected from the mesa inclined surface, the n ⁺ layers 44, 44 to be the source region and the drain region are formed as shown in FIG. 25, and the gate-drain distance is narrowed. Without increasing the drain-source distance. Therefore, the drain-source resistance can be reduced without lowering the gate breakdown voltage.

(Example 2) FIG. 26 shows a FET of Example 2 of Example 11.
It is a cross-sectional view showing the structure of. An n ⁻ layer 46 is formed in the operating layer 45 on the n ⁺ layer 44 side of the drain region. Other structures are
Since it is the same as the above-described example 1, the same parts are designated by the same reference numerals and the description thereof will be omitted. Of course, in Example 2 having such a structure, the same effects as in Example 1 can be obtained.

Example 3 FIG. 27 shows the FET of Example 3 of Example 11.
It is a cross-sectional view showing the structure of. In FIG. 27, 50 is III−
It is a semi-insulating GaAs substrate as a group V compound semiconductor substrate. The GaAs substrate 50 has a stepped portion, and the stepped portion has an inverted mesa shape. On the surface side of the inverted mesa upper portion of the GaAs substrate 50, an operating layer (n layer) 45 is formed from the surface to a predetermined depth. Has been formed. Further, on the surface side from the reverse mesa side portion of the GaAs substrate 50 to the lower portion of the reverse mesa, the n ⁺ layers 44 and 44 serving as the source region and the drain region are formed at a predetermined distance from the surface to a predetermined depth. Are formed. A gate electrode 42 is provided on the upper surface of the reverse mesa of the GaAs substrate 50 so as to be connected to the operating layer (n layer) 45.
A source electrode 41 and a drain electrode 43 are provided on the surface of the As substrate 50 below the reverse mesa, respectively, which are connected to the n ⁺ layers 44, 44, respectively. The surface side length and the inner depth side of the operating layer 45 formed on the reverse mesa are 2.3 μm and 1.7 μm, respectively, and the gate length of the gate electrode 42 is 0.5 μm. The distance between the gate and the source (the distance from the end of the n ⁺ layer 44 that is the source region to the end of the gate electrode 42) and the distance between the gate and the drain (the distance from the end of the n ⁺ layer 44 that is the drain region to the end of the gate electrode 42) are , 0.4 μm and 1.4 μm, respectively, and by using such an offset gate structure, the breakdown voltage between the gate and the drain is increased.

Next, a method for manufacturing the FET having the structure shown in FIG. 27 will be described with reference to FIG. 28 showing the steps. First, for a semi-insulating GaAs substrate 50, an etchant: CH (OH) COOH (tartaric acid) + H ₂ O
Etching is performed using ₂ + H ₂ O to form an inverted mesa step portion having an etching angle of 55 ° (FIG. 28 (a)).
After forming a resist in the area excluding the upper part of the reverse mesa, a dopant is injected into the upper part of the reverse mesa at an accelerating voltage of 70 keV and a dose amount of 2.5 × 10 ¹² cm ^-2 by using an ion implantation technique, and GaA is added.
The operating layer 45 is formed on the surface side of the reverse mesa upper portion of the s substrate 50 (FIG. 28 (b)).

Next, an impurity diffused layer (n ⁺ layer) to be the source region and the drain region is formed. In Example 3, the stepped portion has an inverted mesa shape. Therefore, in the ion implantation method of Example 1, It is impossible to form an impurity diffusion layer on the side of the reverse mesa. Therefore, in Example 3, the impurity diffusion layer (n ⁺ layer) is formed by the silicon diffusion technique described below.

An SiO _x film 47 (x <2) is formed on the side of the reverse mesa and under the reverse mesa of the GaAs substrate 50 by P-CVD.
After forming a SiN film 48 as a group V atom diffusion preventing film in this order, heat treatment is performed (FIG. 28 (c)). Then, as described above, the Si atoms in the SiO _x film 47 are converted into the GaAs substrate 50.
The Ga atoms therein are replaced and diffused into the GaAs substrate 50, and n ⁺ layers 44, 44 are formed on the side of the reverse mesa and under the reverse mesa (FIG. 28 (d)). Here, SiO _x film 47, SiN film
The film forming conditions and heat treatment conditions (RTA) of 48 are as follows. SiO _x film: SiH ₄ 5sccm, N ₂ O 25sccm; power
150W; Film forming temperature 300 ° C; Film thickness 50 Å SiN film: SiH ₄ 15sccm, NH ₃ 200sccm; Power 2
50W; film forming temperature 300 ° C; film thickness 450Å RTA: temperature 880 ° C; time 5 sec.

After that, the laminated film of the SiO _x film 47 and the SiN film 48 is removed by etching, and finally, the gate electrode 42, the source electrode 41,
The drain electrode 43 is formed separately, and the drain electrode 43 is formed as shown in FIG.
Produce ET.

In the FET of Example 3, SiO_xMembrane 47 and SiN
Due to the laminated film structure with the film 48, the dopant (S
Since i) is diffused, it becomes a source region and a drain region.
N ⁺Layers 44 and 44 are formed as shown in FIG.
Drain-source distance without reducing the rain distance
The distance can be shortened. Therefore, do not reduce the gate breakdown voltage.
In addition, the drain-source resistance can be reduced.

Example 4 FIG. 29 shows the FET of Example 4 of Example 11.
It is a cross-sectional view showing the structure of. An n ⁻ layer 46 is formed in the operating layer 45 on the n ⁺ layer 44 side of the drain region. Other structures are
Since it is the same as the above-mentioned example 3, the same parts are designated by the same reference numerals and the description thereof will be omitted. Of course, in Example 4 having such a structure, the same effect as that of Example 3 can be obtained.

While the n ⁺ layers 44 and 44 were formed by using the ion implantation technique during the manufacture of Example 1, a laminated film of SiO _x film and SiN film was formed as in the case of manufacture of Example 3. After that, a heat treatment is performed to diffuse n ⁺ by silicon diffusion from the SiO _x film.
The layers 44, 44 may be formed. Further, the operation layer 45 may be formed by using the technique for forming the n ⁺ layers 44, 44 in Example 3.

Next, a conventional FET (hereinafter referred to as a conventional example)
A comparison of the transistor characteristics, gate breakdown voltage, and source-drain resistance between the FET of Example 1 shown in FIG. 25 and the FET of Example 3 shown in FIG. 27 will be described. Table 2 shows the numerical results for each of these FETs.

[0138]

[Table 2]

From the results in Table 2, when the conventional example and the examples 1 and 3 of the example 11 are compared, the gate breakdown voltage of the examples 11 and 3 of the example 11 is not much different from that of the conventional example, and the drain-
It can be seen that the resistance between the sources is greatly reduced. Also, it can be seen that the knee voltage also decreases.

As described above, in the FET of the eleventh embodiment, since the impurity diffusion layers serving as the source region and the drain region are formed on the side of the step portion and below the step portion of the semiconductor substrate having the step portion, the gate is formed. The drain-source resistance can be reduced without lowering the breakdown voltage. As a result, the knee voltage is reduced and the output power is not restricted, providing a high-output, high-efficiency FET for power amplification. it can. Further, since the drain-source resistance is reduced, the transconductance gm can be increased and the transistor characteristics can be improved.

(Embodiment 12) Embodiment 12 shows an example of manufacturing an FET using the doping technique of the present invention to form an n-layer of a channel and an n ⁺ layer of a source / drain region by two heat treatments. Is.

(Example 1) FIG. 30 is a sectional view showing a step in the method of manufacturing the FET of Example 1 of Example 12. First, semi-insulating G
In the doping layer formation region on the aAs substrate 51, a diffusion source 52 is formed by stacking a non-doped SiO _x film (x <2) and a SiN film which is a group V atom diffusion prevention film in this order.
The film forming conditions of the diffusion source 52 are as follows. SiO _x film: SiH ₄ 10sccm, N ₂ O 20sccm; power
150W; Film forming temperature 300 ℃; Film thickness 100Å SiN film: SiH ₄ 15sccm, NH ₃ 200sccm, N ₂ 100scc
m; power 250W; film forming temperature 300 ° C; film thickness 400Å

Then, the first heat treatment (800 ° C., 30 seconds) is performed, and the n layer 53 (having a doping concentration of 2) is formed on the surface of the GaAs substrate 51.
A film thickness of × 10 ¹⁸ cm ^-3 and a film thickness of 0.03 μm is formed (Fig. 30 (a)).

Next, the diffusion source 52 in the required area is selectively removed, and the gate electrode 54 made of WSi which is a refractory metal is formed in that portion (FIG. 30 (b)). After that, when the second heat treatment (880 ° C., 5 seconds) is performed, the lower side of the diffusion source 52 is further doped, the doping concentration is higher than that of the n layer 53 (4 × 10 ¹⁸ cm ⁻³ ), and the film is formed. Thick (0.07 μm) n ⁺ layer
55 and 55 are selectively formed (FIG. 30 (c)). And n ⁺ layers
Remove the diffusion source 52 in the required area on 55, 55 and
Ohmic electrodes 56, 56 made of uGe / Ni / Au are formed (FIG. 30 (d)).

(Example 2) FIG. 31 is a cross-sectional view showing the steps of a method for manufacturing an FET of Example 2 of Example 12, which is a modulation-doped FET.
Shows the case. GaAs / AlGaAs in which a non-doped AlGaAs layer 58 is laminated on a non-doped GaAs layer 57 by the MBE (molecular beam epitaxial growth) method.
On the substrate, the diffusion source 52 is formed in the region where the doping layer is formed, as in the case of Example 1 described above. Then, the first heat treatment (800 ° C., 30 seconds) is performed, and the n-layer 53 is formed on the AlGaAs layer 58.
(Doping concentration 2 × 10 ¹⁸ cm ⁻³ , film thickness 0.06 μm) is formed (FIG. 31 (a)).

Next, the diffusion source 52 in the required region is selectively removed, and the gate electrode 54 made of WSi which is a refractory metal is formed in that portion (FIG. 31 (b)). After that, when the second heat treatment (880 ° C., 5 seconds) is performed, the lower side of the diffusion source 52 is further doped, the doping concentration is higher than that of the n layer 53 (4 × 10 ¹⁸ cm ⁻³ ), and the film is formed. Thick (0.15 μm) n ⁺ layer
55 and 55 are selectively formed (FIG. 31 (c)). And n ⁺ layers
Remove the diffusion source 52 in the required area on 55, 55 and
When the ohmic electrodes 56, 56 made of uGe / Ni / Au are formed, the two-dimensional electron gas layer is formed only below the gate electrode 54.
A modulation-doped FET having 59 formed is obtained (FIG. 31).
(d)).

FIG. 32 is a graph showing the electron concentration of the doping layer shown in FIGS. 30 and 31. GaAs (GaAs substrate
In both 51) and AlGaAs (AlGaAs layer 58), a doping layer having a higher doping concentration (electron concentration) and a deeper doping depth than the first time is formed by the second heat treatment. Thus, the temperature of heat treatment,
The doping concentration and the doping depth can be easily controlled by changing the time.

The doping concentration of the doping layer formed by using the method of the present invention can be easily adjusted to two or more by performing heat treatment twice or more.

In this embodiment, a GaAs substrate and Ga are used.
Although the As / AlGaAs heterojunction substrate has been described, it goes without saying that it can be applied to other III-V group compound semiconductor substrates.

(Embodiment 13) Embodiment 13 shows a method of controlling the film thickness of the upper SiN film to fabricate an enhancement mode FET and a depletion mode FET by one heat treatment. is there.

In the thirteenth embodiment, by controlling the film thickness of the SiN film in the above-described doping method of the present invention, it is possible to control the outward diffusion of V group atoms and the diffusion of Si atoms. We are using. FIG. 33 is a graph showing the relationship between the film thickness of the SiN film and the reciprocal of the sheet resistance of the diffusion layer (sheet conductivity). If the film thickness of the SiN film is 200 Å or more, there is almost no change in the sheet conductivity.
If it is less than Å, the sheet conductivity changes greatly.

FIG. 34 is an explanatory view showing a method of forming a conductive layer by utilizing this phenomenon. When a part of the SiN film 3 shown in FIG. 1 is thinned (FIG. 34 (a)) and heat-treated, SiN
A conductive layer 86 having a higher resistance than the conductive layer 85 formed in the thick portion of the SiN film 3 is formed in the thin portion of the film 3 (FIG. 34 (b)). The conductive layer 86 has a shallower diffusion depth and a lower carrier concentration than the conductive layer 85. Thus Si
By controlling the film thickness of the N film 3, it is possible to simultaneously form conductive layers having different resistance values by one heat treatment.

Further, in the thirteenth embodiment, in addition to the above-mentioned effects, since the conductive layers having different resistance values are formed in the heterojunction layer, the required modulation doped structure can be easily formed.

(Example 1) FIG. 35 is an explanatory view showing a method of manufacturing a GaAs type FET in Example 1 of Example 13. First, as shown in FIG. 35 (a), a parallel plate type RF plasma CVD apparatus is used to form SiO _x on a semi-insulating GaAs substrate 61.
A diffusion source 64 composed of the film 62 and the SiN film 63 is formed under the following conditions. SiO _x film 62: SiH ₄ 10sccm, N ₂ O 30sccm; power 150W; film forming temperature 300 ° C; film thickness 50Å SiN film 63: SiH ₄ 15sccm, NH ₃ 200sccm; power
250W; Film forming temperature 300 ℃; Film thickness 60Å

Then, a resist is formed at the position where the conductive layer is to be formed.
65 is formed, and the diffusion source 64 in the portion not covered with the resist 65 is removed.

Next, after removing the resist 65, a resist 66 is formed as a dummy gate at the position where the gate electrode is to be formed (FIG. 35 (b)). Then, a SiN film 67 that can be formed at room temperature is formed on this surface by the ECR-CVD method under the following conditions, and then the resist 66 is removed by the lift-off method to form an inverted pattern (FIG. 35 (c)). SiN film 67: SiH ₄ 13sccm, N ₂ 30sccm; power 600
W: Film formation temperature Room temperature; Film thickness 1000Å

When heat treatment is carried out at 880 ° C. for 5 seconds in this state, Si atoms are sufficiently diffused into the GaAs substrate 61 in the region where the diffusion source 64 exists and the SiN film 67 exists, and the low resistance (sheet resistance value 250 Ω) is obtained. / □) conductive layer 68 is formed, but diffusion does not proceed sufficiently in the region where SiN film 67 does not exist, the diffusion depth is shallower than conductive layer 68, and the resistance value is high (8
A conductive layer 69 is formed (00Ω / □) (FIG. 35 (d)). Then, the diffusion source 64 on the conductive layer 69 is removed by etching, and the gate electrode G
Are formed in a self-aligned manner, the diffusion source 64 in the ohmic electrode formation region on the conductive layer 68 is removed by etching, and the ohmic electrode O is formed to form a FET (FIG. 35 (e)). As described above, by using the thirteenth embodiment, it is possible to form two kinds of conductive layers by one heat treatment.

(Example 2) FIG. 36 is an explanatory view showing a method of manufacturing the E-type and D-type FETs in Example 2 of Example 13. First, as shown in FIG. 36 (a), the E-type and D-type FETs on the semi-insulating GaAs substrate 61 are processed by the same method as the above-mentioned embodiment.
Diffusion source consisting of SiO _x film 62 and SiN film 63 in the formation region
Forming 64. Then, the SiN film 67 is formed in a region other than the position where the gate electrode is formed.

Next, the D-type FET formation region is covered with a resist 70 to expose the SiN exposed in the E-type FET formation region.
The film 63 is removed by etching with 20 Å buffered hydrofluoric acid (Fig. 36).
(b)). Then, after removing the resist 70, heat treatment is performed at 880 ° C. for 5 seconds.
Atom diffusion is most suppressed and resistance is high (3000Ω / □)
The conductive layer 71 is formed. SiN film in D-type FET formation region
The conductive layer 72 having a resistance slightly lower than that of the conductive layer 71 (800 Ω / □) is formed in the portion not covered with 67, and the resistance covered with the SiN film 67 is even lower (250 Ω / □). The layer 73 is formed (FIG. 36 (c)).

Thereafter, the diffusion source 64 and the SiN film 67 other than the boundary between the conductive layers and the elements are removed, the gate electrode G is formed on the conductive layers 71 and 72, and the ohmic electrode O is formed on the conductive layer 73. Formed (FIG. 36 (d)). Then the gate bias is 0V
A D-type FET in which current sometimes flows and an E-type FET in which current does not flow at 0 V are simultaneously formed.

(Example 3) FIG. 37 shows an example 3 of the thirteenth embodiment.
A method for manufacturing an AlGaAs / GaAs modulation-doped FET
It is an explanatory view shown. First, as shown in Fig. 37 (a), semi-insulating
Undoped AlGaAs (Al
Composition 0.22) After forming layer 74, SiO _xMembrane 62 and SiN
A diffusion source 64 consisting of the film 63 is formed under the same conditions as described above.
It Then, a resist 75 is formed at the position where the conductive layer is to be formed.
The diffusion source 64 on the part not covered by the resist 75.
Remove.

Next, after removing the resist 75, a resist 76 is formed as a dummy gate at the position where the gate electrode is to be formed (FIG. 37 (b)). Then, an SiN film 67 that can be formed at room temperature by ECR-CVD is formed on this surface under the same conditions as described above, and then the resist 76 is removed by lift-off to form an inverted pattern (FIG. 37 (c)). .

When heat treatment is performed at 880 ° C. for 5 seconds in this state, Si atoms are sufficiently diffused into the GaAs substrate 61 and the AlGaAs layer 74 in the region where the diffusion source 64 exists and the SiN film 67 exists (diffusion depth). 1500 Å) Low resistance (250Ω / □)
Conductive layer 77 is formed. On the other hand, in the region where the SiN film 67 does not exist, the AlGaAs layer 74 diffuses to the middle (diffusion depth 400 Å), and the AlGaAs diffusion doping layer 78 serves as an electron supply layer, and the AlGaAs / GaAs interface G
A two-dimensional electron gas layer 79 (1200Ω / □) is generated on the side of the aAs layer, and a modulation doping structure is formed (FIG. 37 (d)). Then, the diffusion source 64 on the diffusion doping layer 78 is removed by etching, the gate electrode G is formed in a self-aligned manner, the diffusion source 64 in the ohmic electrode formation region on the conductive layer 77 is removed by etching, and the ohmic electrode O is formed. To form a modulation doped FET (FIG. 37 (e)).
As described above, by using the thirteenth embodiment, it is possible to form the modulation-doped FET by one heat treatment.

Example 4 FIG. 38 shows E in Example 4 of Example 13.
FIG. 6 is an explanatory diagram showing a method for manufacturing a D-type and D-type AlGaAs / GaAs modulation-doped FET. First, as shown in FIG. 38 (a), non-doped AlG is formed on a semi-insulating GaAs substrate 61.
After forming the aAs layer 74, a SiO _x film is formed in the conductive layer forming region.
A diffusion source 64 composed of 62 and the SiN film 63 is formed under the same conditions as described above. Then, the SiN film 67 is formed in a region other than the position where the gate electrode is formed.

Next, the formation region of the D-type modulation doped FET is covered with a resist 70, and the SiN film 63 exposed in the E-type modulation doped FET formation region is removed by etching with 20 Å with buffer hydrofluoric acid (FIG. 38 (b)). ). Then, after removing the resist 70 and performing a heat treatment at 880 ° C. for 5 seconds, as shown in FIG. 38 (c), the diffusion of Si atoms is most suppressed in the portion where the SiN film 63 is partially removed (diffusion depth). 200Å) AlGaAs diffusion doping layer 80 is formed. In addition, D-type modulation-doped FE
A portion of the T formation region not covered with the SiN film 67 has a diffusion depth slightly deeper than that of the diffusion doping layer 80.
An As diffusion doping layer 81 is formed (diffusion depth 400
Å), 2 on the GaAs layer side of the AlGaAs / GaAs interface
The three-dimensional electron gas layers 83 (5000Ω / □) and 84 (1200Ω / □) are formed, respectively. The two-dimensional electron gas layer 84 has a smaller carrier concentration than the two-dimensional electron gas layer 83. Further, a conductive layer 82 having a lower resistance (250Ω / □) is formed in the portion covered with the SiN film 67.

Thereafter, the diffusion source 64 and the SiN film 67 other than the boundary between the conductive layers and the elements are removed, the gate electrode G is formed on the conductive layers 80 and 81, and the ohmic electrode O is formed on the conductive layer 82. Form. Then, a D-type modulation doped FET in which current flows when the gate bias is 0 V and an E-type modulation doped FET in which current does not flow when 0 V are formed simultaneously (Fig.
38 (d)).

Although AlGaAs / GaAs is used as the heterojunction layer in the above-described embodiments, another heterojunction layer composed of a wide bandgap semiconductor layer and a narrow bandgap semiconductor layer which are III-V group compound semiconductors is used. It goes without saying that it can also be used.

(Example 14) The diffusion coefficient Dp of Si of the doping layer formed by using the doping technique of the present invention is D
p = 0.0216 exp (-2.19 eV / kT) (k: Boltzmann constant). Therefore, for example, even at a low temperature heat treatment of about 620 ° C., the diffusion coefficient is 1 × 10 ⁻¹⁴ cm ² / sec, and diffusion is possible even at such a temperature. The diffusion coefficient of Si in the Si-doped layer formed by MBE or ion implantation is one digit smaller than that, and very high temperature is required for re-diffusion, so that device characteristics cannot be controlled by re-diffusion. It was In Example 14, the doping layer of the present invention was used as a channel layer of a MESFET or HEMT (High E
lectron Mobility Transistor) is a technology that can be used when used in the electron supply layer, and after these FETs are manufactured, if the current value and the threshold voltage are smaller than the desired values, heat treatment is performed again. , The method of changing the doping files of the channel layer and changing their values to desired values.

(Example 1) FIG. 39 shows S in Example 1 of Example 14.
FIG. 7 is a cross-sectional view showing a structure in the process of forming an i-doping layer. As shown in FIG. 39, on a GaAs substrate 91 which is a III-V group compound semiconductor, a non-doped SiO _x film (x <
2) 92, and a SiN film 93 which is a group V atom diffusion prevention film on it
Is formed by the P-CVD method under the following film forming conditions. SiO _x film: SiH ₄ 10sccm, N ₂ O 20sccm; power
150W; film forming temperature 300 ° C. SiN film: SiH ₄ 15sccm, NH ₃ 200sccm; power 2
50 W; film formation temperature 300 ° C. Then, the first heat treatment by lamp heating is performed at 880 ° C. for 5 seconds to diffuse Si and dope the GaAs substrate 91 with a doping layer.
Forming 91a. As described above, the Si diffusion is performed by incorporating Si into the Ga holes formed in the GaAs substrate 91 by the heat treatment.

Next, the SiO _x film 92 and the SiN film 93 are removed and a second heat treatment is performed. Generally, the diffusion coefficient of a doping layer formed on a III-V compound semiconductor substrate by crystal growth or ion implantation is 1 × 10 ⁻¹⁵ to 2 × by heat treatment at 850 ° C.
It is 10 ⁻¹⁴ cm ² / sec, and heat treatment at such a high temperature for a long time is required to diffuse the doped layer by heat treatment. However, the doping layer formed by continuously depositing the non-doped SiO _x film and the SiN film on the III-V group compound semiconductor, for example, on the GaAs substrate, and performing the heat treatment to diffuse Si is a group S site occupying the group III site.
Since i (Si _Ga ) and Ga vacancy (V _Ga ) form a pair and diffuse at the closest position by the action of Coulomb force, this (Si
The diffusion coefficient Dp of the _Ga- V _Ga ) pair is larger than the diffusion coefficient of Si alone and has the above-mentioned numerical value, and diffusion is possible even at such a temperature.

FIG. 40 shows a doping layer when the first heat treatment is performed and when the second heat treatment is additionally performed.
9 is a graph showing the relationship between the depth of 91a and carrier concentration. The vertical axis represents the carrier concentration and the horizontal axis represents the depth of the doping layer. The second heat treatment is 600 ℃ for 30 seconds, 700 ℃
It was performed under two conditions of 30 seconds. As is clear from FIG. 40, the carrier concentration is slightly decreased after the second heat treatment and the doping layer is thicker than that after the first heat treatment, and the Si is further deepened by the second heat treatment. You can see that it has been diffused. Further, since the degree of diffusion of Si differs depending on the difference in the second heat treatment condition, it is understood that the depth of the doping layer 91a can be controlled by the heat treatment condition.

(Example 2) Next, Example 2 of the present Example 14 provided with a doping layer by Si diffusion of the present invention as a channel layer.
The FET will be specifically described. Figure 41 shows this example 2
3 is a schematic cross-sectional view showing the structure of MESFET in the manufacturing stage according to FIG. GaA which is a III-V group compound semiconductor
A non-doped SiO _x film (x <2) 92 is formed on the s substrate 91, and a SiN film 93 is formed thereon using the plasma CVD method under the above-described conditions. Then, the first heat treatment is performed by lamp heating at 860 ° C. for 5 seconds, and a doping layer to be a channel layer is formed.
After forming 91a, the SiO _x film 92 and the SiN film 93 are removed. At this time, the thickness of the doping layer 91a is 450Å, and the carrier concentration is about 2 × 10 ¹⁸ cm ^-3 . Next, as shown in FIG. 41 (a), a WSi gate electrode 94 is formed on the doping layer 91a.
Is formed with a gate length of 0.5 μm and a gate width of 20 μm, and a Ni / Si / W source electrode 95 and a drain electrode 96 are formed with the gate length sandwiched.

The ME thus formed is shown in FIG. 41 (a).
A second heat treatment is performed on the SFET by heating the lamp at 600 ° C. for 45 seconds. By this heat treatment, Si in the doped layer 91a is diffused, and the GaAs substrate is formed as shown in FIG. 41 (b).
The doping layer 91b is formed at a position deeper than 91, and the thickness of the doping layer (91a + 91b) is increased.

Then, the ME before and after the second heat treatment is performed.
The DC characteristics of the SFET, that is, the drain current value Idss and the threshold voltage -Vth when the gate voltage is 0V are measured and compared.
Table 3 shows this result. As is clear from this table, the drain current value I
The values of dss and threshold voltage Vth can be increased.

[0175]

[Table 3]

As described above, when the drain current value Idss and the threshold voltage −Vth of the manufactured MESFET are lower than the desired values, it is possible to increase the desired values by performing the second heat treatment.

(Example 3) Next, the modulation-doped transistor according to Example 3 of Example 14 having a doping layer as an electron supply layer will be specifically described. FIG. 42 is a schematic cross-sectional view showing the structure of the modulation-doped transistor in the middle of the manufacturing process according to Example 3. As shown in Figure 42 (a),
MBE (Molecular B
eam Epitaxy: molecular beam epitaxy), and a SiO _x film 92 and a SiN film 93 are further formed thereon in this order. The conditions for forming the SiO _x film 92 and the SiN film 93 are the same as in Example 1. Then, the first heat treatment is performed by lamp heating at 840 ° C. for 5 seconds, and the doping layer 98 that becomes an electron supply layer from the surface of the AlGaAs layer 98 having a thickness of 500 Å to a depth of 400 Å
form a. At this time, the carrier concentration of the doping layer 98a is about 2 × 10 ¹⁸ cm ^-3 . At this time, the AlGaAs layer
A two-dimensional electron gas layer 99 is formed on the boundary surface between the 98 and the GaAs layer 97.

The SiO _x film 92 and the SiN film 93 are removed and the second
Heat treatment at 600 ℃ for 30 seconds. By this heat treatment,
Si in the doping layer 98a is diffused to form a doping layer 98b at a deeper position of the AlGaAs layer 98 as shown in FIG. 42 (b), and the doping layer (98a + 98b) becomes thicker.

The holes in the two-dimensional electron gas layer 99 of the modulation-doped transistor thus formed were measured before and after the second heat treatment for comparison. Table 4 shows these results. As is clear from this table, the second carrier heat treatment increases the sheet carrier concentration (cm ^-2 ) and decreases the hole mobility (cm ² / Vs). is doing. It is considered that this is because the thickness of the doping layer (98a + 98b) was increased by the second heat treatment.

[0180]

[Table 4]

Thus, also in the modulation doped transistor using the two-dimensional electron gas layer 99, the drain current value Ids
If the values of s and threshold voltage −Vth are lower than desired values,
A second heat treatment can be performed to increase the thickness of the doping layer 98a to a desired value.

(Embodiment 15) This embodiment 15 shows a basic production example of a two-dimensional electron gas region and a quantum wire using the doping technique of the present invention.

FIG. 43 is an explanatory view showing a method for producing an electrically conductive region in Example 15, and shows a case of producing a two-dimensional electrically conductive region. First, as shown in FIG. 43 (a), a non-doped i-GaAs layer 101a and a non-doped i-AlG layer are formed.
The hetero junction substrate 101 is formed by laminating the aAs layer 101b. Next, a SiO _x film 102a (100 Å) and a SiN film 102b (400 Å) are formed on the heterojunction substrate 101 by plasma CVD.
To form a diffusion source 102 (FIG. 43 (b)). These film forming conditions are as follows. SiO _x film: SiH ₄ 5sccm, N ₂ O 25sccm; power
150W; film forming temperature 300 ℃; film thickness 100Å SiN film: SiH ₄ 15sccm, NH ₃ 200sccm; power
250W Film formation temperature 300 ℃; Film thickness 400Å

Then, as shown in FIG. 43 (c), the SiN film 102b other than the desired region is removed by plasma etching. This etching is performed on the SiO _x film 102a and the SiN film 102b.
And a power of 250 W using a mixed gas of CF ₄ (17cc) + O ₂ (3cc) having a large selection ratio of After that, if heat treatment is performed for a short time, the i-AlGaAs layer only under the SiN film 102b is formed.
The Ga of 101b and the Si of the SiO _x film 102a are replaced, and
As shown in (d), i-AlGa only under the SiN film 102b is formed.
Si is diffused in the As layer 101b, and n-AlGa is diffused in this portion.
As layer 103 is formed. This n-AlGaAs layer 103
Since the electron concentration distribution at is steep at the diffusion front, a modulation-doped structure is formed and a good two-dimensional electric conduction region 104 can be obtained.

The carrier mobility and the sheet carrier concentration in the two-dimensional electric conduction region thus obtained and in the two-dimensional electric conduction region obtained by the conventional method in which the conductive layer is crystal-grown on the entire surface of the insulating substrate are measured. It shows in Table 5.

[0186]

[Table 5]

2 obtained according to Example 15 as shown in Table 5
The two-dimensional electric conduction region has substantially the same carrier mobility and sheet carrier concentration as the two-dimensional electric conduction region formed on the entire surface of the wafer which is widely used at present. According to the fifteenth embodiment, it is not necessary to perform a treatment such as etching on the conductive layer in order to form the two-dimensional electrically conductive region at a desired position, and defects are hardly generated. Therefore, the obtained two-dimensional electric conduction region has very excellent characteristics.

FIG. 44 shows the SiN film 102b shown in FIG. 43 (c) in the step of etching the SiN film up to the accuracy limit of the pattern.
The width of 102b is reduced and a one-dimensional electric conduction region is formed as a thin line. Also in this case, a very excellent one-dimensional electric conduction region 105 can be obtained.

(Example 16) This example 16 shows an example of producing a quantum wire using the doping method of the present invention.

(Example 1) FIGS. 45 to 48 are schematic sectional views of a III-V compound semiconductor substrate at the stage of forming quantum wires of Example 1 of Example 16. As shown in FIG. 45, a GaAs layer 112 of approximately 1 μm and undoped A of 50 Å are formed on a semi-insulating substrate 111.
The lGaAs layer 113, the 100-liter N-type AlGaAs layer 114, and the undoped AlGaAs layer 115 are laminated in this order to form a III-V group compound semiconductor substrate L having a modulation doping structure. Then, plasma CV is performed using SiH ₄ and NH _3.
By the D method, approximately 200 Å of SiN is formed on the AlGaAs layer 115.
A layer is deposited and dry etching is performed to form Si on the AlGaAs layer 115 corresponding to the region where the quantum wire is to be formed.
A step is provided by forming a SiN layer 116 which is a diffusion prevention layer.

Then, 5 sccm of SiH is formed by P-CVD method.
_As shown in FIG. 46, an SiO _x film 117 (x <2) of 50 Å is formed on the stepped AlGaAs layer 115 and SiN layer 116 at a film-forming temperature of 300 ° C. and N ₂ O of ₄ , 30 sccm. . Then, by plasma CVD method, 15 sccm of SiH ₄ , 200 scc
A 100 Å SiN film 118, which is the group V atom diffusion preventing film, is formed on the SiO _x film 117 at m ₃ NH ₃ and a film forming temperature of 300 ° C.

Then, as shown in FIG. 47, the SiN layer 116 is
The SiO _x film 117 and the SiN film 118 formed on the side walls of the SiO 2 film 117 remain and the other SiO _x film 117 and the SiN film 118 remain.
To remove. SiN film 118 / Si formed on this side wall
The O _x film 117 is a diffusion source for diffusing Si into the AlGaAs layer 115, and the width of the contact surface with the AlGaAs layer 115 is 15
It is 0Å. The width of this contact surface is controlled by the thickness of the SiN film 118 formed on the side wall of the SiN layer 116, and can be formed with high precision and thinness.

Next, heat treatment is applied to this substrate. As a result of this heat treatment, the group III atom A in the AlGaAs layer 115
l diffuses out, and vacancies are generated in the AlGaAs layer 115. Si is a group IV atom of the SiO _x film 117
Is spread. It is a group V atom in the AlGaAs layer 115.
The diffusion of As is suppressed by the SiN film 118. When Si is diffused in this way, crystal defects do not occur in the substrate.

By heat treatment at 880 ° C. for 5 seconds, as shown in FIG. 48, 150 Å of the AlGaAs layer 115 just below the diffusion layer of the SiN film 118 / SiO _x film 117, an S of about 1 × 10 ¹⁸ cm ^-3 was added.
The i atom is diffused to a depth of about 200Å to form a diffusion portion 119. As a result, carriers having a linear density of about 10 ⁶ cm ^-1 are generated here, and the quantum wire 120 having a channel width of 150 Å is formed.

The quantum wire thus formed can be formed with a high precision channel width without causing crystal defects and by controlling the thickness of the SiN film 118.

Example 2 FIGS. 49 to 52 are schematic cross-sectional views of III-V compound semiconductor substrates at the stage of forming quantum wires of Example 2 of Example 16. As shown in FIG. 49, the AlGa of the III-V group compound semiconductor substrate L of the modulation doping structure is formed.
Example 1 except that the As layer 115 has a stepped shape
The structure is similar to that of the compound semiconductor substrate, and the same reference numerals are given and description thereof is omitted. By plasma CVD using SiH ₄ and NH ₃ on the III-V compound semiconductor substrate L,
A SiN layer 116 of approximately 200 Å which is a Si diffusion preventing layer is deposited.

As shown in FIG. 50, dry etching is performed to leave the SiN layer 116 formed on the side wall of the step of the AlGaAs layer 115. Then, as shown in FIGS. 51 and 52, in the same manner as in Example 1, a 50 Å SiO _x film 117 is formed.
(X <2) and 100Å SiN which is a group V atom diffusion prevention film
The film 118 is formed under the same conditions as in Example 1. And 880 ℃,
After the heat treatment for 5 seconds, the AlGaAs layer 115 is diffused into the diffusion layer 11
9 is formed, and a quantum wire 120 having a channel width of 150Å is formed.

As described above, the quantum wire formed on the compound semiconductor substrate having a step has a high channel width without causing crystal defects and by controlling the thickness of the SiN film 118. It can be formed with precision.

Example 3 FIG. 53 is a schematic plan view of a compound semiconductor substrate having quantum wires formed therein according to Example 3 of Example 16. A disc-shaped SiN layer 116, which is a disk-shaped Si diffusion prevention layer, is formed on the AlGaAs layer 115 to form a step, and a SiO _x film (x <2) and a group V atom diffusion prevention film SiN are formed on the sidewalls of the step. By forming a film and heat-treating it, a diffusion part 119 is formed as shown in FIG. Thus, SiN
A ring-shaped quantum wire can be formed by depositing the layer 116 in a disk shape. Thus, the SiN layer 11
Since the diffusion portion 119 is formed along the side wall of 6, the quantum wire can be formed in an appropriate shape.

(Embodiment 17) This embodiment 17 is also the same as the above embodiment.
Similarly to 16, it shows an example of manufacturing a quantum wire using the doping method of the present invention.

(Example 1) FIGS. 54 to 57 are schematic cross-sectional views of a substrate showing a step of forming quantum wires in Example 1 of Example 17.
As shown in FIG. 54, Ga that is a III-V compound semiconductor
The As layer 121 and the AlGaAs layer 122 are heterojunctioned to form a substrate. As shown in FIG. 55, the GaAs layer 121
And 100 Å SiO _x (x <
2) The film 123 was formed by plasma CVD using SiH ₄ 5sccm,
N ₂ O 25sccm, deposited at a film forming temperature of 300 ° C., on which V
A 400Å SiN film 124, which is a group atom diffusion preventing film, is deposited by plasma CVD at SiH ₄ 15sccm, NH ₃ 200sccm, and a film forming temperature of 300 ° C.

Next, heat treatment is performed at 880 ° C. for 5 seconds.
As shown in 56, the AlGaAs layer 122 has a diffusion portion a with a depth of 800 Å, and the GaAs layer 121 has a diffusion portion b with a depth of 600 Å.
Is formed. As described above, the GaAs layers 121 and A
In the lGaAs layer 122, there is a difference in the diffusion depth of Si. Then, as shown in FIG. 57, the GaAs layer 121 and the AlGaAs layer 122 corresponding to the depth of the diffusion portion b, and the Si
The N film 124 and the SiO _x film 123 are removed by dry etching. As a result, a diffusion portion A in which Si is diffused to a depth of 200 Å is formed in the AlGaAs layer 122.
A one-dimensional electron gas is formed in the vicinity of the diffusion portion A at the interface between the s layer 121 and the AlGaAs layer 122, and becomes a quantum wire 130 having a channel width of 200Å. In this way, a thin quantum wire with a precise channel width can be formed without causing crystal defects.

Example 2 FIGS. 58 to 61 show Example 2 of Example 17.
It is a typical sectional view of a substrate showing a formation step of a quantum wire.
As shown in FIG. 58, a step formed of a III-V group compound semiconductor
The AlGaAs layer 122 is formed on the GaAs layer 121 having
The junction surface of is heterojunction perpendicular to the step direction. Fig. 59
As shown in FIG.
100Å SiO on the surface_x(X <2) film 123, P-CV
SiH by D method_Four5sccm, N ₂O 25sccm, film forming temperature 3
Deposited at 00 ° C, and on top of it is a group V atom diffusion preventive film 4
The SiN film 124 of 00Å is SiH by plasma CV._Four15
sccm, NH₃Deposition is performed at 200 sccm and a film forming temperature of 300 ° C.

[0204] As shown in FIG. 60, as to leave the SiO _x film 123 and the SiN film 124 formed on the side wall of the step, the SiO _x film 123 and the SiN film 124 other than the region is removed by dry etching. And 880 ℃, 5se
The AlGaAs layer 122 is heated to a depth of 8
A diffusion portion a of 00Å and a diffusion portion b having a depth of 600Å are formed in the GaAs layer 121.

Then, as shown in FIG. 61, the GaAs layer 121, the AlGaAs layer 122, the SiN film 124, and the SiO _x film 123, which correspond to the depth of the diffusion portion b, are removed by dry etching. As a result, a diffusion portion A in which Si is diffused up to 200 Å in the diffusion direction is formed in the AlGaAs layer 122, and a one-dimensional electron gas is formed in the vicinity of the diffusion portion A at the bonding surface of the GaAs layer 121 with the AlGaAs layer 122. Channel width
It becomes a quantum wire 130 of 200 Å. In this way, a thin quantum wire with a precise channel width can be formed without causing crystal defects.

(Example 3) FIGS. 62 and 63 are schematic sectional views of a substrate showing a step of forming quantum wires in Example 3 of Example 17.
As shown in FIG. 62, an AlGaAs layer 122 is formed on a stepped GaAs layer 121, which is a III-V group compound semiconductor, and its junction surface is heterojunction perpendicular to the step direction. The GaAs layer 121 and the AlGaAs layer 122 which are parallel to this junction surface
On top, SiN layers 125 and 125 are deposited by the ECR-CVD method. And a 100 Å SiO _x (x <2) film on the surface
123, SiH ₄ 5sccm, N ₂ O 25 by P-CVD method
The film is deposited at a sccm film forming temperature of 300 ° C., and a 400 Å SiN film 124, which is a group V atom diffusion preventing film, is deposited thereon by a P-CVD method, SiH ₄ 15 sccm, NH ₃ 200 sccm, film forming temperature 300 ° C.
Is deposited at. Then, heat treatment is performed at 880 ° C. for 5 seconds to form a diffusion portion a having a depth of 800 Å in the AlGaAs layer 122.
A diffusion portion b having a depth of 600Å is formed in the GaAs layer 121.

Then, as shown in FIG. 63, the GaAs layer 121, the AlGaAs layer 122, the SiN layers 125, 125, the SiN film 124, and the SiO _x film 123 corresponding to the depth of the diffusion portion b are removed by dry etching. This allows AlGaA
In the s layer 122, a diffusion portion A in which Si is diffused to a depth of 200Å is formed, and the AlGaAs layer 122 of the GaAs layer 121 is formed.
A one-dimensional electron gas is formed in the vicinity of the diffusion part A at the junction surface with and becomes a quantum wire 130 with a channel width of 200Å. In this way, a thin quantum wire with a precise channel width can be formed without causing crystal defects.

The difference between the depths of the diffusion portions changes depending on the film quality, the film thickness and the heating temperature of the SiO _x film and the group V atom diffusion preventing film formed on different kinds of III-V group compound semiconductors. The channel width of the quantum wire can be controlled by changing these conditions.

(Embodiment 18) This embodiment 18 shows a method of manufacturing a quantum wire and a quantum box using the doping technique of the present invention. Even if the pattern size is large in this manufacturing method, 20
Electrons can be confined to sizes below 0 Å.

FIG. 64 is a sectional view showing a quantum wire (or quantum box) obtained in the eighteenth embodiment. GaAs substrate 13
A GaAs layer 132, which is a narrow bandgap semiconductor layer, and an AlGaAs layer 133, which is a wide bandgap semiconductor layer, are stacked on top of each other, and the surface of the AlGaAs layer 133 is processed into a sawtooth shape. A SiO _x film 140 and a SiN film 141, which is a group V atom diffusion preventing film, are formed in this order and heat-treated to form a doping layer 13 on the surface of the AlGaAs layer 133.
6 are formed. Since the doping layer 136 formed in the sawtooth-shaped recess is close to the narrow bandgap semiconductor layer / wide bandgap semiconductor layer interface, the narrow bandgap semiconductor layer (Ga) at this position is formed.
Electrons are easily accumulated in the As layer 132), and electrons are less likely to be accumulated in other portions because the distance from the interface is long, and as a result, the region where electrons are accumulated is limited to a very small width, and the quantum layer is a channel layer having an extremely narrow width. Wire 137 (or quantum box 14)
2) You can get

FIG. 65 is an explanatory view showing the method of forming quantum wires in the eighteenth embodiment. First, on a semi-insulating GaAs substrate (100) 131, GaAs which is a narrow band gap semiconductor layer is formed.
Layer 132 (thickness 8000Å) and wide bandgap semiconductor layer Al
AlGaAs layered with a GaAs layer 133 (film thickness 2000Å)
/ GaAs substrate is formed. Photoresist on it 13
4 is patterned in a stripe shape, and bromethanol (Br ₂ = 1 wt%) is used to etch the AlGaAs layer 133 in a sawtooth shape. At this time, since bromethanol is used as an etchant, (11
1) It is possible to utilize the plane orientation dependency of the etching rate at which the surface appears, and the portion where the photoresist 134 does not exist is V-shaped etched, resulting in AlG.
The aAs layer 133 can be processed into a sawtooth shape (FIG. 65).
(a)).

After removing the photoresist 134, a diffusion source 135 composed of a SiO _x film and a SiN film which is a group V atom diffusion preventing film is formed on the surface of the sawtooth AlGaAs layer 133 by the plasma CVD method under the following conditions. Form (Fig. 65
(b)). SiO _x film: SiH ₄ 10sccm; N ₂ O 20sccm; RF power 150W; film formation temperature 300 ° C; film thickness 150Å SiN film: SiH ₄ 15sccm; NH ₃ 200sccm; RF power 250W; film formation temperature 300 ° C; film thickness 450Å

Then, the Si atoms of the SiO _x film are diffused into the AlGaAs layer 133 by a short-time heat treatment at 880 ° C. for 5 seconds to form a doping layer 136 having an electron concentration of 3 × 10 ¹⁸ cm ⁻³ and a diffusion depth of 400 Å. . Then, the AlGaAs layer 133
Electrons are accumulated in the GaAs layer 132 below the sawtooth-shaped concave portion to form the quantum wire 137 (FIG. 65 (c)).

Here, after removing the diffusion source 135, the Schottky electrode 138 is formed on the doping layer 136 (FIG. 65).
(d)), when this electrode is biased, the doping layer 13
It is possible to limit the area where electrons are accumulated within 6,
It is possible to miniaturize the quantum wire 137. By doing so, even if the pattern size is large, it is possible to accurately and easily form a quantum thin line of 200 Å or less.

FIG. 66 is a perspective view showing a quantum wire transistor according to the eighteenth embodiment. Figure 65 (c) or Figure 65 above
On the doped layer 136 after the step shown in (d), ohmic electrodes 138, 138 are formed in the source and drain regions, and Schottky electrodes 139 are formed as gate electrodes at predetermined intervals in the direction crossing the quantum wires 137. Due to
A quantum wire transistor can be manufactured. Further, it can be applied to other semiconductor devices.

FIG. 67 is a partial perspective view for explaining the quantum box forming method according to the eighteenth embodiment. After processing the AlGaAs layer 133 into a sawtooth shape by the method shown in FIG.
A SiO _x film 140 is formed on the surface of the 1GaAs layer 133. Then, a striped or linear SiN film 141 is formed at a predetermined interval only at the position where the quantum box is formed, and heat treatment is performed. At this time, in the region where the SiN film 141 exists, Si
Are diffused to form a doped layer 136, but SiN
Si is not diffused in the region where the film 141 does not exist. Since the diffusion region (doping layer 136) of Si is limited in this way, the quantum box 142 has the doping layer 136 and A
GaAs located below the sawtooth recess of the 1GaAs layer 133
Only formed on layer 132. Also in this case, since the channel layer is nondestructively formed, defects such as crystal defects are hardly generated in the quantum box 142.

(Embodiment 19) This embodiment 19 uses AlGaAs.
An example of manufacturing an HEMT integrated circuit using the doping method of the present invention on a hetero substrate such as a / GaAs system will be described. By using the method of the nineteenth embodiment, it is possible to relatively easily manufacture the HEMT in the depletion mode and the enhancement mode without recess etching and the integrated circuit using them.

FIG. 68 is a schematic cross-sectional view showing the process of the method for manufacturing a semiconductor circuit element in Example 19, which is DCFL.
The case where a circuit element is manufactured is shown. First, as shown in Fig. 68 (a), a semi-insulating GaAs substrate is prepared by the molecular beam epitaxy method.
I-GaAs layer 152 (6000 Å), i-AlGaA on 151
s spacer layer 153 (20Å), n-AlGaAs layer 154 (200
Å, 3 × 10 ¹⁸ cm ^-3 ), i-AlGaAs layer 155 (200 Å)
Then, the i-GaAs layer 156 (500 Å) is sequentially formed, and elements are separated from other elements by mesa etching (not shown).

Next, an E mode FET element and a D mode FE
A refractory metal gate 157 made of, for example, WSiN and having a gate length of 0.35 μm is sputter-deposited on the region where the T element is formed.
It is formed by an etching method. Si is formed on both sides of the refractory metal gate 157 in the region where the E mode FET element is formed.
Sidewalls 158 and 158 made of O ₂ are formed by the CVD method (FIG. 68 (b)). And plasma CVD on this surface
By the method, a diffusion source 159 having a two-layer structure composed of a SiO _x film (x <2) / SiN film is formed and is removed except on the mesa etching. The conditions for forming the SiO _x film and the SiN film are as follows. SiO _x film: SiH ₄ 5sccm; N ₂ O 25sccm; power
150W; film forming temperature 300 ° C; film thickness 50Å SiN film: SiH ₄ 15sccm; NH ₃ 200sccm; power 2
50W; Film forming temperature 300 ℃; Film thickness 450Å

Further, after forming a SiO ₂ film 160 (1000 Å) on the upper surface as a subsequent heat treatment protection film,
Heat treatment is performed for a short time of 5 seconds. Then the diffusion source 159
Si of the SiO _x film in FIG.
-Diffusing into the AlGaAs layer 155, refractory metal gate 15
A diffusion layer 161 is formed on the portion except for the lower side of 7 (Fig. 68).
(c)). Here, the SiN film acts as an As diffusion preventing film in the heat treatment. Finally, an ohmic electrode 16 is formed to form an E mode FET element and a D mode FET element.
2 is formed (FIG. 68 (d)).

In the step of forming the diffusion layer 161 in FIG. 68 (c), Si is more i-AlG than i-GaAs layer 156.
Diffusion is easier in the aAs layer 155. Figure 69 is iG
It is a graph which shows the electron concentration distribution in the depth direction of an aAs layer (A) and an i-AlGaAs layer (B). This diffusion can be controlled by the film quality, film thickness, and heat treatment conditions of the SiO _x film and SiN film. When only the refractory metal gate 7 is formed on the i-GaAs layer 156 as in the present embodiment by utilizing such characteristics, the i-AlGaAs below the gate 7 is formed.
Although Si diffuses into the layer 155, a portion of the i-GaAs layer 156 where Si does not diffuse remains.

When the refractory metal gate 157 and the sidewalls 158 and 158 are formed to increase the coating width, S
The region where i does not diffuse is the i-GaAs layer 156, i-AlGa
Any As layer 155 remains, and its region is i-AlGa.
The As layer 155 is narrower. The former operates as a D-mode FET element in which a current flows even if the gate voltage is 0, and the latter operates as an E-mode FET element.

Table 6 shows the results obtained in Example 19 on a 2-inch substrate.
When an E-mode FET element and a D-mode FET element are manufactured by using, the threshold voltage and S before and after Si diffusion
i shows the standard deviation after diffusion.

[0224]

[Table 6]

As is clear from Table 6, the threshold voltage after Si diffusion sufficiently satisfies the condition for the DCFL circuit,
It is also excellent in uniformity. The reason for this is that since the recess etching technique for the gate portion is not used, variations due to etching and a damaged layer are not generated. Further, when the gate delay time and the power consumption were measured in the ring oscillator equipped with the DCFL circuit element according to the method of the present invention, the voltage between the source and drain was measured.
Good characteristics of 9 ps / gate and 1.0 mW / gate at 1.5 V were obtained.

The III-V group compound semiconductor is not limited to the semiconductor used in this embodiment. The layer for diffusing the impurities is not limited to the two-layer structure of the i-AlGaAs layer and the i-GaAs layer.

In addition, the SiN film in Example 19 was i-
As from the GaAs layer 156 and the i-AlGaAs layer 155
Is used to prevent the diffusion of Al, and a diffusion prevention layer for other V group atoms can be used as a substitute. In addition, although a case has been described with the nineteenth embodiment for manufacturing a DCFL circuit used for a modulation-doped FET, the application of the present embodiment is not limited to this.

(Embodiment 20) In Embodiment 20, different doping HEMTs or HEs are used by using the doping technique of the present invention.
It shows an example in which MT and MESFET are integrated.

(Example 1) FIG. 70 shows one type of HEMT and E
A process for producing a DCFL (direct coupling type FET logic circuit) using a D type (enhancement mode) and a D type (depletion mode) MESFET on the same substrate is shown.

First, as shown in FIG. 70 (a), semi-insulating GaA
undoped i-G on the s substrate 171 using the crystal growth method
A heterojunction layer composed of an aAs layer 172 and an i-AlGaAs layer 173 is formed by lamination. Next, E-type and D-type MESFE
All the i-AlGaAs layer 173 in the T formation region and i-Ga
A part of the As layer 172 in the thickness direction is removed by etching with a sulfuric acid-based etchant (FIG. 70 (b)). And H
Diffusion sources 174, 175, and 176 of SiO _x film / SiN film are deposited by plasma CVD under the conditions shown in Table 7 at the required positions of the EMT, E-type MESFET, and D-type MESFET forming regions (FIG. 70 (c)).

[0231]

[Table 7]

Thereafter, a short time heat treatment (850 ° C., 5 seconds) is performed, and the i-AlGaAs layer 173 in the HEMT formation region is n-doped.
-AlGaAs layer 177 is formed, E-type MESFET,
The n-GaAs layers 178 and 179 are respectively formed on the i-GaAs layer 172 in each formation region of the D-type MESFET (FIG. 70 (d)).
These doping layers (n-AlGaAs layer 177, n-Ga
As layers 178 and 179) have desired electron concentration distributions, as shown in FIG. Finally, the source electrode S, the drain electrode D, and the gate electrode G are appropriately formed on each doping layer.

The characteristics of each element obtained in Example 1 as described above are as follows. HEMT: NF = 0.50 dB (12 GHz) E-type MESFET: threshold voltage V _th = 0.1 V mutual conductance g _m = 500 mS / mm D-type MESFET: threshold voltage V _th = -1.0 V mutual conductance g _m = 500 mS / mm

This DCFL circuit realizes a high-speed operation with a delay time of 10 ps / gate. Therefore, according to this embodiment, the digital logic circuit using the E-type / D-type MESFET and the MESFET having low noise can be manufactured monolithically with a small number of manufacturing steps. Fig. 70
It is clear that the resistor can be manufactured by the manufacturing process similar to that shown in FIG.

(Example 2) Next, an HEM having different characteristics
FIG. 72 shows a process of manufacturing an MMIC including T. Here, a case will be described where a HEMT having a low noise characteristic in the X band and a HEMT having a high gain characteristic are formed on the same heterojunction layer. First, as shown in FIG. 72 (a), a heterojunction layer comprising a non-doped i-GaAs layer 182 and an i-AlGaAs layer 183 is laminated on a semi-insulating GaAs substrate 181 by the crystal growth method. Next, a portion of the i-AlGaAs layer 183 in the HEMT2 forming region in the thickness direction is removed by etching with a sulfuric acid etchant. Then, SiO _x was formed at a required position of each HEMT1 and HEMT2 forming region by plasma CVD under the conditions shown in Table 8.
The diffusion sources 184 and 185 of the film / SiN film are deposited (FIG. 72 (b)).

[0236]

[Table 8]

After that, a short-time heat treatment (850 ° C., 5 seconds) is performed, and i-Al in each formation region of HEMT1 and HEMT2 is formed.
The n-AlGaAs layers 186 and 187 are formed on the GaAs layer 183 (FIG. 72 (c)). These doping layers (n-AlGaA
As shown in FIG. 73, the s-layers 186 and 187) respectively have desired electron concentration distributions. Finally, the source electrode S, the drain electrode D, and the gate electrode G are appropriately formed on each doping layer. Table 9 shows the characteristics of each element obtained in Example 2 as described above.
Shown in.

[0238]

[Table 9]

As is clear from Table 9, according to Example 2, HEMT1 having a low noise characteristic and HEM having a high gain characteristic are provided.
T2 and T2 can be fabricated on the same heterojunction layer. Therefore, for example, the first stage HEM that requires low noise characteristics
H1 is installed in the 2nd and 3rd stages where T1 is installed and high gain is required.
By disposing T2, it becomes possible to fabricate an MMIC X band low noise receiving converter amplifier on the same heterojunction layer. Similarly, undoped AlGaAs /
HEMT MMICs having different characteristics can be manufactured even on InGaAs / GaAs pseudomorphic substrates.

It is also possible to fabricate two types of HEMTs and two types of MESFETs on the same substrate by combining the method shown in FIG. 70 (example 1) and the method shown in FIG. 72 (example 2). For example, in the etching process shown in FIG. 70 (b), regions having different thicknesses of the i-AlGaAs layer 173 are formed, and diffusion regions (SiOx) are formed in these regions under the conditions shown in Table 2.
Film / SiN film) is formed separately. And Fig. 70 (c), Fig. 70
By performing the process shown in (d), two types of HEMTs and two types of MESFETs can be manufactured on the same substrate.

Further, in the step shown in FIG. 70 (d), i-
A diode can be produced by appropriately forming a Schottky electrode and an ohmic electrode on the doping layer obtained by doping the GaAs layer 172, and a resistor is produced by forming an ohmic electrode on the doping layer. It is also possible.

(Embodiment 21) This embodiment 21 shows a method for manufacturing an electron wave interference element using the doping technique of the present invention.

FIG. 74 shows the basic structure of the electron wave interference element in the twenty-first embodiment. FIG. 74 (a) is its plan view and FIG. 74 (b).
FIG. 74 is a sectional view taken along the line AA ′ in FIG. 74 (a). 191 in the figure
Is semi-insulating GaAs191 from the surface to a depth of 0.2 μm.
b and below are GaAs substrates made of p-type GaAs 191a. A hole having a depth of about 0.3 μm is formed in the central portion of the GaAs substrate 191, leaving a part thereof.
On the side wall on the center side of the remaining portion, a channel layer 192 made of a high concentration layer formed by a diffusion technique is formed with a thickness of 0.1 μm or less (about 0.01 to 0.1 μm). On this occasion,
Since the thickness of the channel layer 192 is 0.1 μm or less, its electron concentration is about 3 × 10 ¹⁸ cm ⁻³ .

The channel layer 192 includes the channel layer 192.
An electron injection electrode 195 and an electron extraction electrode 196 are provided at two locations that divide the length of each of the electrodes 195,
Between 196, the electron wave can propagate in two paths (channel layers) 192a and 192b having a length of 0.2 μm or less. Further, a high concentration layer 193 for applying an electrostatic potential is formed on the side wall on the side of the margin of the remaining portion, and a gate electrode 194 is provided in connection with the high concentration layer 193.

Next, the operation will be described. When an electric field is applied between the electron injection electrode 195 and the electron extraction electrode 196, the electrons pass through the inside of each channel layer 192a, 192b. Here, since the channel layer 192 is made thin, the energy levels of electrons are quantized, and the phase thereof is less affected by scattering from impurities and is less likely to be disturbed. Then, from the gate electrode 194 provided in the vicinity of the channel layer 192 to the high concentration layer 19
By applying an appropriate potential via 3, electron waves propagating in both channel layers 192a, 192b cause interference,
The interference state can be controlled. By the above,
The structure of Example 21 also functions as an electron wave interference element.

Next, a method of manufacturing the electron wave interference element having such a structure will be described. 75 to 77 are cross-sectional views showing the process, which are taken along the line AA ′ in FIG. 74 and the line BB ′.
The cross-sections are illustrated in parallel in process order.

First, a photoresist film 201 is formed on the main surface of a GaAs substrate 191 made of semi-insulating GaAs 191b from the surface to a depth of 0.2 μm, and p-type GaAs 191a below that.
Is patterned into a desired shape (FIG. 75 (a)). Using this photoresist film 201 as a mask, G
A hole 202 having a depth of about 0.3 μm is formed in the aAs substrate 191 (FIG. 75 (b)). Then, by the ECR-CVD method, S
An iO ₂ film 203 is formed with a thickness of about 1000Å (FIG. 75 (c)).

Slight etching is performed using a mixed solution of NH ₄ F: HF = 120: 1 to selectively remove the SiO _x film 203 on the sidewalls of the GaAs substrate 191 and the photoresist film 201 (FIG. 76 (d)). . The SiO ₂ film 203 on the photoresist film 201 is removed by the lift-off method (FIG. 76 (e)). Next, by plasma CVD method, SiO _x / S for Si diffusion
The iN laminated film 204 is formed over the entire area (FIG. 76 (f)). SiO _x
The / SiN laminated film 204 has, for example, a lower layer of a SiO _x film (film thickness: about 150 Å) and an upper layer of a SiN film (film thickness: about 450 Å). Anisotropic etching is performed by the RIE method to remove the SiO _x / SiN laminated film 204 other than the side wall of the hole 202 (FIG. 76 (g)).

By the P-CVD method, a SiN film 205 as a protective film for annealing is formed over the entire area to a thickness of about 1000Å (FIG. 77 (h)). Then, an annealing treatment is performed at 880 ° C. for 5 seconds to form a high-concentration layer having a desired thickness to be the channel layer 192 and the high-concentration layer 193 (FIG. 77 (i)). At this time, the thickness of the high-concentration layer to be formed can be controlled according to the formation conditions of the SiO _x / SiN laminated film 204 and the annealing treatment conditions. After patterning the photoresist film 206 into a desired shape, the SiN film in the electrode formation region is selectively removed using the photoresist film 206 as a mask (FIG. 77 (j)). Next, Au
A metal film for the electrode made of Ge / Ni is deposited, and the metal film on the photoresist film 206 is removed by a lift-off method.
The gate electrode 194, the electron injection electrode 195, and the electron extraction electrode 196 are formed by performing heat treatment for 120 seconds in an H ₂ atmosphere at 450 ° C. (FIG. 77 (k)).

The fine pattern etching technique, electrode forming technique, etc., which are the main techniques used in the above manufacturing process, are widely used in the fabrication of general compound semiconductor devices, and the element structure of this Example 21 is It can be said that it is suitable for high-density integration.

[0251]

As is evident from the foregoing description, in the doping method of the present invention, heat treatment is performed to the wafer was deposited with SiO _x film and Group V atomic diffusion preventing film on the III-V compound semiconductor III
Since doping is performed by diffusing silicon in the group-V compound semiconductor, it is possible to extremely easily perform the doping process with good controllability on the group-III compound semiconductor. The doping method of the present invention can be widely applied when manufacturing semiconductor devices using III-V group compound semiconductors, and can greatly contribute to the development of semiconductor device manufacturing technology.

Further, in the resistance layer according to the ninth aspect, since the concave portion is provided in the resistance layer and the current flows through the side surface of the concave portion, the resistance layer occupying area of the semiconductor layer is not changed and the desired resistance value is obtained. A resistance layer can be formed, a saturation current value can be increased, and ohmic characteristics can be improved.

In the method of manufacturing an FET according to claim 10 , since a diffusion source having a two-layer structure composed of a SiOx film and a group V diffusion prevention film is formed and heat treatment is performed to diffuse Si,
It is possible to perform doping with good in-plane uniformity even in a portion where it has been difficult to dope conventionally, and a high-performance and high-quality FET can be obtained.

Further, in the FET manufacturing method according to the eleventh aspect , after the laminated film of the SiOx film and the As diffusion preventing film is formed on the III-V group compound semiconductor substrate which is selectively vertically etched, the heat treatment is performed. Since the operation layer is formed by performing the application, it is possible to easily form an operation layer having a uniform impurity concentration even on the side surface of the compound semiconductor substrate, and it is possible to achieve higher performance than the lateral configuration. To
Even if a compound semiconductor substrate of III-V group is used, it can be manufactured with good reproducibility.

According to the twelfth aspect of the method of manufacturing an FET, the SiOx film and the group V atom diffusion preventing film are laminated on the side of the step portion and below the step portion of the III-V group compound semiconductor substrate having the step portion. After applying the heat treatment,
Since the impurity diffusion layer is formed, it is possible to easily form the impurity diffusion layer on the side portion of the compound semiconductor substrate irrespective of the shape of the step portion and to improve the transistor characteristics, and to manufacture the FET with good reproducibility. You can

The method of manufacturing the FET according to claim 13 is
After forming the SiOx film and the group V atom diffusion preventing film and performing the heat treatment to form the doping layer, the heat treatment is further performed only on the region where the high concentration doping layer is formed, leaving the SiOx film and the group V atom diffusion preventing film. As a result, a doping layer having a higher impurity concentration can be selectively formed, and the manufacturing process can be simplified and the yield can be improved.

Further, in the method for manufacturing a semiconductor circuit element according to the fourteenth and fifteenth aspects, an expensive ion implantation apparatus is used by using the above-mentioned doping method and controlling the film thickness of the group V atom diffusion preventing film. Without doing so, a semiconductor integrated circuit element having several resistance values can be manufactured by a single heat treatment, and the cost is reduced.

Further, in the method of manufacturing an FET according to claim 16 , when the current value and the threshold voltage of the manufactured FET are lower than desired values, the Si existing in the doping layer is further diffused by heat treatment at a low temperature. Then, the current value and the threshold voltage can be increased and the desired values can be obtained, so that the yield is improved.

Further, in the method of manufacturing an electric conduction region according to the seventeenth aspect , a SiOx film and a group V atom diffusion prevention film are formed in this order on a III-V compound semiconductor, and a one-dimensional or two-dimensional electric conduction region is formed. After removing the group V atom diffusion preventive film other than the formation portion, heat treatment is simply performed to turn Si into a desired region of III-V.
It can be diffused into the group compound semiconductor. Moreover, according to this method, it is not necessary to perform a treatment such as etching on the III-V group compound semiconductor, so that no defect occurs and a good electric conduction region can be obtained.

In the method for forming a quantum wire according to the eighteenth aspect, a hole is formed in the III-V compound semiconductor substrate and Si is diffused therein to form a quantum wire without causing crystal defects. be able to. Further, the channel width for diffusing Si is determined by controlling the thickness of the diffusion layer formed on the III-V compound semiconductor substrate, so that it can be formed accurately and thinly. Further, the quantum wires can be formed along the side wall of the Si diffusion preventing layer for providing the step, and the shape is not restricted.

Further, in the method for forming a quantum wire according to claim 19 , since the difference in depth of diffusion portions formed in different kinds of III-V group compound semiconductors is used as the channel width of the quantum wire, crystal defects are caused. It is possible to form a thin quantum wire with an accurate channel width without causing it.

Further, in the method for forming a quantum wire according to claim 20 , since the cross-sectional shape of the wide band gap semiconductor layer is processed into a sawtooth shape and the doping layer is formed on the surface thereof, the doping layer which is a sawtooth-shaped recess is formed. Since the narrow forbidden band semiconductor layer / wide forbidden band semiconductor layer interface is close, electrons are accumulated in the narrow forbidden band semiconductor layer at this position, and a quantum wire which is an extremely narrow channel layer can be obtained and obtained. The quantum wire has almost no defects such as impurities or crystal defects.

In the method of forming a quantum box according to claim 21 , the group V atom diffusion preventing film is formed in a direction intersecting with the saw-toothed concavities and convexities, whereby the forming range of the doping layer is limited and the width is extremely narrow. It is possible to obtain a quantum box which is a channel layer having a limited length, and the obtained quantum box has almost no defects such as impurities or crystal defects.

The quantum wire transistor according to claim 22 has good characteristics because the quantum wire formed according to claim 20 is used.

Further, in the method for manufacturing a semiconductor circuit element according to the twenty- third aspect of the present invention, it is preferable that the SiOx film / group V atom diffusion prevention film 2
Since a diffusion source having a layered structure is formed on a semiconductor layer of a III-V group compound and heat-treated, Si can be diffused into the semiconductor layer at a predetermined depth and a predetermined concentration. Therefore, a selective etching technique is used. It is possible to manufacture a semiconductor circuit device such as a modulation-doped FET without a need.

[0266] In the manufacturing method of the semiconductor integrated circuit according to claim 24, 25, by using the above-described doping method, possible to easily realize the monolithic multiple elements having conventionally difficult even different properties Therefore, the communication device can be downsized, and the manufacturing process thereof is not complicated.

Furthermore, in the electron wave interference element of claim 26 ,
Since the high-concentration layer formed by the diffusion technique is used as the channel layer, it is possible to obtain an electron wave interference element having an arbitrary shape and size having a structure suitable for integration into an integrated circuit at an arbitrary position on the surface of the compound semiconductor substrate.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a laminated film structure of a SiO _x film / SiN film for explaining the principle of a doping method of the present invention.

FIG. 2 is a schematic view showing the mechanism of Si doping in the present invention.

FIG. 3 is a graph showing the relationship between the film quality of a SiO _x film and the occurrence of doping.

FIG. 4 is a graph showing Si concentration distribution and electron concentration distribution.

FIG. 5 is a graph showing an electron concentration distribution for explaining a correlation between a gas flow rate and an electron concentration distribution when forming a SiO _x film.

FIG. 6 is a graph showing an electron concentration distribution for explaining the correlation between the film thickness of a SiO _x film and the electron concentration distribution.

FIG. 7 is a graph showing an electron concentration distribution for explaining a correlation between a deposition temperature of a SiO _x film and an electron concentration distribution.

FIG. 8 is a graph showing the electron concentration distribution for explaining the correlation between the gas flow rate and the electron concentration distribution when forming the SiN film.

FIG. 9 is a graph showing an electron concentration distribution for explaining the correlation between the heat treatment temperature and the electron concentration distribution.

FIG. 10 is a cross-sectional view showing the structure of a wafer used in an example of the present invention.

FIG. 11 is a graph showing an electron concentration distribution when the present invention is applied to AlGaAs.

FIG. 12 is a perspective view of a semiconductor device in which a resistance layer of Example 1 of Example 8 is formed.

13 is a cross-sectional view taken along line XX of FIG.

FIG. 14 is a plan view showing an example of the shape of a recess of Example 1 of Example 8.

FIG. 15 is a graph showing a current-voltage relationship of a resistance layer of Example 1 of Example 8.

FIG. 16 is a perspective view of a semiconductor device in which a resistance layer of Example 2 of Example 8 is formed.

17 is a sectional view taken along line XX of FIG.

FIG. 18 is a perspective view of a semiconductor device in which a resistance layer of Example 3 of Example 8 is formed.

19 is a cross-sectional view taken along line XX of FIG.

20 is a graph showing the current-voltage relationship of the resistance layers of Example 2 and Example 3 of Example 8. FIG.

FIG. 21 is a cross-sectional view showing a step of the method for manufacturing the field effect transistor of Example 9.

FIG. 22 is a cross-sectional view showing a step of the method for manufacturing the field effect transistor of Example 9.

23 is a graph showing an electron concentration distribution of the diffusion layer shown in FIG.

FIG. 24 is a cross-sectional view showing a step of the method for manufacturing the field effect transistor of Example 10.

FIG. 25 is a cross-sectional structure diagram of the field effect transistor of Example 1 of Example 11.

FIG. 26 is a cross-sectional structure diagram of the field-effect transistor of Example 2 of Example 11.

27 is a cross-sectional structure diagram of the field effect transistor of Example 3 of Example 11. FIG.

28 is a cross-sectional view showing the manufacturing process of the field effect transistor shown in FIG. 27. FIG.

29 is a cross-sectional structure diagram of the field effect transistor of Example 4 of Example 11. FIG.

FIG. 30 is a cross-sectional view showing a step in the method for manufacturing the field-effect transistor of Example 1 of Example 12.

FIG. 31 is a cross-sectional view showing a step in the method for manufacturing the field-effect transistor of Example 2 of Example 12.

32 is a graph showing the electron concentration of the doping layer shown in FIGS. 30 and 31. FIG.

FIG. 33 is a graph showing the relationship between the film thickness of the SiN film and the sheet conductivity.

FIG. 34 is a cross-sectional view showing the method of forming the conductive layer in Example 13.

FIG. 35 is a cross-sectional view showing a step in the method of manufacturing the GaAs field effect transistor of Example 13.

FIG. 36 is a cross-sectional view showing a step in the method of manufacturing an E-type and D-type field effect transistor of Example 13.

FIG. 37 is a cross-sectional view showing a step in the method for manufacturing the modulation-doped field effect transistor of Example 13.

FIG. 38 is a cross-sectional view showing a step in a method for manufacturing an E-type and D-type modulation-doped field effect transistor of Example 13.

FIG. 39 is a sectional view showing a structure in the process of forming a Si doping layer in Example 14.

FIG. 40 is a graph showing the results of measuring the carrier concentration when the second heat treatment was performed in Example 14.

FIG. 41 is a cross-sectional view showing the structure of MESFET in the manufacturing stage of Example 14;

FIG. 42 is a cross-sectional view showing the structure of the modulation doped transistor in the middle of the manufacturing process of Example 14;

FIG. 43 is a cross-sectional view showing a step in the method for producing the electrically conductive region of Example 15.

FIG. 44 is a schematic diagram showing a one-dimensional electric conduction region obtained in Example 15.

45 is a cross-sectional view of the compound semiconductor substrate at the stage of forming quantum wires in Example 1 of Example 16. FIG.

FIG. 46 is a sectional view of the compound semiconductor substrate at the stage of forming quantum wires in Example 1 of Example 16.

47 is a cross-sectional view of the compound semiconductor substrate at the stage of forming quantum wires in Example 1 of Example 16. FIG.

48 is a sectional view of the compound semiconductor substrate at the stage of forming quantum wires in Example 1 of Example 16. FIG.

FIG. 49 is a cross-sectional view of the compound semiconductor substrate at the stage of forming quantum wires in Example 2 of Example 16.

50 is a sectional view of the compound semiconductor substrate at the stage of forming quantum wires in Example 2 of Example 16. FIG.

51 is a cross-sectional view of the compound semiconductor substrate at the stage of forming quantum wires in Example 2 of Example 16. FIG.

52 is a cross-sectional view of the compound semiconductor substrate at the stage of forming quantum wires in Example 2 of Example 16. FIG.

53 is a plan view of a compound semiconductor substrate having a quantum wire formed therein according to Example 3 of Example 16. FIG.

FIG. 54 is a cross-sectional view of the substrate at the stage of forming quantum wires in Example 1 of Example 17.

55 is a cross-sectional view of the substrate at the stage of forming quantum wires in Example 1 of Example 17. FIG.

FIG. 56 is a cross-sectional view of the substrate at a stage of forming quantum wires in Example 1 of Example 17.

FIG. 57 is a cross-sectional view of the substrate at the stage of forming quantum wires in Example 1 of Example 17.

FIG. 58 is a cross-sectional view of the substrate at the stage of forming quantum wires in Example 2 of Example 17.

FIG. 59 is a cross-sectional view of the substrate at a stage of forming quantum wires in Example 2 of Example 17.

FIG. 60 is a cross-sectional view of the substrate at a stage of forming quantum wires in Example 2 of Example 17.

61 is a cross-sectional view of the substrate at the stage of forming the quantum wires in Example 2 of Example 17. FIG.

FIG. 62 is a cross-sectional view of the substrate at a stage of forming quantum wires in Example 3 of Example 17.

63 is a cross-sectional view of the substrate at a stage of forming quantum wires in Example 3 of Example 17. FIG.

64 is a cross-sectional view showing a quantum wire (or a quantum box) obtained in Example 18. FIG.

FIG. 65 is a cross-sectional view showing a step in the method for forming a quantum wire according to Example 18.

FIG. 66 is a perspective view showing a quantum wire transistor according to an eighteenth embodiment.

FIG. 67 is a partial perspective view for explaining the quantum box forming method in Example 18.

FIG. 68 is a cross-sectional view showing a step of the method for manufacturing the semiconductor circuit element of Example 19.

FIG. 69 is a graph showing an electron concentration distribution of a diffusion layer in Example 19.

FIG. 70 is a cross-sectional view showing the step of the method for manufacturing the semiconductor integrated circuit of Example 1 of Example 20.

71 is a graph showing an electron concentration distribution of a doping layer obtained by the manufacturing method shown in FIG. 70.

72 is a sectional view showing a step in the method for manufacturing the semiconductor integrated circuit of Example 2 of Example 20. FIG.

73 is a graph showing an electron concentration distribution of a doping layer obtained by the manufacturing method shown in FIG.

74A and 74B are a plan view and a cross-sectional view showing the basic structure of the electron wave interference element according to the twenty-first embodiment.

FIG. 75 is a cross-sectional view showing a step in the method of manufacturing the electron wave interference element of Example 21.

FIG. 76 is a cross-sectional view showing a step in the method of manufacturing the electron wave interference element of Example 21.

77 is a cross-sectional view showing a step in the method of manufacturing the electron wave interference element of Example 21. FIG.

[Explanation of symbols]

1 GaAs Substrate 2 SiO _x Film 3 SiN Film 11 Semiconductor Substrate 12 SiOx / SiN Laminated Film 13 Resistive Layers 13a, 13b, 13c Recess 14 Electrode 21 GaAs Substrate 22 Low Concentration Doping Layer 23 T-type Gate Electrode 24 Diffusion Source 25 SiO ₂ Film 26 Highly-doped layer 27 Medium-doped layer 28 Ohmic electrode 31 GaAs substrate 32 SiO _x film 33 SiN film 34 Operating layer 35 Source electrode 36 Drain electrode 37 Si ₃ N ₄ film 38 Gate electrode 41 Source electrode 42 Gate electrode 43 Drain electrode 44 n ⁺ layer 45 operating layer (n layer) 46 n ⁻ layer 47 SiO _x film 48 SiN film 50, 51 GaAs substrate 52 diffusion source 53 n layer 54 gate electrode 55 n ⁺ layer 56 ohmic electrode 57 GaAs layer 58 AlGaAs layer 61 GaAs substrate 62 SiO _x film 63, 67 SiN film 64 Diffusion source 71, 72, 73 Conductive layer 74 AlGaAs layer 77 Conductive layer 78 Diffused doping layer 79 Two-dimensional electron gas layer 80, 81 Diffusion doped layer 82 Conductive layer 83, 84 2 Dimension electric Gas layer 91 GaAs substrate 91a, 91b doped layer 92 SiO _x film 93 SiN film 97 GaAs layer 98 AlGaAs layer 98a, 98b doped layer 101 Heterojunction substrate 101a i-GaAs layer 101b i-AlGaAs layer 102 diffusion source 102a SiO _x film 102b SiN film 103 n-AlGaAs layer 104 Two-dimensional electric conduction region 105 One-dimensional electric conduction region 115 AlGaAs layer 116 SiN layer 117 SiO _x film 118 SiN film 119 Diffusion part 121 GaAs layer 122 AlGaAs layer 123 SiO _x film 124 SiN film 130 Quantum Fine wire 131 GaAs substrate 132 GaAs layer 133 AlGaAs layer 135 Diffusion source 136 Doping layer 137 Quantum wire 138 Ohmic electrode 139 Schottky electrode 140 SiO _x film 141 SiN film 142 Quantum box 151 GaAs substrate 152 i-GaAs layer 153 Spacer layer 154 n-AlGaAs Layer 155 i-AlGaAs layer 156 i-GaAs layer 157 Refractory metal gate 158 Sidewall 159 Diffusion 171 GaAs substrate 172 i-GaAs layer 173 i-AlGaAs layer 174, 175, 176 Diffusion source 181 GaAs substrate 182 i-GaAs layer 183 i-AlGaAs layer 184, 185 Diffusion source 191 GaAs substrate 192 p-type GaAs 193 For potential application High concentration layer 194 Gate electrode 195 Electron injection electrode 196 Electron extraction electrode

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 29/06 601 H01L 29/80 E 27/04 P 29/778 29/812 (31) Priority claim number Japanese Patent Application No. 4- 183260 (32) Priority date June 16, 1992 (June 16, 1992) (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 4-186196 (32) Priority date Heisei June 18, 1992 (June 18, 1992) (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 4-186375 (32) Priority date June 19, 1992 ( June 19, 1992 (33) Country of priority claim Japan (JP) (31) Claim number for priority right Japanese Patent Application No. 4-186376 (32) Priority date June 19, 1992 (June 19, 1992) 33) Priority claiming country Japan (JP) (31) Priority claiming number Japanese Patent Application No. 4-312744 (32) Priority date October 27, 1992 (1992.10.27) (33) Priority claiming country Japan (J (31) Priority claim number Japanese Patent Application No. 4-316248 (32) Priority date October 30, 1992 (October 30, 1992) (33) Country of priority claim Japan (JP) (31) Priority claim No. Japanese Patent Application No. 4-310559 (32) Priority date November 19, 1992 (November 19, 1992) (33) Country of priority claim Japan (JP) (31) No. Japanese Patent Application No. 4-345473 (32) Priority date November 30, 1992 (November 30, 1992) (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 5-3612 (32) Priority date 1993 January 12, 1993 (January 12, 1993) (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 5-5307 (32) Priority date January 14, 1993 (1993) 1.14) (33) Priority claim country Japan (JP) (31) Priority claim number Japanese Patent Application No. 5-6950 (32) Priority date January 19, 1993 (January 19, 1993) (33) ) Priority claiming country Japan (JP) (31) Priority claiming number Japanese Patent Application No. 5-54053 (32) Priority date March 15, 1993 (1993.15) (33) Priority claiming country Japan ( JP) (72) Inventor Eimi I, 2-18, Keihanhondori, Moriguchi-shi, Osaka Sanyo Denki Co., Ltd. (72) Inventor Taiei Tono 2--18, Keihanhondori, Moriguchi, Osaka Pref. Sanyo Electric Co., Ltd. (72) Inventor Yamada 2-18 Keihan Hondori, Moriguchi City, Osaka Prefecture Sanyo Electric Co., Ltd. (72) Inventor Akihito Nagamatsu 2-18 Keihan Hondori, Moriguchi City Osaka Prefecture Sanyo Electric Co., Ltd. (72) Inventor Nao Kurose Osaka 2-18 Keihanhondori, Moriguchi-shi Sanyo Electric Co., Ltd. (72) Inventor Daijiro Inoue 2-18-2 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Koji Matsumura Osaka Moriguchi 2-18, Keihan Hondori, Sanyo Electric Co., Ltd. (56) Reference JP-A-49-32580 (JP, A) JP-A-6-204151 (JP, A) JP-A-6-236895 (JP, A) Electronic materials, Japan, January 1, 1993, Vol. 32, No. 1, p. 38-44 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/338 H01L 21/22 H01L 27/095 H01L 29/06 H01L 29/778 H01L 29/812 (54) [Invention title] Doping method, semiconductor device, resistance layer, field effect transistor manufacturing method, semiconductor circuit element manufacturing method, electric conduction region manufacturing method, quantum wire forming method, quantum box forming method, quantum wire transistor, semiconductor Integrated circuit manufacturing method and electron wave interference element

Claims (26)

(57) [Claims] 1. A method for doping an impurity in a III-V group compound semiconductor, wherein a crystal of the III-V group compound semiconductor comprises a non-doped silicon oxide film (SiOx film) and a crystal of the III-V group compound semiconductor. a step of sequentially laminating a film for preventing the external diffusion of group V atoms to which
By applying at least one or more heat treatment al,
And a step of diffusing silicon (Si) in the SiOx in film in the group III-V compound semiconductor, the SiOx
A doping method, wherein x of the film is x <2 . 2. The III-V group compound semiconductor is GaA.
s series, InP series, AlAs series, AlGaAs series, InG
2. At least one selected from the group consisting of aAs series and InAlAs series.
The doping method described. 3. The doping according to claim 1, wherein the film for preventing outdiffusion of group V atoms is selected from the group consisting of SiN film, AlN film, WSi film and WSiN film. Method. 4. After stacking the two films, the two films
2. The doping method according to claim 1, further comprising the step of leaving one of the two films only in a predetermined region, or leaving the SiOx film and a film for preventing out-diffusion of group V atoms in the predetermined region. 5. When laminating the two films, the film thickness and / or film characteristics of at least one film are changed to change the Si diffusion profile after the heat treatment. 1. The doping method according to 1. 6. A semiconductor device having a doping layer formed by using the doping method according to claim 1. 7. The semiconductor device according to claim 6 , wherein the semiconductor device is an integrated circuit having at least one or more field effect transistors, diodes, and resistance layers. 8. The semiconductor device is selected from the group consisting of a quantum effect element having a two-dimensional or one-dimensional electron gas layer, a zero-dimensional quantum box, and an element using electron wave interference. 7. The semiconductor device according to claim 6 , wherein: 9. A resistance layer formed by diffusing impurities on a surface of a semiconductor layer between electrodes, wherein the semiconductor layer is provided with a recess, and a side surface and a bottom surface of the recess are formed by using the doping method according to claim 1. Is diffused, and the recess has a side surface area such that a distance of a current flowing between the electrodes and a cross-sectional area of a portion where the current flows are predetermined values. 10. A low-concentration doping layer immediately below a gate electrode and a source / source layer formed on a substrate surface made of a III-V group compound.
In a method of manufacturing a field effect transistor having a high-concentration doping layer in a drain region and a medium-concentration doping layer between the low- and high-concentration doping layers, a step of forming a low-concentration doping layer on the substrate surface, Forming a gate electrode in the center of the upper surface of the concentration doping layer,
Forming a SiOx film and a Group V atom diffusion preventing film doped to an upper surface of the lightly doped layer, said forming a highly doped layer on both end portions of the lightly doped layer, the SiOx film by heat treatment Si of the above
Is diffused into the substrate, possess a step of forming a medium-concentration doped layer in the lightly doped layer except the lower side of the gate electrode, and forming an ohmic electrode on the upper surface of the high-concentration doped layer, wherein X of the SiOx film is x <2
A method for manufacturing a field effect transistor , characterized by being present. 11. A method of manufacturing a field effect transistor using a III-V group compound semiconductor substrate, the step of selectively etching the compound semiconductor substrate substantially vertically, and the selectively etched compound semiconductor. A step of forming a laminated film of a non-doped SiOx film and a group V atom diffusion preventing film on the side surface and the upper surface of the substrate, and heat-treating the compound semiconductor substrate having the laminated film formed thereon to form the SiOx film.
Forming an operating layer by diffusing a compound semiconductor substrate of Si inner, source electrode on a compound semiconductor substrate of the upper surface of the operation layer, and forming a drain electrode, on the active layer side of the compound semiconductor substrate It has a step of forming a gate electrode, a field effect type method for producing a transistor, wherein x of the SiOx film is x <2. 12. A III-V group compound semiconductor substrate has an operation layer and an impurity diffusion layer, a gate electrode is provided on the operation layer, and a source electrode and a drain electrode are provided on the impurity diffusion layer. In the method for manufacturing a field effect transistor, a step of forming a step portion by etching a III-V group compound semiconductor substrate, a step of forming the operation layer above the step portion, and before subjected forming a laminated film of the step portion side and the stepped portion lower non-doped SiOx film and a group V atom diffusion preventing film, the heat treatment compound semiconductor substrate laminated film is formed
The Si in the serial SiOx film to diffuse into the compound semiconductor substrate possess and forming the impurity diffusion layer, the SiO
A method of manufacturing a field effect transistor, wherein x of the x film is x <2 . 13. A method for manufacturing a field effect transistor comprising a plurality of doping layers having different impurity concentrations on a III-V compound semiconductor substrate, wherein a non-doped SiOx film and a non-doped SiOx film are formed on the III-V compound semiconductor substrate. A step of stacking a group V atom diffusion preventing film in this order and a heat treatment are performed to form the SiO in the III-V compound semiconductor substrate.
a step of diffusing Si in the x film to form a doping layer, a step of removing the SiOx film and the group V atom diffusion preventing film in a required region, and a heat treatment to obtain the S
a region iOx film and the Group V atom diffusion preventing film exists, have a forming a high doping layer impurity concentration than the doping layer, x of the SiOx film x
<2 . A method for manufacturing a field effect transistor, wherein <2 . 14. A method for manufacturing a semiconductor circuit device having a conductive layer having different resistance values by doping a III-V group compound semiconductor with impurities, wherein a non-doped SiOx film and a V group group are formed on the III-V group compound semiconductor. A step of forming an atomic diffusion preventive film in this order, a step of reducing the thickness of the group V atomic diffusion preventive film in a portion where a conductive layer having a high resistance value is formed, and a heat treatment of the III-V group compound semiconductor. hand
It possesses a step of diffusing Si of the SiOx in film III-V compound semiconductor, x of the SiOx film x <2
A method for manufacturing a semiconductor circuit element, comprising: 15. A method for manufacturing a semiconductor circuit device having a conductive layer having different resistance values by doping a III-V group compound semiconductor with impurities, wherein the non-doped narrow bandgap semiconductor layer is a III-V group compound semiconductor. A wide forbidden band semiconductor layer to form a heterojunction layer, a step of forming a non-doped SiOx film and a group V atom diffusion prevention film in this order on the heterojunction layer, and a conductive material having a high resistance value. A step of reducing the thickness of the group V atom diffusion preventing film in the portion where the layer is formed, and heat treatment of the group III-V compound semiconductor to form S in the SiOx film in the group III-V compound semiconductor.
The i possess a step of diffusing, x of the SiOx film x
<2 . A method for manufacturing a semiconductor circuit element, characterized in that 16. A method for manufacturing a field effect transistor comprising a doping layer formed in a III-V compound semiconductor layer as a channel layer or an electron supply layer, comprising a non-doped SiO 2 layer on the III-V compound semiconductor layer.
a step of forming an x film and a group V atom diffusion preventing film in this order, and heat treatment to form a film in the III-V group compound semiconductor layer.
A step of diffusing Si in the SiOx film to form the doping layer, and further subjecting the doping layer to a heat treatment to further diffuse Si in the doping layer into the III-V compound semiconductor layer; <br /> method for producing a field effect transistor, characterized in that the possess a step of thick, x of the SiOx film is x <2. 17. A method for injecting an impurity into a III-V compound semiconductor to form a one-dimensional or two-dimensional electric conduction region, wherein a non-doped SiOx film and a V-group diffusion preventive are provided in the III-V compound semiconductor. A step of forming a film in this order, a step of removing the group V diffusion prevention film other than a portion where the electric conduction region is to be formed, and a heat treatment
It possesses a step of diffusing Si of the SiOx in film III-V compound semiconductor, x of the SiOx film x <2
The method for manufacturing a conductive region, characterized in that it. 18. A method of forming a quantum wire, comprising:
A step of forming a Si diffusion preventing layer on a II-V compound semiconductor substrate to form a step, and a step of forming a non-doped SiOx film and a group V atom diffusion preventing film in this order on the Si diffusion preventing layer, Steps of removing the portions of the SiOx film and the group V atom diffusion preventing film other than those formed on the sidewalls of the step, and heating the substrate that has undergone these steps to remove the Si
From Ox film to the Group III-V compound semiconductor substrate, allowed diffusion of Si through their contact surfaces, have a forming a quantum wire, x of the SiOx film x <2 Dearuko
And a method for forming a quantum wire characterized by: 19. In the method for forming a quantum wire, a non-doped SiOx film and a V-group atom diffusion prevention film are formed on the surface of a substrate on which a plurality of different III-V group compound semiconductors both appear on the same surface. And a heat treatment to diffuse Si from the SiOx film,
A step of forming a diffusion portion having a difference in the depth direction in each of the III-V group compound semiconductors, and removing a portion on the front surface side of the substrate so that the deeper diffusion portion remains so that the diffusion portion near the remaining diffusion portion is formed. 1-dimensional electron gas possess a step of the quantum wire to, x of the SiOx film forming method of a quantum wire according to Patent <br /> symptoms that the x <2 is formed. 20. A method of forming a quantum wire in which a carrier moving direction in a channel layer is one-dimensional,
A cross-sectional shape is formed by a step of stacking a narrow bandgap semiconductor layer and a wide bandgap semiconductor layer made of a III-V group compound semiconductor in this order on a substrate and etching by utilizing the plane orientation dependence of the wide bandgap semiconductor layer. A step of processing into a sawtooth shape, a step of forming a non-doped SiOx film and a group V atom diffusion preventing film in this order on the sawtooth-shaped wide bandgap semiconductor layer, and heat treatment to perform the wideband band semiconductor. In front of layer surface
The step of diffusing Si in the SiOx film to form a doping layer and the step of forming a channel layer only in the narrow band gap semiconductor layer located below the sawtooth-shaped recess of the doping layer to form a quantum wire. Yes and, x of the SiOx film in the x <2
A method for forming a quantum wire , characterized by being present. 21. A method of forming a quantum box in which carriers in a channel layer are confined in a three-dimensional direction, wherein a narrow bandgap semiconductor layer and a wide bandgap semiconductor layer made of a III-V group compound semiconductor are provided on a substrate in this order. A step of laminating, a step of processing into a sawtooth shape by etching utilizing the plane orientation dependency of the wide forbidden band semiconductor layer, and a step of forming a non-doped SiOx film on the wide bandgap semiconductor layer processed into the sawtooth shape A step of forming a group V atom diffusion preventing film at a position where a quantum box is formed, and a heat treatment to diffuse Si in the SiOx film to a required region on the surface of the wide bandgap semiconductor layer and a doping layer. forming a said serrated are under the recess and only by forming a channel layer on the narrow bandgap semiconductor layer position is below the doped layer have a a step of a quantum box, the x of iOx film x <2 Dearuko
And a method for forming a quantum box characterized by: 22. In a quantum wire transistor including a quantum wire as a channel layer under an electrode, a narrow bandgap semiconductor layer formed on a substrate, and a cross-sectional shape formed in a sawtooth shape formed on the narrow bandgap semiconductor layer. A wide bandgap semiconductor layer formed, and a doping layer formed on the surface of the wide bandgap semiconductor layer having a sawtooth shape by the doping method according to claim 1, and formed only under the sawtooth recessed portion of the doping layer. A quantum wire transistor, comprising: a quantum wire; and an electrode formed on the wide bandgap semiconductor layer in a direction intersecting the saw-toothed concavities and convexities. 23. A method of manufacturing a semiconductor circuit device, comprising: a diffusion layer having portions having different impurity concentrations on a substrate; and electrodes provided on the diffusion layer.
Forming a semiconductor layer made of a group compound, forming a plurality of shields having different coating widths on the semiconductor layer with a predetermined distance, and the surface of the shield and the semiconductor layer having no shield. possess a step of a SiOx film and a group V atom diffusion preventing film formed in this order on the surface undoped of, and forming a diffusion layer by diffusing Si in the SiOx film into the semiconductor layer by heat treatment , X of the SiOx film is x
<2 . A method for manufacturing a semiconductor circuit element, characterized in that 24. A method of manufacturing a semiconductor integrated circuit by doping a group III-V compound semiconductor with impurities to form a plurality of devices, wherein a non-doped narrow bandgap semiconductor which is a group III-V compound semiconductor is formed on a substrate. A layer and a wide bandgap semiconductor layer in this order to form a heterojunction layer; a step of removing the wide bandgap semiconductor layer in a required region to expose the narrow bandgap semiconductor layer; Forming a non-doped SiOx film and a group V atom diffusion preventing film on the layer and the wide band gap semiconductor layer in this order, and performing a heat treatment to diffuse Si in the SiOx film into the III-V compound semiconductor. forming a doping layer, and forming an electrode on the doped layer possess, the SiO
A method of manufacturing a semiconductor integrated circuit, wherein x of the x film is x <2 . 25. A method for manufacturing a semiconductor integrated circuit by doping a III-V group compound semiconductor with impurities to form a plurality of elements, wherein a non-doped narrow bandgap semiconductor which is a III-V group compound semiconductor is formed on a substrate. Layer and a wide bandgap semiconductor layer in this order to form a heterojunction layer, a step of partially removing the wide bandgap semiconductor layer in a required region in the thickness direction, and a wide bandgap having a different thickness. forming the SiOx film and the group V atom diffusion preventing film on a semiconductor layer, prior to the III-V compound semiconductor by heat treatment
Forming a serial doping layer is diffused Si in SiOx film, possess and forming an electrode on the doping layer, x of the SiOx film is a semiconductor integrated which is a x <2 Circuit manufacturing method. 26. In an electron wave interference device having a plurality of electron wave paths in the vicinity of the surface of a compound semiconductor, the path is a high concentration layer formed by using the doping method according to claim 1. Electron wave interference element.