JPH02219271A - Compound semiconductor field effect transistor and its manufacture - Google Patents

Abstract

PURPOSE:To reduce the gate leak current and threshold voltage and stabilize the element operations of the title transistor by setting orientations of the first semiconductor layer and first insulating layer to plane (111) or another plane close to (111). CONSTITUTION:This compound semiconductor field effect transistor is provided with the first semiconductor layer 22 which is formed on a monocrystalline substrate 21 and has a spherical type crystal structure, first insulating layer 22 which is formed on the layer 22 and has a fluorite type crystal structure, a gate electrode provided on the layer 23, a source and drain areas 25a and 25b provided in the layer 22, and a source electrode 26a and drain electrode 26b respectively provided adjacent to areas 25a and 25b. In addition, orientations of the layers 22 and 23 are set to plane (111) or another plane close to (111). Therefore, the homogeneity of the monocrystalline insulating layer is improved, resulting in reduction of gate leak current, and, at the same time, the threshold voltage is lowered due to a reduction in interface level density. In addition, the characteristics of the transistor are stabilized, because occurrence of stress is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an ultra-high speed/ultra-high frequency compound semiconductor field effect transistor using a ■-■ group compound semiconductor, particularly GaAs, and a method for manufacturing the same.

(Prior Art) Conventionally, attempts have been made to fabricate a field effect transistor using a MIS structure made of a compound semiconductor, particularly GaAs, and an amorphous insulating layer, such as a silicon oxide film or an aluminum oxide film. However, defects and natural oxide film exist at the interface between GaAs and the amorphous insulating layer.

It is difficult to remove disorders, etc., and the density of interface states caused by these is high.
GaAs field effect transistor (GaAs MISFET) using MIS structure composed of aAs interface
However, it was difficult to form a good inversion layer to serve as a channel, making it difficult to realize transistor operation (for example, Hideki Hase, Applied Physics, Vol. 50, No. 12 "■
- MIS interface of group semiconductors and its applications.

In order to overcome this problem, as shown in FIG. 2, a single crystal insulating layer having a fluorite structure, such as single crystal calcium fluoride CaF
Attempts have been made to fabricate a GaAs MISFET using a heterostructure formed by molecular beam epitaxial method (MBE) (T, Waho and F, Yanag).
awa, IEEl[t EDL-9, No, 10 (
198B) p, 54B"^ GaAs MISFE
Using an MBE-grown
CaF, gate insulator 1 ayer
”).

Such a GaAsM I S F E T structure has an undoped (100) G layer on a semi-insulating GaAs substrate 11.
Using a heterostructure in which an aAs semiconductor layer 12 and a single crystal fluoride film CaFz 16 are successively formed, ions to be impurities are implanted using the gate electrode 17 as a mask, followed by high-temperature annealing to activate the impurities. After forming the source region 13a and the drain region 13b in a self-aligned manner, the source electrode 14a and the drain electrode 1 are further formed.
4b. This GaAsM
The ISFET operates in the same way as a normal FET by applying a predetermined positive voltage to the gate electrode 17 and forming a channel 15 in the semiconductor layer 12 under the gate electrode.

(Problem to be solved by the invention) However, conventional GaAs using CaF2 grown on such a (100) GaAs semiconductor layer as a gate insulating film
The gMISFET structure had the following problems.

(a) The gate leakage current I9 is large, and the performance of the transistor (transconductance glI power consumption) is reduced.

(b) It is difficult to significantly reduce the interface state density, the dark value voltage is high, and manufacturing variations are large.

(c) The transistor characteristics are unstable.

In addition, in manufacturing GaAsMISFET, in the heat treatment process for activating the impurities ion-implanted to form the source and drain regions, for the purpose of preventing the evaporation of group (I) elements with high vapor pressure, The above-mentioned method using an amorphous insulating film or the so-called face-to-face method of covering with the same type of compound semiconductor substrate have been adopted. There is a problem in that impurities are unavoidably mixed into the surface of the compound semiconductor during the heat treatment process, and this has a serious adverse effect on the electrical characteristics of the compound semiconductor/insulator interface and, ultimately, on the MISFET characteristics.

The present invention was proposed in order to improve the above-mentioned drawbacks, and its purpose is to reduce gate leakage current, lower dark voltage, and stabilize element operation in high-performance compound semiconductor field effect transistors. The goal is to realize this and provide a manufacturing method for it.

(Means for Solving the Problems) In order to achieve the above object, the present invention includes a single crystal substrate, a first semiconductor layer having a zinc blende crystal structure formed on the single crystal substrate, and a first semiconductor layer having a zinc blende crystal structure formed on the single crystal substrate. a first insulating layer having a fluorite crystal structure formed on a first semiconductor layer; a gate electrode provided on the first insulating layer; and a gate electrode provided in the first semiconductor layer. A source region, a drain region, and a source electrode and a drain electrode provided in connection with the source region and the drain region, respectively, wherein the first semiconductor layer and the first insulating layer are in or near the (111) plane. The gist of the invention is a compound semiconductor field effect transistor characterized by having a plane orientation that is

Furthermore, the present invention includes a step of forming a first semiconductor layer having a zincblende crystal structure on a semi-insulating substrate with a (111)B orientation plane by molecular beam epitaxial method, followed by a step of forming a first semiconductor layer having a zinc blende crystal structure in the same vacuum. a step of forming a single crystal insulating layer acting as a gate insulating film on the first semiconductor layer by molecular beam epitaxial method; and annealing to activate ion-implanted impurities using the insulating layer as a protective film. The gist of the invention is a method for manufacturing a compound semiconductor field effect transistor characterized by comprising the steps of:

(Operation) The most important feature of the present invention is the (111) fluorite type single crystal.
Layered growth on the (111) plane of a zinc blende compound semiconductor, which has the lowest surface energy compared to other plane orientations and has a similar crystal structure to be deposited on the fluorite single crystal. Taking advantage of this fact, the compound semiconductor field effect transistor structure utilizes a steep compound semiconductor layer/single crystal insulating layer heterostructure formed in a layered mode throughout the entire process. Therefore, the uniformity of the single crystal insulating layer is dramatically improved, high resistivity can be achieved, and gate leakage current can be reduced.

Because it has the above features, and at the same time, as a second feature, it uses a mixed crystal insulating layer of multiple insulators with a fluorite crystal structure to achieve lattice matching with the semiconductor layer, which is a cause of interface states. By suppressing the generation of non-bonding pairs (dangling bonds) at the interface and reducing the interface state density, it is possible to reduce the threshold value. It has the effect of improving

Because of the above effects, it is possible to realize a field effect transistor with unprecedented high speed and low power consumption.

(Example) Next, an example of the present invention will be described. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements may be made without departing from the spirit of the present invention.

FIG. 1 is a diagram explaining the present invention in detail.

Regarding the method for realizing this structure, first the interface formation method and then the FET structure formation method will be explained in that order.

First, semi-insulating (111
) An undoped GaAs layer 22, which is a first semiconductor layer, is homoepitaxially grown on a BGaAs crystal substrate 21 by a molecular beam epitaxial method, and then calcium strontium fluoride C is grown by a molecular beam epitaxial method.
By growing a, lSr+-xFz, a single crystal insulating layer 23 (which acts as a gate insulating film) is formed.

The semiconductor layer 22 is formed under commonly used growth conditions, such as a substrate temperature of 650° C. and a growth rate of approximately 0.6.
n/h and a film thickness of 0.7n.

At this time, the conductivity type of the GaAs layer 22 is P, and the carrier concentration is 10'' to 10''cm-''.
The growth conditions for the r+-xFz film 23 include, for example, a substrate temperature of 500°C, a growth rate of 0.0671 m/h, and a film thickness of 60 m/h.
nm is used. Under these or similar conditions, both the semiconductor layer and the single crystal insulating layer are aligned with the substrate orientation (111
) and grown with (111) plane orientation/
An insulator interface can be formed.

Preferably, the lattice constant of the first single-crystal insulating layer having a fluorite structure is lattice-matched to the lattice constant of the first zinc blende semiconductor layer within a range of ±0.5%.

Further, the first zincblende semiconductor layer is made of GaAs, the first fluorite structure single crystal insulating layer is calcium strontium fluoride, and the ratio of calcium to strontium is , 1; preferably in the range of (0.9 to 1.3).

High purity calcium fluoride CaFz and high purity strontium fluoride SrF2 are used as molecular beam sources for the molecular beam epitaxial method. By controlling the cell temperature of each molecular beam source, the composition ratio χ of Ca and Sr can be set to an arbitrary value with an accuracy within ±3%. Approximately 0.44. 600'C
By setting the value to about 0.56, lattice matching between CaX5r1-xF2 and GaAs can be achieved.

The well-known ordinary GaAsME is used for FET fabrication.
Refractory metal gate self-line process used in SFET fabrication (e.g. 19811SSCCTec
hnical Digest “A self-ali”
gned 5source/drain planar
device for ultra-high-speed
ed GaAsMESFET'VLSI's")
Adopt a process similar to.

First, a high melting point metal film WSt is formed on the entire surface by sputtering, and a gate electrode 24 is formed by using a normal reactive ion etching (RIB) method. Next, St ions are added as n-type impurities to the gate electrode 2 under the conditions of an energy of 50 KeV and a dose of 4 XIO cm-.
For example, by ion-implanting 4 and then performing high-temperature annealing for activation using the single-crystal insulating layer 23 as a protective film.
The source region 25a and the drain region 25b are formed in a self-aligned manner under the conditions of 50° C. and 6 to 800° C. for 4 to 10 seconds.

In this annealing process, the single crystal insulating layer 23 is made of GaA
It is used as a surface protective film for the s-layer 22.

Furthermore, the single-crystal fluoride mixed crystal layer was etched with an HCI-based etching solution using the resist as a mask to open contact windows with the source and drain regions, and then the Au
By forming an ohmic source electrode 26a and a drain electrode 26b made of GeNi and wiring made of Ti/Au, an N-channel GaAsM I 5FET structure can be realized. Because of this structure, when a predetermined positive voltage, for example, a value of 0.9 V or more is applied to the gate electrode, N is generated in the first semiconductor layer 22 near the insulating layer 23 under the gate electrode 24. A shaped channel 27 is formed to provide normal FET operation.

Similarly, P-channel GaAsM I 5
When manufacturing a FET, Be ions, which will become a p-type impurity, are implanted at an energy of 30 KeV instead of an n-type impurity in the impurity ion implantation process for manufacturing the MISFET.

This can be achieved by ion implantation at a dose of 2 x 1013 cm-'' and by using ^Zn for the ohmic electrode.

In addition, the above-mentioned N-channel and P-channel MIS
By forming the FETs on the same heterogeneous substrate, separating the elements of each MISFET by H ion implantation, etc., and interconnecting them with Ti/Au wiring electrodes, these GaAsM ISFETs It is possible to realize a complementary circuit using At this time, N-channel GaAsM
When forming an I S F E T, the homoepitaxially grown GaAs layer in which the channel will be formed contains 10
A p-type impurity of 15 to 7×10'6/Cm3 is doped by ion implantation during growth or before forming a gate electrode, and conversely, when forming a P-channel GaAs MISFET, an n-type impurity is doped into the GaAs layer in the same way. Of course, even better characteristics can be obtained by doping with .

Also, in the transistor according to the invention, the source and drain regions are p-doped, in which case the main current carriers in the channel are holes.

In the CaxSr+-xFz film, the surface energy of the (111) plane is the smallest, so as in this example, (
111) Ca, Sr, -x on the B-oriented GaAs layer
When the Fz layer is formed, the Ca)ISr+-XF2 layer is
We believe that the reflected high-speed electron beam (
'RHEED) analysis. For this reason, the generation of a large number of defects introduced as a result of the coalescence of three-dimensionally grown islands, which was noticeable when growing Ca, Sr+-xFz films on conventional (001) substrates, is significantly suppressed. This has made it possible to form a gate insulating layer with good insulation properties. In this case, the resistivity of the single crystal insulating layer 23 is 0.1 to 5.
XIO"Ω·cm, which is about 50 to 100 times larger than the conventional one. Therefore, it has become possible to significantly reduce the gate leakage current of this MISFET.

Because it has become possible to significantly reduce gate leakage current, complementary circuits can significantly reduce the current flowing into the transistor outside the board when the transistor is switched, and GaA
It is possible to realize a circuit that has low power consumption as well as high speed inherent in s.

In this example, since GaAs with (111) plane orientation is used as the substrate on which Ca)(Sr+-xFz is grown,
The CaXSr+-, Fz film grows in layers, forming a steep interface, and as a result of lattice matching, the formation of dangling bonds is suppressed, making it possible to reduce the interface state density. , it has become possible to reduce the threshold voltage value of MISFET and improve controllability. Also,
Because the generation of internal stress near the interface can be suppressed, MISFE
The stability of T operation can be ensured by IC.

Further, in the structure of this embodiment, the CaxSr+-*F2 film 2 is formed in the same vacuum following the GaAs epitaxial layer 22.
When taken out into the atmosphere to grow G.
Cleaning of the aAs/CaXSr 1□F2 interface can be achieved. Furthermore, the CaxSr+-xFz film 23 grows in a layered manner, and the bond at the GaAs boundary between the insulating layer and the semiconductor is strong, and there are few defects in the film, so it can be used as a protective film in this annealing process. , Ga diffuses from the first semiconductor layer 22 under the gate electrode 24 where a channel is formed into the insulating layer 23, and Ga vacancies are generated in the GaAs layer 22, thereby preventing deterioration of the interface characteristics of the GaAs layer 22. A tremendous protective film effect can be obtained.

In this example, a Ca, Sr, -, F, /GaAs heterostructure and a MISFET using the same were described.
Exactly the same effect can be expected by a combination of a zinc blende compound semiconductor film having the 111) orientation or an orientation close to it and a fluorite structure single crystal insulating film. For example, In
Of course, similar effects can be expected even if P, 5rFz+ Garb, and 5rxBa+-xFz are used.

In addition, in this example, the (111) plane was used as an example, but the crystallographically equivalent plane to (111) and the (111)
) It is clear that effects similar to those described above can be obtained for surfaces close to the surface.

(Effects of the Invention) As described above, according to the present invention, a high-speed, low-power field effect transistor is made possible by reducing gate leakage current, improving controllability of dark voltage, and stabilizing operation.

If this device is used in a complementary circuit, it can be
In addition to the low power consumption characteristic of complementary circuits using FETs, the use of GaAs has made it possible to achieve ultra-high-speed operation. Since it has become possible to make the gate insulating film thinner without increasing gate leakage current, a high transconductance value can be achieved, and high drive performance can be obtained when used in digital circuits. Furthermore,
As a result of being able to make the gate insulating film thinner, the gate length can be made smaller than before, making it possible to further improve high-speed performance.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a compound semiconductor field effect transistor of the present invention, and FIG. 2 shows a conventional example. 21... Semi-insulating (111) GaAs substrate crystal 22...
...Undoped (111) Ga that becomes the first layer semiconductor
As 23...Single crystal (111)C that becomes the first insulating film layer
agSr+-xFz (x = 0.5) 24... Gate electrode 25a... Source region 25b... Drain region 26a... Source electrode 26b... Drain electrode 27... Channel

Claims (3)

[Claims] (1) a single crystal substrate; a first semiconductor layer having a zinc blende crystal structure formed on the single crystal substrate;
A first layer having a fluorite crystal structure formed on a semiconductor layer of
an insulating layer, a gate electrode provided on the first insulating layer, a source region and a drain region provided in the first semiconductor layer, and a source region and a drain region provided in connection with the source region and the drain region, respectively. the first semiconductor layer and the first insulating layer have (11
1) A compound semiconductor field effect transistor characterized by having a plane orientation or a plane orientation close to it. (2) A compound semiconductor field effect transistor according to claim 1, wherein the source region and the drain region are p-doped and the main current carrier in the channel is a hole. (3) Forming a first semiconductor layer having a zincblende crystal structure on a semi-insulating substrate with a (111)B orientation plane by molecular beam epitaxial method; A step of forming a single crystal insulating layer acting as a gate insulating film on the semiconductor layer by molecular beam epitaxial method, and an annealing step of activating ion-implanted impurities using the insulating layer as a protective film. A method for manufacturing a compound semiconductor field effect transistor characterized by: