JP2633009B2 - Compound semiconductor field effect transistor and method of manufacturing the same - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an ultra-high-speed / ultra-high frequency compound semiconductor field-effect transistor using a III-V compound semiconductor, especially GaAs, and a method for manufacturing the same.

(Prior art) Conventionally, compound semiconductors, especially GaAs and an amorphous insulating layer,
For example, a silicon oxide film, an aluminum oxide film, etc.
Attempts have been made to manufacture field effect transistors using the MIS structure. However, it is difficult to remove defects, natural oxide films, disorder, and the like existing at the interface between GaAs and the amorphous insulating layer, resulting in a high interface state density. In a GaAs field-effect transistor (GaAs MISFET) using an MIS structure composed of a GaAs / GaAs interface, a favorable inversion layer serving as a channel could not be formed, and it was difficult to realize transistor operation (for example, Hideki Hasegawa) , Applied Physics, Vol. 50, No. 12, "MIS Interface of III-V Semiconductors and Its Application").

In order to overcome this, as shown in FIG. 2, a single crystal insulating layer having a fluorite structure, for example, single crystal calcium fluoride CaF ₂ is formed on a semi-insulating GaAs substrate having a (100) orientation by a molecular beam epitaxial method. Fabrication of GaAs MISFET using heterostructure formed by (MBE) has been attempted (T. Waho a
nd F. Yanagawa, IEEE EDL-9, No. 10 (1988) p.548 “A Ga
As MISFET using an MBE-grown CaF ₂ gate insulator
layer ").

Such a GaAs MISFET structure has an undoped (100) GaAs semiconductor layer 12 and a single crystal fluoride film C on a semi-insulating GaAs substrate 11.
Using a heterostructure in which aF ₂ 16 is formed continuously, ion implantation of ions serving as impurities is performed using the gate electrode 17 as a mask, followed by high-temperature annealing for activating impurities, and the source is self-aligned. After forming the region 13a and the drain region 13b, the source electrode 14a and the drain region 14b
Is obtained. This GaAs MISFET performs the same operation as a normal FET by applying a predetermined positive voltage to the gate electrode 17 and forming a channel 15 in the semiconductor layer 12 below the gate electrode.

(Problems to be Solved by the Invention) However, such a conventional GaAs MISFET structure using CaF ₂ grown on a (100) GaAs semiconductor layer as a gate insulating film has the following problems.

(B) gate leakage current I _g is large, the performance of the transistor (transconductance g _m power consumption) is reduced.

(B) It is difficult to greatly reduce the interface state density, the threshold voltage is high, and the manufacturing variation is large.

(C) The transistor characteristics are unstable.

In the manufacture of GaAs MISFETs, the heat treatment for activating the impurities implanted to form the source and drain regions requires the above-mentioned amorphous material for the purpose of preventing evaporation of the V group element having a high vapor pressure. A method using an insulating film, a so-called face-to-face method of covering with a compound semiconductor substrate of the same kind, and the like are employed. There is a problem that impurities are inevitably mixed into the semiconductor surface, and have a serious adverse effect on the electrical characteristics of the compound semiconductor / insulator interface, and further on the MISFET characteristics.

SUMMARY OF THE INVENTION The present invention has been proposed to improve the above-mentioned disadvantages, and has as its object to reduce the gate leakage current, lower the threshold voltage, and stabilize the operation of the device. It is an object of the present invention to provide a realization and a manufacturing method thereof.

(Means for Solving the Problems) To achieve the above object, the present invention provides a single crystal substrate,
A first semiconductor layer having a zinc blende type crystal structure formed on the single crystal substrate; a first insulating layer having a fluorite type crystal structure formed on the first semiconductor layer; First
A gate electrode provided on the insulating layer, a source region and a drain region provided in the first semiconductor layer, and a source electrode and a drain electrode provided in connection with the source region and the drain region, respectively. Wherein the first semiconductor layer and the first insulating layer have a (111) plane or a plane orientation close to the (111) plane.

Further, the present invention provides a step of forming a first semiconductor layer having a zinc-blende-type crystal structure on a (111) B-oriented semi-insulating substrate by a molecular beam epitaxy method, and subsequently, forming the first semiconductor layer in the same vacuum. A step of forming a single-crystal insulating layer acting as a gate insulating film on the semiconductor layer by molecular beam epitaxy; and an annealing step of activating ion-implanted impurities using the insulating layer as a protective film. An object of the present invention is to provide a method of manufacturing a compound semiconductor field-effect transistor characterized by including the above.

(Action) The most important feature of the present invention is that the (111)
The surface energy of the plane is the lowest compared to the surface energies of the other plane orientations, and the crystal structure deposited on the fluorite-type single crystal is similar to that of the zinc blende type compound semiconductor. The structure of a compound semiconductor field-effect transistor using a steep compound semiconductor layer / single-crystal insulating layer heterostructure formed in a layered mode throughout the entire process. Accordingly, the uniformity of the single crystal insulating layer is significantly improved, and a high resistivity can be realized. As a result, the gate leakage current can be reduced.

Due to the above characteristics, and at the same time, as a second characteristic, lattice matching with the semiconductor layer is performed by using a mixed crystal insulating layer of a plurality of insulators having a fluorite type crystal structure. Couple (dangling bond) at different interfaces
Has the effect of reducing the threshold by reducing the interface state density, and has the effect of suppressing the generation of stress and improving the stability of transistor characteristics.

With the above effects, unprecedented high speed,
A field-effect transistor having low power consumption can be realized.

(Example) Next, an example of the present invention will be described. It should be noted that the embodiments are merely examples, and it is needless to say that various changes or improvements can be made without departing from the spirit of the present invention.

FIG. 1 is a diagram for explaining an embodiment of the present invention. For the method to realize this structure, first, the interface formation method, then the FET
The order of the structure forming method will be described.

First, semi-insulating (111) B by pull-up sealing (LEC)
Undoped first semiconductor layer on GaAs crystal substrate 21
The GaAs layer 22 is homoepitaxially grown by the molecular beam epitaxy method, and then calcium strontium fluoride Ca _x Sr _1-x F ₂ is grown by the molecular beam epitaxy method to form a single crystal insulating layer (as a gate insulating film). (Acting) 23. For the formation of the semiconductor layer 22, a growth condition generally used, for example, a substrate temperature of 650 ° C., a growth rate of about 0.6 μm / h, and a film thickness of 0.7 μm is used. GaAs at this time
Layer 22 has a conductivity type of P and a carrier concentration of 10 ¹⁴ -10 ¹⁵ cm ^-3 . The growth conditions for the single-crystal Ca _x Sr _1-x F ₂ film 23 include:
For example, substrate temperature 500 ° C, growth rate 0.06μm / h, film thickness 60nm
Is used. Under these or similar conditions,
Both the semiconductor layer and the single crystal insulating layer are aligned with the substrate orientation (111), and a semiconductor / insulator interface grown with the (111) plane orientation can be formed.

It is preferable that the lattice constant of the single crystal insulating layer having the first fluorite structure is lattice-matched to the lattice constant of the first zinc-blende semiconductor layer within a range of ± 0.5%.

Further, the first zinc-blende semiconductor layer is made of GaAs, the single-crystal insulating layer having the first fluorite structure is calcium strontium fluoride, and the ratio of calcium to strontium is reduced. , 1: (0.9 to 1.3).

Molecular beam sources used for molecular beam epitaxy include:
High-purity calcium fluoride CaF ₂ and high-purity strontium fluoride SrF ₂ are used. By controlling the cell temperature of each molecular beam source, the composition ratio x of Ca and Sr can be set to an arbitrary value with an accuracy within ± 3%. Here, x is set according to the growth temperature.
For example, by setting the temperature to about 0.44 at room temperature and about 0.56 at about 600 ° C., lattice matching between Ca _x Sr ₁ -xF ₂ and GaAs can be achieved.

The FET fabrication includes a refractory metal gate self-alignment process (eg, the 1981 ISS CC Technical Digest “Ase
lf-aligned source / drain planar device for ultra-
A process similar to high-speed GaAs MESFET VLSI's ") is employed.

First, a refractory metal film WSi is formed on the entire surface by a sputtering method, and a gate electrode 24 is formed by a usual reactive ion etching (RIE) method. Next, Si ions are implanted as n-type impurities, for example, under conditions of an energy of 50 KeV and a dose of 4 × 10 ¹³ cm ⁻² , and the gate electrode 24 is ion-implanted. Using the insulating layer 23 as a protective film, the source region 25a and the drain region 25b are formed in a self-aligned manner, for example, at 650 ° C. to 800 ° C. for 4 to 10 seconds.

In this annealing step, the single crystal insulating layer 23 is
Used as a surface protective film for 22.

Further, using a resist as a mask, the single crystal fluoride mixed crystal layer is etched with an HCl-based etchant to open contact windows with the source region and the drain region.
By forming the source electrode 26a and the drain electrode 26b for the ohmic contact made of Ni and the wiring made of Ti / Au, an N-channel GaAs MISFET structure can be realized. Due to such a structure, a predetermined positive voltage is applied to the gate electrode, for example, 0.
When a value of 9 V or more is applied, an N-type channel 27 is formed in the first semiconductor layer 22 near the insulating layer 23 below the gate electrode 24, and a normal FET operation can be obtained.

Similarly, when fabricating a P-channel GaAs MISFET, Be ions serving as p-type impurities are substituted for n-type impurities in the above-described impurity ion implantation step of MISFET fabrication.
By implanting ions at an energy of 30 KeV and a dose of 2 × 10 ¹³ cm ^-2 and using AuZn for the ohmic electrode,
realizable.

In addition, the above-mentioned N-channel and P-channel MISF
The ET formed on the same hetero substrate, each with H ⁺ ion implantation or the like
By separating the elements of the MISFET and connecting them to each other with Ti / Au wiring electrodes,
A complementary circuit using SFET can be realized. At this time, in the case of forming an N-channel GaAs MISFET, the GaAs layer formed by homoepitaxial growth in which a channel is formed is 10 ^{15 to} 7 × 10
^{A 16} / cm ³ p-type impurity is doped by ion implantation at the time of growth or before the formation of a gate electrode.
When a GaAs MISFET is formed, needless to say, better characteristics can be obtained by doping the GaAs layer with an n-type impurity.

Also, in the transistor according to the invention, the source and drain regions are doped p-type, in which case the main current carriers in the channel are holes.

In the Ca _x Sr _{1 -x} F ₂ film, since the surface energy of the (111) plane is the smallest, the Ca _x Sr _{1 -x} F ₂ layer is formed on the (111) B oriented GaAs layer as in this embodiment. When formed, Ca _x Sr _1-x F ₂
We confirmed by reflection high-energy electron beam (RHEED) analysis that the layers were grown in layers from the first layer to a thickness of 5 to 50 nm required for the gate insulating layer. For this reason, the conventional (00
1) The generation of a large number of defects introduced with the coalescence of the three-dimensionally grown islands, which was remarkable when growing the Ca _x Sr _1-x F ₂ film on the substrate, was greatly suppressed, and was favorable. It is possible to form a gate insulating layer having excellent insulating characteristics. In this case, the resistivity of the single crystal insulating layer 23 is 0.1 to 5 × 10 ¹³ Ω · cm, which is
It was 100 to 100 times larger. For this reason, the gate leakage current of the present MISFET can be significantly reduced.

Gate-leakage current can be greatly reduced, so in a complementary circuit, the current flowing through the transistor can be greatly reduced except when the transistor switches, and GaAs
A circuit having low power consumption as well as the inherent high speed can be realized.

In this embodiment, as a substrate on which Ca _x Sr _1-x F ₂ is grown (11
1) Since GaAs with plane orientation is used, the Ca _x Sr _1-x F ₂ film grows in layers and has a steep interface, and further, as a result of lattice matching, the formation of dangling bonds is suppressed. It is possible to reduce the interface state density,
The threshold voltage of the MISFET can be reduced and controllability can be improved. Further, since the generation of internal stress near the interface can be suppressed, the stability of the MISFET operation can be ensured.

In the structure of this embodiment, the GaAs epitaxial layer 22
Then, to grow the Ca _x Sr _1-x F ₂ film 23 in the same vacuum, when taken out to the atmosphere, C, O, unavoidable surface
The adsorption of H ₂ O and the like can be prevented, and the GaAs / Ca _x Sr _1-x F ₂ interface can be cleaned. Further, the Ca _x Sr _1-x F ₂ film 23 grows in a layered manner, and the bond between the insulating layer and the semiconductor at the GaAs boundary is strong,
Further, since there are few defects in the film, Ga is used as a protective film in this annealing step, so that Ga is removed from the first semiconductor layer 22 under the gate electrode 24 where a channel is formed.
The GaAs layer 22 is diffused into the GaAs layer 22 to generate Ga vacancies, which can prevent the interface characteristics of the GaAs layer 22 from deteriorating.

In this embodiment, the Ca _x Sr _1-x F ₂ / GaAs heterostructure and the MISFET using the same have been described. However, a zinc blende type compound semiconductor film having a (111) orientation or an orientation close thereto and a fluorite structure Exactly the same effect can be expected by combining the single crystal insulating films. For example, InP and SrF ₂ , GaSb and Sr _x Ba _1-x F ₂
Of course, a similar effect can be expected even if is used.

In the present embodiment, the (111) plane has been described as an example, but the plane crystallographically equivalent to the (111) plane and the plane close to the (111) plane have also been described so far. It is clear that the same effect as the effect can be obtained.

(Effects of the Invention) As described above, according to the present invention, a high-speed, low-power field-effect transistor has been made possible by reducing gate leakage current, improving controllability of threshold voltage, and stabilizing operation. If this element is used in a complementary circuit, it will
In addition to the low power consumption characteristic of complementary circuits using SFETs, it has become possible to achieve ultra-high-speed operation using GaAs. Since the thickness of the gate insulating film can be reduced without increasing the gate leakage current, a high transconductance value can be realized, and a high driving capability can be obtained when used in a digital circuit. Furthermore, as a result of the gate insulating film being thinner, the gate flow can be reduced more than before, and the high-speed performance can be further improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a compound semiconductor field effect transistor of the present invention, and FIG. 2 shows a conventional example. 21: semi-insulating (111) GaAs substrate crystal 22: undoped (111) GaAs to be the first semiconductor layer 23: single crystal (111) Ca _x Sr _1-x to be the first insulating film layer F
₂ (x = 0.5) 24 gate electrode 25a source region 25b drain region 26a source electrode 26b drain electrode 27 channel

Claims (3)

(57) [Claims] 1. A single crystal substrate, a first semiconductor layer having a zinc blende type crystal structure formed on the single crystal substrate, and a fluorite type crystal structure formed on the first semiconductor layer A first insulating layer, a gate electrode provided on the first insulating layer, a source region and a drain region provided in the first semiconductor layer, and a source region and a drain region, respectively. A compound semiconductor field-effect transistor comprising a source electrode and a drain electrode provided in series, wherein the first semiconductor layer and the first insulating layer have a (111) plane or a plane orientation close to the (111) plane. . 2. The compound semiconductor field effect transistor according to claim 1, wherein the source region and the drain region are doped p-type, and the main current carrier in the channel is a hole. . 3. A step of forming a first semiconductor layer having a zinc-blende-type crystal structure on a semi-insulating substrate having a (111) B orientation plane by a molecular beam epitaxial method. A step of forming a single-crystal insulating layer acting as a gate insulating film on the semiconductor layer by molecular beam epitaxy; and an annealing step of activating ion-implanted impurities using the insulating layer as a protective film. A method for manufacturing a compound semiconductor field effect transistor, comprising: