WO2002015233A2 - Integrated transistor devices - Google Patents
Integrated transistor devices Download PDFInfo
- Publication number
- WO2002015233A2 WO2002015233A2 PCT/US2001/025150 US0125150W WO0215233A2 WO 2002015233 A2 WO2002015233 A2 WO 2002015233A2 US 0125150 W US0125150 W US 0125150W WO 0215233 A2 WO0215233 A2 WO 0215233A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- compound semiconductor
- oxide
- layer
- field effect
- effect transistor
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 145
- 150000001875 compounds Chemical class 0.000 claims abstract description 94
- 230000005669 field effect Effects 0.000 claims abstract description 49
- 239000012212 insulator Substances 0.000 claims abstract description 49
- XCZLSTLZPIRTRY-UHFFFAOYSA-N oxogallium Chemical compound [Ga]=O XCZLSTLZPIRTRY-UHFFFAOYSA-N 0.000 claims abstract description 38
- 239000003870 refractory metal Substances 0.000 claims abstract description 25
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 claims abstract description 9
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical class [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910001195 gallium oxide Inorganic materials 0.000 claims abstract description 7
- 239000000203 mixture Substances 0.000 claims abstract description 7
- 229910005224 Ga2O Inorganic materials 0.000 claims abstract description 5
- 229910052761 rare earth metal Inorganic materials 0.000 claims description 20
- 150000002500 ions Chemical class 0.000 claims description 18
- 239000007943 implant Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 17
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 16
- 229910052760 oxygen Inorganic materials 0.000 claims description 16
- 239000001301 oxygen Substances 0.000 claims description 16
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 15
- 229910052733 gallium Inorganic materials 0.000 claims description 15
- 230000000295 complement effect Effects 0.000 claims description 14
- 125000006850 spacer group Chemical group 0.000 claims description 10
- 229910052731 fluorine Inorganic materials 0.000 claims description 4
- -1 metal-oxide compound Chemical class 0.000 claims description 3
- 230000007547 defect Effects 0.000 claims description 2
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000002927 oxygen compounds Chemical class 0.000 claims 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 abstract description 14
- 241001101998 Galium Species 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 69
- 238000005516 engineering process Methods 0.000 description 12
- 238000000151 deposition Methods 0.000 description 11
- 230000008021 deposition Effects 0.000 description 11
- 230000010354 integration Effects 0.000 description 11
- 238000000034 method Methods 0.000 description 9
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000002207 thermal evaporation Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 150000002910 rare earth metals Chemical class 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 230000004907 flux Effects 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- ZPDRQAVGXHVGTB-UHFFFAOYSA-N gallium;gadolinium(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Gd+3] ZPDRQAVGXHVGTB-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910052688 Gadolinium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010549 co-Evaporation Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- UIWYJDYFSGRHKR-UHFFFAOYSA-N gadolinium atom Chemical compound [Gd] UIWYJDYFSGRHKR-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/802—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
Definitions
- the present invention pertains to low power and high speed integrated circuits in the compound semiconductor field utilizing field effect transistors and more specifically complementary field effect transistors used in concert including enhancement mode self- aligned metal-oxide-compound semiconductor transistors and depletion mode self-aligned metal-oxide-compound semiconductor transistors and methods of materials growth and fabrication of said structures and the ultra large scale integration of said transistors.
- the gallium arsenide and indium phosphide integrated circuit industry has been limited without a technology that simultaneously allows the integration of complementary field effect transistor devices and transistors with low gate leakage currents.
- CMOS complementary metal oxide semiconductor
- FETs Field effect transistor
- III-V semiconductor industry employ metal gates and Schottky gate contacts that are have quiescent-state leakage currents exceeding many microamps.
- the use of metal gates in compound semiconductor technology further results in individual transistors and integrated circuits that have excessively high power dissipation, reduced transconductance, reduced logic swing and the inability to operate on a single power supply, and generally limited performance characteristics.
- CMOS complementary metal-oxide-semiconductor
- FIG. 1 is simplified cross sectional view of a self-aligned enhancement mode compound semiconductor MOSFET in accordance with a preferred embodiment of the present invention
- FIG. 2 is a simplified flow chart illustrating a method of manufacturing a self-aligned enhancement mode compound semiconductor MOSFET in accordance with a preferred embodiment of the present invention.
- the exemplification set out herein illustrates a preferred embodiment of the invention in one form thereof, and such exemplification is not intended to be construed as limiting in any manner.
- the present invention provides, among other things, a self-aligned enhancement mode metal-oxide-compound semiconductor FET.
- the FET includes a gallium oxygen insulating structure that is composed of at least two distinct layers.
- the first layer is most preferably more that 10 angstroms thick but less that 25 angstroms in thickness and composed substantially of gallium oxygen compounds including but not limited to stoichiometric Ga 2 O 3 and Ga 2 O, and possibly a lesser fraction of other gallium oxygen compounds.
- the upper insulating layer in the gallium oxide insulating structure is composed of an insulator that does not intermix with the underlying gallium oxygen insulating structure.
- This upper layer must possess excellent insulating qualities, and is most typically composed of gallium oxygen and a third rare earth element that together form a ternary insulating material. Therefore the entire gallium oxide rare earth gate insulator structure is composed of at least two layers and may contain a third intermediate graded layers that consists of a mixture of the upper insulating material and the gallium oxygen compounds that compose the initial layer. Together the initial gallium oxygen layer, any intermediate graded layer and the top insulating region form both a gallium oxide insulating structure and the gate insulator region of a metal-oxide- compound semiconductor field effect transistor.
- the initial substantially gallium oxygen layer forms an atomically abrupt interface with the top layer of the compound semiconductor wafer structure, and does not introduce midgap surface states into the compound semiconductor material.
- a refractory metal gate electrode is preferably positioned on the upper surface of the gate insulator structure layer.
- the refractory metal is stable on the gate insulator structure layer at elevated temperature.
- Self-aligned source and drain areas, and source and drain contacts are positioned on the source and drain areas.
- the metal-oxide-compound semiconductor transistor includes multilayer gate insulator structure including an initial gallium oxygen layer, intermediate transition layer, and upper insulating layer of 30-250 angstroms in thickness positioned on upper surface of a compound semiconductor heterostructure that form the gate insulator structure.
- the preferred embodiment also comprises a compound semiconductor heterostructure including a GaAs, Al x Ga ⁇ -x As and In y Ga ⁇ -y As layers with or wothout n-type and/or p-type charge supplying layers which are grown on a compound semiconductor substrate, a refractory metal gate of W, WN, or WSi, self aligned donor (n-channel FET) or acceptor (p- channel FET) implants, and source and drain ohmic contacts.
- the compound semiconductor heterostructure comprises an friyGaj.
- y As, ALIn ⁇ x As, and InP compound semiconductor heterostructure and n-type and/or p-type charge supplying layers which are grown on an InP substrate, and a refractory metal gate of W, WN, or WSi, self aligned donor (n-channel FET) or acceptor (p-channel FET) implants, and source and drain ohmic contacts.
- FIG. 1 is simplified cross sectional view of a self-aligned enhancement mode compound semiconductor MOSFET in accordance with a preferred embodiment of the present invention.
- Device 10 includes a compound semiconductor material, such as any III-V material employed in any semiconductor device, represented herein by a III-V semiconductor substrate 11 and a compound semiconductor epitaxial layer structure 12.
- a compound semiconductor wafer structure which in FIG. 1 is designated 13.
- Methods of fabricating semiconductor wafer structure 13 include, but are not limited to, molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD).
- Device H) further comprises a gate insulator structures (30) that includes at least two or more layers.
- the first layer of the gate insulator structure (31) is composed entirely of gallium oxide compounds and is directly adjacent to and deposited upon the compound semiconductor structure.
- the second layer of the gate insulator structure (32) is composed of a compound of gallium, oxygen, and one or more rare earth elements from the periodic table.
- the initial gallium oxygen layer (31) forms an atomically abrupt interface 14 with the upper surface of top layer 15, the top layer of the compound semiconductor structure.
- a refractory metal gate electrode 17 which is stable in the presence of top insulating material at elevated temperature is positioned on upper surface 18 of the gate insulator structure.
- Dielectric spacers 26 are positioned to cover the sidewalls of metal gate electrode 17.
- Source and drain contacts 19 and 20 are deposited on self-aligned source and drain areas 21 and 22, respectively.
- the compound semiconductor epitaxial layer structure consists of a ⁇ 11 angstrom GaAs top layer (15), a ⁇ 101 angstrom Al x Ga 1-x As spacer layer (23), a ⁇ 251 angstrom In y Ga 1-y As channel layer (24), and a GaAs buffer layer (25) grown on a GaAs substrate (11).
- Top GaAs layer (15) is used to form an atomically abrupt layer with the gate insulator structure with an abrupt interface with low defect density.
- a III-V compound semiconductor wafer structure 13 with an atomically ordered and chemically clean upper surface of top layer 15 is prepared in an ultra-high vacuum semiconductor growth chamber and transferred via a ultra high vacuum transfer chamber to a second ultra high vacuum oxide and insulator deposition chamber.
- the initial gallium oxygen layer (31) is deposited on upper compound semiconductor surface layer 15 using thermal evaporation from a high purity Ga 2 O 3 source or from crystalline gadolinium gallium garnet, Ga 3 Gd 5 O ⁇ 2 .
- This initial gallium oxygen layer is deposited while holding the substrate temperature of the compound semiconductor structure at ⁇ 580°C, and most preferably at a substrate temperature ⁇ 495°C.
- deposition of the second insulator layer is initiated.
- the deposition of the -second insulator layer starts by directing the flux from a low power oxygen plasma source into the ultra high vacuum system such that the oxygen plasma effluent and species are largely directed toward and impinging upon said compound semiconductor structure with initial gallium oxygen layer.
- the flux from the oxygen plasma source should be directed at the surface for between 2-5 seconds, subsequently followed by the co-evaporation of gallium oxygen compounds from Ga 2 O 3 and a second thermal evaporation source that contains a rare-earth element.
- the flux beams from the oxygen source, Ga 2 O 3 and rare-earth evaporation source thermal evaporation sources are carefully balanced to provide a ternary insulator layer on top of the initial gallium oxygen layer on said compound semiconductor structure.
- the substrate temperature is simultaneously adjusted to provide an optimized substrate temperature for the deposition of this layer.
- the substrate temperature required to deposit the gallium+oxygen+rare earth layer is ⁇ 530°C.
- this second insulator layer proceeds until the total insulator thickness of 200-250 angstroms is achieved.
- Shutters and valves are utilized to stop the deposition of the ternary gallium+oxygen+rare earth layer upon the deposition of the required thickness of the insulator layer.
- the substrate temperature is cooled in-vacuum to approximately 200°C, and the deposition of a refractory metal which is stable and does not interdiffuse with on the top layer of the gate insulator structure at elevated temperature such as WSi or WN is deposited on upper surface 18 of oxide layer 32 and subsequently patterned using standard lithography.
- the refractory metal layer is etched until oxide layer 31 is exposed using a refractory metal etching technique such as a fluorine based dry etching process.
- the refractory metal etching procedure does not etch the oxide layer 31, thus, oxide layer 31 functions as an etch stop layer such that upper surface of top layer 15 remains protected by oxide layer 31. All processing steps are performed using low damage plasma processing.
- Self-aligned source and drain areas 21 and 22, respectively are realized by ion implantation of Si (n-channel device) and Be/F or C/F (p-channel device) using the refractory metal gate electrode 17 and the dielectric spacers 26 as implantation masks.
- Such ion implantation schemes are compatible with standard processing of complementary compound semiconductor heterostructure FET technologies and are well known to those skilled in the art.
- the implants are activated at 700-900°C using rapid thermal annealing in an ultra high vacuum environment such that degradation of the interface 16 established between top layer 15 and oxide layer 31 is completely excluded.
- ohmic source and drain contacts 19 and 20 are deposited on the self-aligned source and drain areas 21 and 22, respectively.
- the devices may then be interconnected using the standard methods to those skilled in the art of integrated microelectronics and integrated circuit manufacture.
- FIG. 2 is a simplified flow chart illustrating a method of manufacturing a self-aligned enhancement mode compound semiconductor MOSFET in accordance with a preferred embodiment of the present invention.
- a compound semiconductor wafer structure is produced using standard epitaxial growth methods in the art.
- a layer consisting of gallium oxygen compounds including but not limited to Ga 2 O 3 and Ga 2 O is deposited on upper surface of said compound semiconductor wafer structure.
- an insulating layer of gallium oxygen and one or more rare earth elements is deposited on the upper surface of the initial gallium oxygen compound layer.
- the gallium oxide gate insulator structure is formed in steps 104 and 105.
- a stable refractory gate metal is positioned on upper surface of said gate insulator structure.
- source and drain ion implants are provided self-aligned to the gate electrode.
- source and drain ohmic contacts are positioned on ion implanted source and drain areas.
- step 100 provides a compound semiconductor substrate such as GaAs or InP.
- Step 102 includes the preparation and epitaxial growth of an atomically ordered and chemically clean upper surface of the compound semiconductor wafer structure.
- Step 103 preferably comprises thermal evaporation from a purified and crystalline gadolinium gallium garnet or Ga 2 O 3 source on an atomically ordered and chemically clean upper surface of the compound semiconductor wafer structure.
- Step 104 comprises the formation of a gallium+oxygen+rare earth elemental insulating layer formed through the simultaneous vacuum evaporation of gallium oxygen species and at least one rare earth element such as Gadolinium with the simultaneous oxidation using the effluent of an oxygen gas plasma source directed in simultaneous combination with other thermal evaporation sources toward substrate 100.
- the initial gallium oxygen compound layer of the gate insulator structure preferably functions as an etch stop layer such that the upper surface of the compound semiconductor wafer structure remains protected by the gate oxide during and after gate metal etching.
- the refractory gate metal desirably does not react with or diffuse into the gate oxide layer during high temperature annealing of the self-aligned source and drain ion implants.
- the quality of the interface formed by the gate oxide layer and the upper surface of the compound semiconductor structure is desirably preserved during high temperature annealing of the self-aligned source and drain ion implants.
- the self-aligned source and drain implants are desirably annealed at approximately 700°C in an ultra high vacuum environment.
- the self-aligned source and drain implants are desirably realized by positioning dielectric spacers on the sidewalls of the refractory gate metal.
- new and improved compound semiconductor devices and methods of fabrication are disclosed.
- the new and improved self-aligned enhancement mode metal- oxide-compound semiconductor heterostructure field effect transistors enable stable and reliable device operation, provide optimum compound semiconductor device performance for low power/high performance complementary circuits and architectures, keep interconnection delay in ULSI under control, and provide optimum efficiency and output power for RF and microwave applications as well as for digital integrated circuits that require very high integration densities.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2001288239A AU2001288239A1 (en) | 2000-08-10 | 2001-08-10 | Integrated transistor devices |
JP2002520272A JP2004507081A (en) | 2000-08-10 | 2001-08-10 | Integrated transistor device |
EP01967960A EP1312122A4 (en) | 2000-08-10 | 2001-08-10 | Integrated transistor devices |
KR10-2003-7001947A KR20030027017A (en) | 2000-08-10 | 2001-08-10 | Integrated transistor devices |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/636,484 US6936900B1 (en) | 2000-05-04 | 2000-08-10 | Integrated transistor devices |
US09/636,484 | 2000-08-10 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002015233A2 true WO2002015233A2 (en) | 2002-02-21 |
WO2002015233A3 WO2002015233A3 (en) | 2002-06-27 |
Family
ID=24552107
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2001/025150 WO2002015233A2 (en) | 2000-08-10 | 2001-08-10 | Integrated transistor devices |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1312122A4 (en) |
JP (1) | JP2004507081A (en) |
KR (1) | KR20030027017A (en) |
AU (1) | AU2001288239A1 (en) |
WO (1) | WO2002015233A2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003063227A2 (en) * | 2002-01-22 | 2003-07-31 | Massachusetts Institute Of Technology | A method of fabrication for iii-v semiconductor surface passivation |
WO2005093851A1 (en) * | 2004-03-12 | 2005-10-06 | Hewlett-Packard Development Company, L.P. | Semiconductor device having channel including gallium oxide |
US7187045B2 (en) | 2002-07-16 | 2007-03-06 | Osemi, Inc. | Junction field effect metal oxide compound semiconductor integrated transistor devices |
US7190037B2 (en) | 2000-05-04 | 2007-03-13 | Osemi, Inc. | Integrated transistor devices |
CN116072707A (en) * | 2023-02-08 | 2023-05-05 | 厦门大学 | Planar SiC MOSFET containing rare earth gate dielectric layer and manufacturing method thereof |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6756320B2 (en) * | 2002-01-18 | 2004-06-29 | Freescale Semiconductor, Inc. | Method of forming article comprising an oxide layer on a GaAs-based semiconductor structure |
US7382001B2 (en) * | 2004-01-23 | 2008-06-03 | International Rectifier Corporation | Enhancement mode III-nitride FET |
JP7067702B2 (en) * | 2017-06-30 | 2022-05-16 | 国立研究開発法人物質・材料研究機構 | Gallium nitride based semiconductor device and its manufacturing method |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5665658A (en) * | 1996-03-21 | 1997-09-09 | Motorola | Method of forming a dielectric layer structure |
US5945718A (en) * | 1998-02-12 | 1999-08-31 | Motorola Inc. | Self-aligned metal-oxide-compound semiconductor device and method of fabrication |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5962883A (en) * | 1994-03-23 | 1999-10-05 | Lucent Technologies Inc. | Article comprising an oxide layer on a GaAs-based semiconductor body |
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2001
- 2001-08-10 WO PCT/US2001/025150 patent/WO2002015233A2/en active Application Filing
- 2001-08-10 KR KR10-2003-7001947A patent/KR20030027017A/en not_active Application Discontinuation
- 2001-08-10 EP EP01967960A patent/EP1312122A4/en not_active Withdrawn
- 2001-08-10 AU AU2001288239A patent/AU2001288239A1/en not_active Abandoned
- 2001-08-10 JP JP2002520272A patent/JP2004507081A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5665658A (en) * | 1996-03-21 | 1997-09-09 | Motorola | Method of forming a dielectric layer structure |
US5945718A (en) * | 1998-02-12 | 1999-08-31 | Motorola Inc. | Self-aligned metal-oxide-compound semiconductor device and method of fabrication |
Non-Patent Citations (1)
Title |
---|
See also references of EP1312122A2 * |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7190037B2 (en) | 2000-05-04 | 2007-03-13 | Osemi, Inc. | Integrated transistor devices |
WO2003063227A2 (en) * | 2002-01-22 | 2003-07-31 | Massachusetts Institute Of Technology | A method of fabrication for iii-v semiconductor surface passivation |
WO2003063227A3 (en) * | 2002-01-22 | 2004-04-15 | Massachusetts Inst Technology | A method of fabrication for iii-v semiconductor surface passivation |
US6933244B2 (en) | 2002-01-22 | 2005-08-23 | Massachusetts Institute Of Technology | Method of fabrication for III-V semiconductor surface passivation |
US7187045B2 (en) | 2002-07-16 | 2007-03-06 | Osemi, Inc. | Junction field effect metal oxide compound semiconductor integrated transistor devices |
WO2005093851A1 (en) * | 2004-03-12 | 2005-10-06 | Hewlett-Packard Development Company, L.P. | Semiconductor device having channel including gallium oxide |
US7250627B2 (en) | 2004-03-12 | 2007-07-31 | Hewlett-Packard Development Company, L.P. | Semiconductor device |
CN116072707A (en) * | 2023-02-08 | 2023-05-05 | 厦门大学 | Planar SiC MOSFET containing rare earth gate dielectric layer and manufacturing method thereof |
Also Published As
Publication number | Publication date |
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AU2001288239A1 (en) | 2002-02-25 |
JP2004507081A (en) | 2004-03-04 |
EP1312122A2 (en) | 2003-05-21 |
WO2002015233A3 (en) | 2002-06-27 |
KR20030027017A (en) | 2003-04-03 |
EP1312122A4 (en) | 2006-08-02 |
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