JPH04188716A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a high performance hetero structure transistor and improve heat resistance of a film grown with deformation by covering a single crystal substrate with an amorphous insulating film and providing an opening part through part of said substrate, and further performing hetero epitaxial growth. CONSTITUTION:A single crystal substrate 1 is coated with an amorphous insulating film and an opening part 3 is formed through only a portion which becomes a base or a channel, and thereafter a semiconductor film is formed over the entire surface of the substrate under hetero epitaxial growth conditions. For example, a square opening part 3 is formed through an SiO2 film and a 150nm Si0.9Ge0.2 film is crystal-grown over the entire surface, and as a result an SiO2 film is provided to limit a single crystal growth region in a square small region. Hereby, misfitting dislocation is sharply reduced. Particularly, in one crystal- grown for an about 1mum radius circular opening part no misfitting dislocation is observed. Hereby, hetero effect and deformation effect can effectively be utilized and heat resistance of the hetero structure can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device using a semiconductor heterostructure and a method for manufacturing the same.

[Conventional technology]

In recent years, hetero bipolar transistors (HBTs) have been developed.

Alternatively, transistors using semiconductor heterostructures, such as modulated top transistors (MODEFETs or HEMTs), are attracting attention as high-speed, highly integrated devices. The semiconductor material used is also G a A s / A
From Q Ga As system to InGaAs system, 5iGe
It is expanding into the system. The latter uses GaAs or S as a substrate.
It is a so-called strained hetero system having a lattice constant different from that of i and Ge. The film grows under strain when it is below the critical thickness, and when it becomes thicker, misfit dislocations occur and the strain is relaxed. The possibility that strain in films can be used effectively to control electronic properties, such as increasing the value of band discontinuity between heterojunctions and decreasing the effective mass of holes, is attracting attention. Therefore, a technique that suppresses the occurrence of misfit dislocations and utilizes the strain while retaining the strain is important.

Figure 2 is an example (International, Electron Devices, Meeting, Technical Digest (19
1987) pages 874 to 876 (IEDN'87)
Tech, Dig, (1987) pp874-8
76) shows a cross-sectional structure of a hetero bipolar transistor using Si, , □Geo, □2 as a base. Si emitter 22, S 1 o, maG e
o, 1* due to the band discontinuity of the valence band with base 21.

Hole injection from the base to the emitter is suppressed, achieving high emitter injection efficiency.

Moreover, FIG. 2 shows an example of a 5-strain heterostructure FET (IEE Electron Device Letters EDL-7 (1986), pages 308 to 310 (IEEE Electron Device Letters EDL-7 (1986), pages 308 to 310).
Lett, EDL-7 (1986) PP308-
3103), Si substrate 20, Si,...G
e, P-type Sio, 2G created by heteroepitaxially growing the channel layer 31 and the P-type Si layer 32
It has been recognized that a two-dimensional hole gas (2DHG) is formed at the interface and operates as a MODFET. Here, the channel layer 31 has a thickness of 2G less than the critical film thickness for strain growth on the Si substrate 20.
It is formed to a thickness of 50 people.

[Problem to be solved by the invention]

However, in the HBT having the above structure, the band discontinuity value ΔEv between S i /S l , maG e'o, 1□ was as low as about 0.1 eV, and the effect of the heterostructure was insufficient.

In addition, the MODFET with the above structure has a low sheet carrier concentration of 2.5×10°cm-” and a low mutual conductance g of 2.5 mS/mm. This is because S i / S ig, sG This is because the band discontinuity ΔEv between eO,2 is as small as about 0.15 eV, and a sufficient amount of holes cannot be confined in the potential well.

Therefore, in order to improve the characteristics, increase the X value of Si, -xGex (for HBT, x>0.2, for FET, For ΔEv>0.15eV, for FET ΔE−>
0.2eV)L.

However, if X≧0.2 and x)0.3, then
The critical thickness of the film relative to the Si substrate is as small as 600 or 300 Å or less, making it difficult to strain-grow the film to a sufficient thickness for the base layer and channel layer. Furthermore, even if strain growth occurs (at low temperature) under the condition of x<0.2, there is a problem in that defects occur during subsequent heat treatment.

Therefore, an object of the present invention is to realize a high-performance heterostructure transistor by suppressing the occurrence of misfit dislocations and allowing strained growth even in a film with large lattice misalignment as described above. Another object is to improve the heat resistance of the strain-grown film.

[Means to solve the problem]

In order to achieve the above object, in the present invention, a single crystal substrate 1 shown in FIG. A semiconductor film may be grown under certain conditions.

At this time, it is effective that the area of the opening is 4 μm 2 or less.

Further, it is particularly effective when the difference in lattice constant between the substrate and the semiconductor epitaxially grown on the substrate is in the range of 0.5 to 2%. When the lattice constant is 2% or more, the strain is too large and the effect of reducing misfit dislocations is small. Lattice constant difference is 0.5%
Below, ΔEv cannot be sufficiently increased.

[Effect]

Hereinafter, the effect of the present invention will be explained using the S i G e /S i system as an example.

Square-shaped openings are provided in the SiO2 film, and the entire surface is filled with S.
As a result of growing 150 nm crystals of jo, , geo, and z films, it was found that misfit dislocations were significantly reduced by providing a SiC2 film and limiting the single crystal growth region to a square micro region. In particular, no misfit dislocations were observed in the crystals grown in circular openings with a radius of about 1 μm. Figure 4 shows this result quantitatively.

In this method, polycrystalline 5jGe grows on the Si◯2 film, so that strain-grown single-crystalline 5iGe regions are separated by unstrained polycrystalline 5iGe regions. The strain in the single crystal is relaxed at the boundary between the single crystal 5iGe and the polycrystal, and even if a misfit dislocation occurs in a single crystal region adjacent to a certain single crystal region, the movement will not occur in the polycrystal region. The mechanism of dislocation reduction is that the dislocations are blocked and do not reach this single crystal region.

Furthermore, in FIG. 5, S xo, , G efl, 12
/' The change in dislocation density when the Si film is heat treated is shown.

In the case of epitaxial growth on the entire surface of the Si substrate, the dislocation density increased by about one order of magnitude, whereas in the case of a single crystal in a micro region of 2×2 μm 2 , no change was observed. Thus, it has become clear that this local growth method can also significantly improve the heat resistance of the film.

〔Example〕

[Example 1] First, an example in which a 5iGe-based hetero bipolar transistor is formed according to the present invention will be described with reference to FIG. After forming an n-type buried layer 72 on a P-type Si substrate 71, an n-layer 73 was epitaxially grown to a thickness of 150 nm by MBE (molecular beam epitaxy) at a substrate temperature of 700°C.Next, wet LOG OS was grown.
(Local oxidation of silicon: L
An insulating film 74 for element isolation was formed by oxidation (ocal oxidation of Si) (FIG. 6(a)).

At this time, the shape of the opening 70 is 2×2 μm 2 .

Subsequently, S i , , G eo , z base layer 75 (
30 nm, lXl0"cm-3B doped), n+Si emitter layer 76 (30nm, lXl0"cm-3As
dope) were sequentially grown by MBE.

A single crystal grows on the opening to become the active region (intrinsic base and emitter) of the device, and a polycrystal grows on the insulating film to become the extrinsic base.

Next, 300 nm of n1 polycrystalline 5i77 was deposited by CVD (chemical vapor deposition) (FIG. 2(b)). This was processed by a photolithography process to form an emitter (FIG. 4(C)).

Next, 1iet oxidation, Si, and N4 films 78 were deposited to passivate the emitter base and base-chorephthal n junction ends. Subsequently, B+ ions were implanted into the entire surface to form an external base 79 (FIG. 4(d)). lastly,
AΩ electrode wiring (not shown) was performed.

By using Si,,sGe,,2, the emitter injection efficiency increases, and even if the base concentration is increased to IXl0''cm-3, the common emitter current amplification factor hrE can be maintained at around 100, and ft= Achieved 100GHz.

As a production process, a highly reliable high temperature process (≦800°C) such as wet a was used, but S
There were no misfit dislocations at the Geo, 2/S1 interface, and the pn junction characteristics were good. This is 3 j
This is a specific effect obtained by growing a single crystal of a llG e o , 2 film in a micro area of about 2×2 μm 2 . In addition, when using Sio, 5Ge0°, film,
Heat treatment at about 900°C was also possible.

[Example 2] Next, using FIG. 7, Sl. An example of a P-type MODFET using a channel layer will be described.

P-type S1 substrate 80 is oxidized with LOGO5, and Si○2 film 81 is formed.
Membrane shape 1. The shape of the Si○2 membrane opening 89 serving as a channel is 8×0.5 μm2. Next, by molecular beam epitaxy, at a substrate temperature of 500°C, S l 1), 7 G
EO, 3 film 82, and P-type Si film 87 were grown in sequence. The thickness of each film is 200 people.

There are 300 people. Polycrystalline 83°84 was deposited on the Si○2 film. Subsequently, a Ti gate electrode 88 was deposited by sputtering, an AuGa source/drain 86° 87 was deposited by vacuum evaporation, and annealing was performed at 330° C. to form an AuGa alloy.

Hall effect measurement of a sample with this structure revealed that at 77K, Ns=IX1012cm-2, p=5000cm
"/V・S value was obtained, which was a significant improvement compared to the conventional structure. This is because the X value of the Si-xGex channel was increased to 0.3, and ΔEv=0.25e
This is considered to be because the effective mass of the hole became smaller due to the fact that the hole was V and the compressive strain (approximately 1.2%). As a result of the above, a mutual conductance of 500 mS/mm was achieved for the MODFET.

In addition, as a channel layer, S. ,,Geo,2 films improve heat resistance, so the conventional 51M
A 08FET formation process can be used. That is, as shown in FIG. 8, a gate oxide film and a passivation film 91 were formed by thermal oxidation. Furthermore, a polycrystalline S1 gate 92 is formed, and using this as a mask, B+
A P'' region that will become a source and a train is formed by ion implantation. In particular, in FIG.
The O2 film 81 was made sufficiently thick, and gate processing was performed by an etch-back method after full-surface polycrystalline deposition.

〔Effect of the invention〕

According to the present invention, a film with a large lattice misalignment can be grown epitaxially without misfit dislocations, the hetero effect and strain effect can be effectively utilized, the heat resistance of the hetero structure is improved, and the conventional 5iLSI process is improved.

This will allow you to achieve consistency with the

[Brief explanation of drawings]

Figures 1 (a) and (b) are a sectional view and a plan view of a heterostructure showing the outline of the present invention, Figures 2 and 3 are sectional views of essential parts of a conventional element structure, and Figures 4 and 5 are 6 to 8, which are diagrams for explaining the operation of the present invention, are sectional views of essential parts of elements of embodiments of the present invention. Explanation of symbols

Claims (1)

[Claims] 1. In a method for manufacturing a heterostructure element made of different types of semiconductors with different lattice constants, a single crystal substrate is covered with an amorphous insulating film, an opening is formed in a part of the amorphous insulating film, and then a heterostructure A method of manufacturing a semiconductor device characterized by performing epitaxial growth. 2. In the method for manufacturing a heterostructure element according to claim 1, the lattice constant difference between the substrate and the single crystal thin film is 2%.
A method for manufacturing a semiconductor device, characterized in that the area of the opening is 4 μm^2 or less. 3. In the method for manufacturing a heterostructure element according to claim 2, Si_1_-_xGe_x(
0≦x<0.5) A method for manufacturing a semiconductor device, characterized in that a film is grown. 4. A semiconductor device manufactured by the manufacturing method according to claim 1. 5. A semiconductor device according to claim 4, comprising:
A hotelobipolar transistor characterized in that a base layer is a single crystal region grown heteroepitaxially from the opening. 6. A semiconductor device according to claim 4, comprising:
A field effect transistor characterized in that a channel layer is a single crystal region grown heteroepitaxially from the opening.